Download A Variable Threshold Voltage Inverter For Cmos

TÍTULO DE LA TESIS
“POWER AND TIMING MODELING OF SUBMICRON CMOS GATES”
AUTOR:
Josep Lluís Rosselló
DIRECTOR:
Jaume Segura Fuster
FECHA DE LECTURA
22 de Febrero de 2003
PUBLICACIONES DERIVADAS
REVISTAS
“A Variable Threshold Voltage Inverter for CMOS Programmable Logic Circuits” J.
Segura, J.L. Rosselló, J.Morra, H.Sigg, IEEE Journal of Solid-State Circuits, pp.12621265, vol. 33. no. 8 Agosto 1998
"Charge-based analytical model for the evaluation of power consumption in sub-micron
CMOS buffers" J.L. Rosselló and Jaume Segura IEEE Transactions on Computer Aided
Design of Integrated Circuits and Systems. pp.433-448, vol. 21, no. 4, Abril 2002.
"Simple and accurate propagation delay model for submicron CMOS gates based on
charge analysis" J.L. Rossello and J. Segura, Electronics Letters, IEE, pp. 772-774, Vol.
38, no. 15, Julio 2002
"An analytical charge-based compact delay model for submicron CMOS inverters", J.L.
Rosselló and J Segura, IEEE Transactions on Circuits and Systems I, (Aceptado para su
publicación)
CONGRESOS
Autores: J.L. Rosselló, E. Isern, M. Roca, E. García, J. Segura
Título: An analytical model of the charge driven by CMOS buffers
Tipo de participación: comunicación a congreso
Congreso: XII Design of Circuits and Integrated Systems Conference
Publicación: Proceedings, pp. 471-474
Lugar de celebración: Sevilla
Fecha: Noviembre 1997
Autores: I. De Paul, R. Picos, J.L. Rosselló, M. Roca, E. Isern, J, Segura, C.F. Hawkins
Título: Transient current testing based on current (charge) integration
Tipo de participación: comunicación a congreso
Congreso: International Workshop on IDDQ Testing
Publicación: Proceedings, pp. 26-30
Lugar de celebración: San Jose, California, USA
Fecha: Noviembre 1998
Autores: J.L.Rosselló, E.Isern, M.Roca and J.Segura
Título: An analytical model of CMOS buffers power consumption
Tipo de participación: comunicación a congreso
Congreso: XIV Design of Circuits and Integrated Systems Conference
Publicación: Proceedings, pp. 125-130
Lugar de celebración: Palma de Mallorca, Baleares, España
Fecha: Noviembre
1999
Autores: J.L.Rosselló and J.Segura
Título: A physical modeling of the alpha-power law MOSFET model
Tipo de participación: comunicación a congreso
Congreso: XV Design of Circuits and Integrated Systems Conference
Publicación: Proceedings, pp 65-70
Lugar de celebración: Montpellier, Francia Fecha: Noviembre 2000
Autores: J.L.Rosselló and J.Segura
Título: A simple power consumption model of CMOS buffers driving RC interconnect
lines
Tipo de participación: comunicación a congreso
Congreso: XI International Workshop on Power and Timing Modeling
Publicación: Proceedings, Artículo no. 4.2
Lugar de celebración: Yverdon-Les-Bains, Suiza Fecha: Septiembre 2001
Autores: J.L.Rosselló and J.Segura
Título: Power-delay modeling of Dynamic CMOS gates for circuit optimization
Tipo de participación: comunicación a congreso
Congreso: the International Conference on Computer Aided Design (ICCAD’01)
Publicación: Proceedings, pp 494-499
Lugar de celebración: San José, CA, USA Fecha: Noviembre 2001
Autores: J.L.Rosselló and J.Segura
Título: Modeling the input-output coupling capacitor effects on the CMOS buffer power
consumption
Tipo de participación: comunicación a congreso
Congreso: XVI Conference on Design of Circuits and Integrated Systems
Publicación: Proceedings, pp 613-617
Lugar de celebración: Porto, Portugal
Fecha: Noviembre 2001
Autores: J.L.Rosselló and J.Segura
Título: A compact charge-based propagation delay model for submicronic CMOS buffers
Tipo de participación: comunicación a congreso
Congreso: XII International Workshop on Power and Timing Modeling (PATMOS
2002),
Publicación: Proceedings, pp 219-228
Lugar de celebración: Sevilla, España
Fecha: Septiembre 2002
Autores: J.L.Rosselló and J.Segura
Título: A Simple Analytical Description of Power Dissipation in Submicronic CMOS
Buffers
Tipo de participación: comunicación a congreso
Congreso: XVII Conference on Design of Circuits and Integrated Systems
Publicación: Proceedings, pp 627-630
Lugar de celebración: Santander, España Fecha: Noviembre 2002
Autores: J.L.Rosselló and J.Segura
Título: Power and Timing modeling of Submicron CMOS Gates
Tipo de participación: Presentación poster
Congreso: 40th Design Automation Conference (DAC’03)
Publicación: Proceedings, pp 627-630
Lugar de celebración: Anaheim, CA, USA. Fecha: Junio 2003
Autores: J.L.Rosselló and J.Segura
Título: A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic
CMOS Gates
Tipo de participación: Comunicación a congreso
Congreso: XII International Workshop on Power and Timing Modeling (PATMOS 2003)
Publicación: Proceedings, pp 627-630
Lugar de celebración: Torino, Italia. Fecha: Septiembre 2003
Autores: J.L.Rosselló and J.Segura
Título: A physically-based nth power law MOSFET model for efficient CAD
implementation
Tipo de participación: Comunicación a congreso
Congreso: XVII Design of Circuits and Integrated systems Conference (DCIS’03)
Publicación: Proceedings, pp 380-383
Lugar de celebración: Ciudad Real, España. Fecha: Noviembre 2003
Autores: J.L.Rosselló and J.Segura
Título: A Compact Propagation Delay Model for Deep-submicron CMOS Technologies
including Crosstalk Effects
Tipo de participación: Comunicación a congreso
Congreso: Design Automation and Test in Europe (DATE’04),
Lugar de celebración: Paris, Francia. Fecha: Febrero 2004
1262
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 8, AUGUST 1998
A Variable Threshold Voltage Inverter for CMOS Programmable Logic Circuits
J. Segura, J. L. Rosselló, J. Morra, and H. Sigg
Abstract— A programmable input threshold voltage inverter
compatible with double gate transistors fabrication processes is
presented. Such a circuit is useful as a programmable input
threshold buffer for general purpose circuits that can be included
in both TTL and CMOS environments, or can be used as low cost
analog programmable comparator. A prototype is fabricated and
measured.
of the n-MOS and p-MOS transistors, respectively. The
values that
can take are determined by the relative sizing
of the transistors composing the buffer.
In the next section we present the design of the inverter,
while the experimental results are reported in Section III.
Finally, the conclusions are reported in Section IV.
Index Terms—Buffer circuits, integrated circuit design.
II. CIRCUIT OPERATION
I. INTRODUCTION
I
N this work we develop a CMOS inverter compatible with
double gate MOS technologies that can be programmed
to different predefined threshold voltages. In the context of
this work, the inverter logic threshold voltage ( ) is defined
as the static input voltage at which the inverter output is
. An input logic threshold programmable CMOS
at
inverter is of high interest in applications such as CMOS
design of input buffers for general purpose circuits (as microcontrollers) to be used in both CMOS and TTL applications.
Once the final application or environment of the circuit is
known, the input circuitry can be programmed to match
the outside signal threshold voltage (TTL or CMOS), thus
optimizing the noise margin and the power consumption,
as will be shown. A programmable logic threshold inverter
is also of interest in analog applications, to be used as a
voltage comparator. Instead of using a whole analog block
(as an A/D or opamp) to determine if a signal is above or
below a given reference, the proposed variable logic threshold
inverter can be programmed to a voltage being the reference
voltage required for each application. The inverter has the
advantage of a significant area reduction given its simplicity
and the reduced number of transistors required. Additionally,
a comparator requires two inputs, while a programmable logic
threshold buffer used as a comparator would only require a
single package pin.
The design proposed can be divided into two blocks: the
programming circuitry and the buffer circuitry. The number
of transistors of the buffer determines the different logic
threshold levels of the whole inverter. A buffer with
transistors ( , N-type transistors, and one P-type MOS), can
logic threshold voltages between
be programmed to
and
,
and
being the threshold voltages
Manuscript received September 30, 1997; revised January 19, 1998. This
work was supported in part by the Spanish Government under Grant TIC961602-E.
J. Segura and J. L. Rosselló are with the Physics Department, Balearic
Islands University, 07071 Palma de Mallorca, Spain (e-mail: dfsjsf4@
ps.uib.es).
J. Morra and H. Sigg are with the Microcontroller Product Group,
Philips Semiconductors, Albuquerque, NM 87113 USA (e-mail: Jim.Morra@
abq.sc.philips.com).
Publisher Item Identifier S 0018-9200(98)05530-9.
The logic threshold voltage of a CMOS inverter is given
of the N and P transistors. In
by the aspect ratio
general, both transistors have the same length. Thus, the
ratio (the ratio between the transistor widths) is the
value that determines the inverter logic threshold voltage.
For general applications, inverters are designed to have a
curve
symmetric static transfer characteristic, i.e., the
at
. Therefore,
intersects the unity-gain line
using the Shockley model to describe the behavior of the
MOS transistor, and assuming the same value of the gate
oxide thickness for both transistors, then the aspect ratio that
gives a symmetric transfer characteristic has the well-known
expression
(1)
and
are the electron and hole mobility, respecwhere
and
are the transistors threshold voltages.
tively, and
In those cases where the transfer characteristic is not symmetric, the logic threshold voltage can be expressed as [1]
(2)
where it has been assumed that both transistors have the same
).
length (i.e.,
A. Buffer Design
A simplified schematic of a programmable logic threshold
voltage inverter (with the programming circuitry not shown) is
given in Fig. 1. Its operation is based on the expression stated
in (2). The inverter uses a single gate p-MOS enhancement
transistor and a pulldown transistors net composed of one
single gate n-MOS enhancement transistor and several double
gate n-MOS devices connected in parallel. The value of
is fixed, while the effective value of
can be changed
0018–9200/98$10.00  1998 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 8, AUGUST 1998
1263
using the TLV
that has its vector components defined as
if
otherwise
Fig. 1. Simplified schematic of a programmable logic threshold inverter.
The programming circuitry is not shown.
by programming or unprogramming the double gate n-MOS
transistors.
The different logic threshold voltages of the programmable
, can be derived from (2) obtaining
inverter,
(3)
is the ratio between the gate oxide
where
capacitance per unit area for the double and single gate
is the width of the th double gate n-MOS
transistors,
is a Boolean variable associated to the th
device, and
is
double gate transistor programming state. The value of
one when such device is unprogrammed and zero otherwise.
Each programming configuration of double gate transistors
has associated a unique set of Boolean variables that define
, as
a threshold level vector (TLV),
(4)
identifies each vector and is the decimal
The subindex
representation of the TLV, defined as
(5)
, each one of the
If
TLV’s will lead to a different value of
.
ratio (the width of transistors
and
The
in Fig. 1) is used to set the maximum value that
can
take, i.e., the logic threshold voltage associated to the TLV
. Only
of the whole
remaining
voltages can be independently chosen. The remaining levels
will be a combination of the independent ones. We use a
simple and straightforward technique to determine the size
of each double gate transistor: associate each logic threshold
level to one of the double gate transistors. This means that the
inverter will be programmed to the logic threshold level
for
to
(6)
and
single gate transistors
Therefore, only both the
for the
and one of the double gate devices (the transistor
TLV ) must be considered to calculate the width of each
programmable transistor. From (3) we get
(7)
B. General Design
The whole programmable inverter, containing both the
buffer and the programming circuitry, is shown in Fig. 2. The
programming circuitry consists of transistors
that connect or isolate the gate of the n-MOS transistors
value, and
from the input buffer depending on the
that drive the gate programming
transistors
. One register—the Programming Register—holds
signal
the TLV during the programming mode, and is reset in normal
transistors. When
,
operation to turn off all the
drives all the
the inverter is in the normal mode, the input
n-MOS transistors, and the equivalent active circuitry is the
same as that in Fig. 1. Given that no dc current goes into the
transistors can be
gate of the n-MOS devices, the size of the
, the inverter is in the programming
minimum. When
mode, the inverter input is disconnected from the n-MOS
transistors gates, and the double gate transistors are driven
by the contents of the Programming Register. In this mode,
the inverter input is used to drive the drain of the double gate
devices through the p-MOS transistor. During programming,
the TLV is held in the Programming Register to drive the
) to the desired devices through
programming gate signal (
transistors. The function of bit
and
the
is different from the remaining
bits and
transistor
devices, and are used to turn off the nonprogrammable
to prevent current through this device in the
transistor
programming mode.
In applications where more than one inverter is used, the
programming register is shared by all the inverters of the
circuit, and the input signal In is used to select which inverter
is being programmed.
C. A Programmable TTL/CMOS Input Inverter
A particular case of the general design is a programmable
TTL/CMOS input buffer. Such a circuit would be the simpler
case of a programmable logic threshold inverter given that only
one double gate device is required. The width ratio of the P
and N single gate transistors is used to set the logic threshold
level of the CMOS buffer configuration, while the width of the
double gate transistor adjusts the TTL configuration input logic
threshold. Given that the circuit is initially unprogrammed, it is
set to the TTL configuration by default. The double gate device
must be programmed and turned off to switch to the CMOS
configuration. The TLV for an input TTL/CMOS buffer has a
single bit, , which is set to program the CMOS configuration
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 8, AUGUST 1998
Fig. 2. Schematic of the programmable logic threshold inverter including the programming circuitry.
Fig. 3. Photograph of the prototype.
and reset for the TTL configuration. In the next section we
present the results obtained from a fabricated prototype.
(a)
III. EXPERIMENTAL RESULTS
We designed and fabricated a CMOS-TTL programmable
input buffer using the Philips 23G 1 double poly single
metal stacked gate EPROM process. The circuit was placed
on the scribe of a wafer, and the sensitivity of the input buffer
logic threshold to process variations was characterized. Only
the buffer circuitry was fabricated. The programming circuitry
was not included as the devices were accessed separately with
probe tips for programming. Measurements were made with
an HP4155 Semiconductor Parameter Analyzer. Fig. 3 shows a
photograph of the circuit. The prototype was designed to have
two programmable logic threshold voltages corresponding to
the TTL and the CMOS switching level. The TTL configuraV, while the CMOS
tion was designed to have
V.
configuration was
Fig. 4 reports the voltage and current static transfer characteristics of the buffer for both the TTL and CMOS modes. The
is 1.35 V, while the
experimental value obtained for
CMOS configuration logic threshold voltage is 3 V [Fig. 4(a)].
The deviations from the theoretical values are 0.05 V for
the TTL configuration and 0.3 V for the CMOS one. These
small deviations are due to the use of the Shockley transistor
(b)
Fig. 4. (a) Static voltage transfer characteristic and (b) current consumption
measured for the programmable inverter for both the CMOS and the TTL
configurations.
model in (7) to derive the effective widths of programmable
transistors. The use of more accurate models that take into
account second order effects of the transistor would correct
these small deviations.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 8, AUGUST 1998
INPUT LOGIC THRESHOLD VOLTAGES
Circuit
TTL
CMOS
A
1.35
2.99
AND
1265
TABLE I
DEVIATIONS FOR THE TTL AND CMOS CONFIGURATION OF SEVERAL MEASURED TTL-CMOS BUFFERS
B
1.37
3.02
C
1.39
3.02
D
1.41
3.02
Fig. 4(a) shows that programming the input buffer logic
threshold improves the noise margin of each application.
Fig. 4(b) reports that the power consumption of the buffer is
optimized when the circuit is used in a CMOS environment,
obtaining a reduction in the current from 60 A to less
V). Therefore, the switching power
than 1 A (for
consumption will be lowered in a CMOS environment using
a programmable inverter because the maximum static current
dissipation is reduced from 120 to 20 A. Such a reduction
will contribute to lower short-circuit current dissipation, and
therefore the overall circuit consumption [2]–[4].
Table I shows the input buffer logic threshold values measured for different circuits. It can be observed that the TTL
buffer logic threshold values have a larger variation than the
CMOS buffer logic threshold values, but in both cases the
variations are small.
Maximum speed transient measurements were not possible
since we did not include output buffers to drive the large
capacitance of the bond pads and measurement equipment [5].
The operation speed of the input buffer can be enhanced by
adding normal inverter stages to obtain a tapered buffer. The
number of stages and its size depends on the capacitance to
be driven as has been extensively studied [6]–[8].
The penalty of the area overhead is small given that the
transistors added to each inverter for the
size of the
programming circuitry can be minimum sized. Additionally,
pass
only one programming register and one set of
transistors are required for all programmable buffers in the die.
devices can be distributed
The programming register and
anywhere in the design which contributes to compact layout.
IV. CONCLUSIONS
A programmable input logic threshold voltage inverter for
double gate transistor technologies is described, along with
E
1.28
3.02
F
1.32
3.05
Max. dev. Mean dev.
8.5%
0.05
11.4%
0.23
Std. dev.
0.046
0.017
its principle of operation and design procedure. A CMOSTTL input buffer has been designed and fabricated showing
that it can be programmed to the CMOS and TTL levels
depending on the outside environment of the final application.
Measurements show good agreement between predicted and
obtained logic threshold voltages. Measurements also show a
significant enhancement of the noise margins of the circuit.
Finally, the input buffer provides the capability of reducing
the input circuitry power consumption, especially for CMOS
applications.
ACKNOWLEDGMENT
The authors would like to thank D. Vancil from Phillips
USA for his assistance in the buffer design.
REFERENCES
[1] J. P. Uyemura, Fundamentals of MOS Digital Integrated Circuits.
Reading, MA: Addison-Wesley, 1988.
[2] H. Veendrick, “Short-circuit dissipation of static CMOS circuitry and
its impact on the design of buffer circuits,” IEEE J. Solid-State Circuits,
vol. 19, pp. 468–473, 1984.
[3] S. Ma and P. Franzon, “Energy control and accurate delay estimation
in the design of CMOS buffers,” IEEE J. Solid-State Circuits, vol. 29,
pp. 1150–1153, Sept. 1994.
[4] U. Ko and P. T. Balsara, “Short-circuit power driven gate sizing
technique for reducing power dissipation,” IEEE Trans. Very Large Scale
Integration (VLSI) Syst., vol. 3, pp. 450–455, Sept. 1995.
[5] C. Yoo, M. K. Kim, and W. Kim, “A static power saving TTL-to-CMOS
input buffer,” IEEE J. Solid-State Circuits, vol. 30, pp. 616–620, May
1995.
[6] B. S. Cherkauer and E. G. Friedman, “A unified design methodology
for CMOS tapered buffers,” IEEE Trans. Very Large Scale Integration
(VLSI) Syst., vol. 3, pp. 99–111, Mar. 1995.
[7] C. Prunty and L. Gal, “Optimum tapered buffer,” IEEE J. Solid-State
Circuits, vol. 27, pp. 118–119, Jan. 1992.
[8] T. Sakurai, “A unified theory for mixed CMOS/BiCMOS buffer optimization,” IEEE J. Solid-State Circuits, vol. 27, pp. 1014–1019, July
1992.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 4, APRIL 2002
433
Charge-Based Analytical Model for the Evaluation of
Power Consumption in Submicron CMOS Buffers
José Luis Rosselló, Member, IEEE, and Jaume Segura, Member, IEEE
Abstract—The authors present an accurate analytical method
for analyzing the power consumption in CMOS buffers. It is derived from the charge transferred through the circuit and makes
use of the physically based MM9 MOSFET model (Velghe et al.,
1994), (Foty et al., 1997) as well as a modified Sakurai alpha-power
law model. The resulting analytical model accounts for the effects
of input slew time, device sizes, carrier velocity saturation effects,
input-to-output coupling capacitance, output load, and temperature. Results are compared to HSPICE simulations (level 50) and
to other models previously published considering a large set of parameters for a 0.18 and 0.35 m technologies, showing significant
improvements.
Index Terms—Closed form expressions, deep submicron, power
modeling and estimation.
NOMENCLATURE
A)
Input Parameters to the Model
zero bias low field mobility;
gate field mobility reduction coefficient (MM9
parameter);
nMOS, pMOS gate field mobility reduction coefficient (MM9 parameter);
drain field mobility reduction coefficient (MM9
parameter);
nMOS, pMOS drain field mobility reduction coefficient (MM9 parameter);
buffer output load;
gate oxide capacitance;
frequency;
substrate sensitivity when depleting bulk doping
(MM9 parameter);
substrate sensitivity when depleting surface
doping (MM9 parameter);
channel length;
channel length of nMOS;
channel length of pMOS;
gate source/drain underdiffusion (MM9 parameter);
nMOS, pMOS gate source/drain underdiffusion
(MM9 parameter);
Manuscript received July 20, 2000; revised August 3, 2001 and December
15, 2001. This work was supported by the Spanish Comisión Interministerial de
Ciencia y Tecnología under Project CICYT-TIC98-0284. This paper was recommended by Associate Editor K. Mayaram.
The authors are with the Physics Department, Balearic Islands University,
07071 Palma de Mallorca, Balears, Spain (e-mail: [email protected]; [email protected]).
Publisher Item Identifier S 0278-0070(02)02473-9.
B)
process bias on the channel length (MM9 parameter);
normalization constant;
surface potential for strong inversion (MM9 parameter);
transition time of input voltage;
voltage of transition between
and (MM9
parameter);
physical threshold voltage with no substrate or
drain bias (MM9 parameter);
nMOS, pMOS physical threshold voltage with no
substrate or drain bias (MM9 parameter);
channel width;
nMOS, pMOS Channel width;
isolation reduction of channel width (MM9 parameter);
process bias on the channel width (MM9 parameter);
Intermediate Parameters
velocity saturation index;
nMOS, pMOS velocity saturation index;
MOSFET conductivity;
nMOS, pMOS conductivity;
body effect coefficient;
nMOS body effect coefficient;
overvoltage;
maximum overvoltage;
overvoltage at
;
charge stored at the output node flowing through
the nMOS transistor when the output is discharged;
output voltage swing;
effective carriers mobility;
interconnect resistance per square;
area capacitance;
fringing capacitance to underlying conductor for
single line;
input to output coupling capacitance;
input to output coupling capacitance value when
the input voltage is high, low;
minimum output capacitance allowed by the
technology;
total output capacitance when the input voltage is
low;
short-circuit energy;
short-circuit energy dissipated in a falling, rising
input transition;
transient energy;
0278-0070/02$17.00 © 2002 IEEE
434
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 4, APRIL 2002
transient energy dissipated in a falling, rising
input transition;
nMOS, pMOS drain current;
drain current at
;
drain current at
and
;
nMOS, pMOS drain current at
;
saturated drain current;
nMOS, pMOS saturated drain current;
drain current;
maximum short-circuit current;
maximum short-circuit current for heavily loaded
buffers;
maximum short-circuit current for unloaded
buffers;
short-circuit current;
effective channel length;
minimum lithographic channel length allowed by
the technology;
effective channel length of pMOS;
total power consumption;
charge stored at
and
;
overshoot charge transferred (OCT);
overshoot charge transferred for a fast input tran);
sition (
overshoot charge transferred for a slow input
);
transition (
overshoot charge fraction transferred during the
;
interval
overshoot charge fraction transferred during the
;
interval
short-circuit charge transferred when
;
short-circuit charge transferred for a rising input
transition;
effective resistance of nMOS;
short-circuit current time interval when
;
short-circuit current time interval;
time;
time at which the short-circuit current is maximum;
time at which the short-circuit current is maximum for unloaded buffers;
time at which the short-circuit current is maximum for heavily loaded buffers;
mathematical limit of
when
;
time at which the nMOS transistor starts to conduct;
overshoot time;
time at which the overshoot current is maximum;
time during which the pMOS device passes a
negative current;
saturation voltage at
;
saturation voltage of pMOS at
;
saturation voltage;
saturation voltage of pMOS;
supply voltage;
drain voltage;
smoothing function used by MM9 between limand
;
iting values
gate voltage;
input voltage;
output voltage;
short-circuit input voltage swing for
;
threshold voltage used by the alpha-power law
MOSFET model;
nMOS, pMOS alpha-power law threshold
voltage;
effective channel width;
minimum lithographic channel width allowed by
the technology;
nMOS, pMOS effective channel width.
I. INTRODUCTION
P
OWER dissipation emerged as an important concern in circuit design during the last decade due to heating problems
in high-density/high-performance circuits and to power savings
required for portable applications. A growing fraction of the
power consumed by very large scale integration (VLSI) circuits
is due to the clock distribution network, signal repeaters, I/O
drivers, and busses all based on inverters. Moreover, the analytical description of the power dissipated in a CMOS inverter
is the most important step in the description of more complex
gates [3].
It is well known that power dissipation in CMOS circuits has
a dynamic and a static component. The dynamic dissipation is
due to the charge/discharge of the gate output load and to the
short-circuit current due to the direct supply-ground conducting
path created during the transition [4]–[6]. Many high-level approaches consider only the first contribution to compute power
in large circuits [7], [8], given the complexity and computing
cost of considering the short-circuit component.
The static dissipation is mainly due to current leakage from
transistors in the off state, although reverse biased diodes from
the device diffusions and well regions also contribute to this current. The off-state current, referred to as subthreshold leakage,
is becoming more important with technology scaling since the
device threshold voltage ( ) is reduced to maintain circuit performance. This term is usually neglected since
( being the Boltzmann constant, the temperature in Kelvin,
and the electron charge) [9].
Several works model the short-circuit power consumption.
Veendrick [4] obtained an expression for unloaded buffers
although the short-circuit component has a strong dependence
on the output capacitance. Hedenstierna et al. [5] calculated the
short circuit current using the Shockley MOSFET model for
loaded buffers. This model cannot be applied to short-channel
devices since they exhibit a linear dependence of saturation
current versus the gate voltage, rather than the traditional
square-law model used for long-channel devices [6]. Sakurai
et al. [6] derived a model for long and short channel devices
using their -power law MOSFET model for unloaded buffers.
This model, as the model in [4], is useful to estimate the
short-circuit component upper bound but cannot be used for
a detailed power dissipation description since the output load
effect must be included. Turgis et al. [10] derived an expression
ROSSELLÓ AND SEGURA: CHARGE-BASED ANALYTICAL MODEL FOR EVALUATION OF POWER CONSUMPTION
for the short-circuit dissipation assuming that carriers were
always moving at the saturation velocity and took into account
overshooting effects. This model is valid only for deep submicron technologies and introduces the concept of equivalent
capacitance, thus allowing a direct and frequency-independent
comparison of the various power components. Hamoui et al.
[11] obtained an expression for the short-circuit power dissipation using a modified version of the th power law MOSFET
model in [12]. This approach requires numerical computing in
a three-step process to determine the time when the short-circuiting transistor changes its mode of operation. Nikolaidis et
al. [13] obtained an expression of the short-circuit dissipation
for buffers driving long interconnect lines using the -model of
an RC load and the -power law model for submicron devices.
They took into account the input–output capacitance effects
while the short-circuit current contribution was neglected when
computing the output waveform. Recently, Nose et al. [14]
derived a closed-form expression for the short-circuit power
dissipation of CMOS gates taking into account short-channel
effects, but not overshooting effects of increasing importance
in submicron CMOS circuits. The work concluded that the
) will not
short-circuit power to total power ratio (
is kept constant.
change with scaling if the ratio
In this work, we propose and evaluate a model to compute accurately the power consumption of CMOS buffers
accounting for the main effects in submicron technologies as
the input–output coupling capacitance and carriers velocity
saturation effects avoiding time-consuming numerical procedures. The energy is computed from a detailed description of
the various charge transference mechanisms involved during
transitions. The final expression is the sum of the power
dissipated when charging/discharging the output capacitance
plus the short-circuit component that is accurately computed
describing the impact of overshooting effects. The modeling
process is described in detail providing a deep insight into the
energy mechanisms involved as well as their interrelationship.
The model is compared to HSPICE simulations (level 50) and
to other models previously published considering a large set
of parameters for a 0.35- and 0.18- m technology, showing
significant improvements over previous works.
The paper is organized as follows: in Section II we describe
the energy components and the method used to derive each contribution. Section III presents the MOSFET models used, while
Sections IV and V derive the short-circuit and transient energy
components, respectively. Section VI presents the results and
Section VII concludes the work.
II. ENERGY COMPONENTS
We derive the energy consumption of a CMOS buffer (Fig. 1)
describing the charge transfer mechanisms in the circuit when
an input ramp is applied. The dynamic behavior of the circuit in
Fig. 1 is described by
(1)
is the output load that includes the gate capacitances
where
driven by the buffer, the interconnect wiring capacitance, and
is the input–output
the diffusion capacitances of the buffer.
Fig. 1.
435
CMOS buffer model used to compute the energy dissipation.
capacitance,
the output voltage,
and
the pMOS
the input
and nMOS transistors current, respectively, and
voltage.
Fig. 2 illustrates the time evolution of the output voltage and
the current through the nMOS and pMOS devices when a rising
input voltage is applied. The input voltage is described with a
linear ramp as
(2)
. From Fig. 2 it follows that
(the short-circuit current time interval
.
when overshooting is neglected) and
We compute separately the short-circuit energy dissipation
component ( ) and the energy associated with the output node
discharge ( ). The short-circuit energy is obtained from the
short-circuit charge, while the expression of the transient energy
is derived computing the charge that flows from the output node
and
) to ground. We use
(i.e., the charge stored at
and
for the short-circuit and transient energy components,
respectively, for a rising input, while
and
refer to these
energies for a fall input transition. The power dissipation in one
period is computed as
where
(3)
is the frequency of the input signal.
where
The current through the pMOS transistor ( in Fig. 2) has
two components clearly distinguished by its sign. The negative
pMOS current is due to a partial discharge of the output capacitance from the output node to the supply rail. This effect appears
when the input–output capacitance drives the output voltage be) at the beginning of the transition
yond the supply value (
[15]. When the nMOS device starts to conduct, it pulls the output
voltage down. This effect is known as overshooting, and the
time during which the output voltage is beyond the supply value
. Once the output voltage goes
is called the overshoot time
, the pMOS current is positive corresponding to the
below
short-circuit component due to the simultaneous conduction of
both devices.
From this picture it is clear that the overshoot and short-circuit
current components are related and their relative contribution is
determined by the input transition time. If the input voltage is
(the input voltage value at which the pMOS
below
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 4, APRIL 2002
Fig. 2. Output voltage and current evolution in the nMOS and pMOS
transistors for a rising input linear voltage.
turns off;
is the pMOS threshold voltage) at
, then
there will be a short-circuit current period from this time until
the pMOS is turned off. This case will be referred to as a slow
input transition. In the case of a fast input transition the output
when the input reaches
.
voltage is still beyond
( being the time at which the nMOS
In this case,
is the short-circuit current
transistor starts to conduct and
time interval when there is no overshooting; see Fig. 2) and there
is no short-circuit period. For a fixed input transition time, the
greater the overshoot time (i.e., the greater the input-output coupling capacitance), the shorter is the duration of the short-circuit current contribution. The overshoot time depends on the
relationship between the input–output capacitance (that drives
) and the driving strength of the
the output voltage beyond
nMOS transistor (that pulls this output voltage down), while the
short-circuit period termination is determined uniquely by the
input transition time. This effect is illustrated in Fig. 3, obtained
from simulation, showing a set of pMOS current curves for a
fixed input rise time and different coupling capacitance values.
The short-circuit current contribution tail end is independent of
the time at which short-circuit starts (since it is determined by
), while its negthe time at which the input voltage is
ative slope does not vary significantly in all cases because the
pMOS transistor is saturated. Note that overshooting does not
only impact short-circuit duration, but also decreases its maximum value.
We included the overshooting effects on the short-circuit expression through the overshoot time using a geometrical approach following the behavior reflected in Fig. 3. This process
is detailed in Section IV.
The short-circuit energy ( ) will be computed from the
pMOS current since this component can be clearly identified.
The energy associated with the overshoot charge transferred will
be neglected since this energy is proportional not only to the
small amount of charge involved, but also on the voltage difference through which it flows, which is also very small when
compared to the supply voltage.
The transient energy ( ) corresponds to the energy dissipated when discharging the output capacitance. The energy of a
Fig. 3. pMOS current shape variation for a fixed input rise time and different
values of the input–output coupling capacitor.
discharging constant capacitance is simply
, where
is the voltage swing and the charge initially stored in the capacitance and discharged through the nMOS transistor (defined
as dynamic charge). The voltage swing of the output node in the
but a higher one, say
buffer circuit is not the supply voltage
, due to overshooting. The dynamic charge will be derived using charge conservation by computing the charge at the
beginning of the transition minus the charge at its end. It is important to remark that the overshoot charge (that is the charge
transferred from the output node to the supply rail) must be subtracted from this term since it flows through a voltage difference
and not through
as occurs for the charge flowing
from the output node to ground. Therefore, although the overshoot charge is small and its overall energy contribution can be
neglected, this charge must be subtracted from the charge variation at the output node since only the dynamic charge is multi) when computing
plied by a large voltage difference (
the transient energy.
The output node charge is stored in both the input–output caand the load capacitance
. Since the transient
pacitance
energy is derived from the computation of the charge at the beginning and the end of the transition, we require an expression
of the input–output capacitance (which is strongly dependent
on the input–output voltage) only for these two static operating
in the static input low state (
)
conditions. The value of
considering the side-wall capacitance of both transistor drains
and the gate to drain overlap capacitance of the pMOS transistor
in the linear region is given by
(4)
and
being the gate source/drain underdiffusion
with
and
for the pMOS and nMOS transistors, respectively.
are the nMOS and pMOS effective channel width, while
is the effective channel length of the pMOS transistor. The
effective channel length and width are [2]
(5)
ROSSELLÓ AND SEGURA: CHARGE-BASED ANALYTICAL MODEL FOR EVALUATION OF POWER CONSUMPTION
437
where
and
are the process bias on the channel
is the isolation rewidth and length, respectively, while
duction of channel width. For a static input high the capacitance
can be obtained similarly.
III. MOSFET MODEL USED
Equation (1) cannot be solved in a closed form even when
the simple Shockley MOSFET model is considered. Moreover,
since carrier saturation effects become important with technology scaling, more advanced MOSFET models accounting
for such effects must be considered.
The alpha-power law MOSFET model [16] is a simple shortchannel MOSFET model expressed as
(6)
with
(7)
The saturation voltage
Fig. 4. Comparison of the saturation voltage provided by MM9 with the linear
description of (8) (with n = 1) for a 0.35-m technology.
the carriers mobility, while
and
are the effective
and
channel width and length, respectively. The parameters
are the gate field and drain bias mobility reduction coefficients and is given by
is given by [16]
(8)
instead of the traditional
dependence
We took
of the saturation voltage [6] to simplify Sakurai’s equations
in the linear region. A comparison of (8) with the physically
based saturation voltage for an nMOS transistor with dimenm and
m is plotted in Fig. 4.
sions
The parameter is the velocity saturation index that takes
a value between two (long-channel devices) and one (shortand
are the drain curchannel). The two parameters
, while
rent and the saturation voltage for
and are fitting parameters [6].
parameters
and
can be computed using any physically based
MOSFET model. We used the MOSFET model 9 (MM9) to
compute these parameters (see [1] and [2] for a detailed description of the MM9 structure). The MM9 is a short-channel
model that is being included in many widely used general-purpose circuit simulators and thus is drawing a significant amount
of attention. A relatively small number of model equations and
parameters are used when compared with many other models
[2]. MM9 basic equation is
(9)
is a smoothing function being equal to the drain
where
to source voltage when the transistor is in the linear region
is the
and to the saturation voltage when it is saturated.
is the threshold voltage.
gate to source voltage and
with
being the gate oxide capacitance,
(10)
is the substrate sensitivity when depleting surface
where
is the substrate sensitivity when depleting bulk
doping and
is a voltage of transition between
and
doping.
.
is the surface potential for strong inversion while
and
are MM9 constants from [1] and [2]. A
detailed description of parameter extraction for this model from
the device I-V current characteristics can be found in [17].
in (7) is computed using (9) while
in
The value of
(8) is obtained from [2]
(11)
Alpha-power law model equations are mathematically simpler than physically based MOSFET models like MM9 with the
disadvantage that the relationship between the empirical paramand the foundry supplied process parameters is not
eters ,
developed directly. We use the following relationship [18] to relate to physical parameters:
(12)
The expression for
in the MOSFET Model 9 is [2]:
(13)
To obtain a better fitting of the transistor characteristics we
by adjusting this threshold voltage to fit
derive a value of
. We obtain this
the drain saturation current at
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 4, APRIL 2002
current value (denoted as
) from (9) and equate it to the
predicted value of the alpha-power law
The short-circuit charge transferred (SCCT) is the integral of
from the time at which the nMOS is turned on, , up to the
(see Fig. 2)
time at which the pMOS turns off,
(14)
(18)
with
given by (12). We use (14) to get
value leading to
from the predicted
That leads to the following:
(19)
(15)
,
,
, and
The parameters
can be obtained using any physically based MOSFET
and
model since
.
analytically to
Equations (12) and (15) relate and
physical parameters without the need for time-consuming numerical computations.
IV. SHORT-CIRCUIT COMPONENT
We derive the short-circuit charge in a first step, neglecting
overshooting effects which are included in a second step through
the overshoot time.
), the short-circuit
In the case of unloaded buffers (
current is equal to the nMOS saturation current for the interval
and to the pMOS saturation current when
, where
is the time at which the short-circuit current is maximum. Therefore, using the alpha-power law
MOSFET model, the short-circuit current for an unloaded buffer
is
(16)
This current dependence is taken as a reference to obtain an
expression for the short-circuit current for loaded buffers using
) and the time at which
the values of the maximum current (
) derived in Appendix A.
and
have
it occurs (
been derived considering the limit of unloaded buffers (i.e., paand
) and heavily loaded buffers (rerameters
,
).
ferred to as
As an analogy to (16), the short-circuit current is shown in
(17) at the bottom of the page.
The value of is selected to set the value of (19) equal to the
. This parameter is required to adjust
HSPICE simulation of
the charge and accounts for deviations mainly due to differences
(from the -power model) and the physical
,
between
as well as other second-order effects not considered similar to
channel length modulation.
This value has been found to be close to 1.5 and 1.7 for 0.35and 0.18- m technologies, respectively, for a large range of parameters values, including variation of the channel length (and
therefore ), the buffer symmetry (which has a strong effect on
the short-circuit current shape), input rise/fall time, output capacitance, input–output capacitance, etc. The value of is the
same for rising or falling input transitions and must be adjusted
only once for the technology since its value remains constant
for all the parameters considered in the model.
Fig. 5 compares (17) to HSPICE simulations for various
to 50
). When
values of the output capacitance (from
is small, the maximum current time is close to
while
HSPICE results are close to the current shape predicted by
(16). As the output capacitance increases, the time at which the
short-circuit current is maximum also increases and is close
for large values of
. The areas under the curves
to
described by (17) and HSPICE simulations (i.e., the charge)
are nearly the same.
Overshooting effects are included through the overshoot time
. Simulations in Fig. 3 showed that overshooting displaces
the short-circuit current to the right, maintaining the current
slopes invariant. This can be described analytically using a geometrical approach as shown in Fig. 6. The short-circuit current
curve displacement is approximated with straight lines of conis the area of the triangle
, while the restant slope.
) is the area within the
duced SCCT due to overshooting (
. With this geometrical analogy,
is derived
triangle
using
as
from
(20)
given by (19). Equation (20) is an approximation obwith
tained assuming that the short-circuit current is linear with time
(17)
ROSSELLÓ AND SEGURA: CHARGE-BASED ANALYTICAL MODEL FOR EVALUATION OF POWER CONSUMPTION
Fig. 5. Short-circuit current versus C for a 0.35-m technology. The
maximum short-circuit current and the time at which such a maximum takes
place are fitted by the model proposed.
and it does not vanish for
is
lation for any
Fig. 6.
Geometrical derivation of Q
439
from Q
using t .
. A more accurate re-
(21)
The mean deviation of (21) with respect to (20) is less than
and provides negligible values for
.
10% of
We plot a comparison of (21) to HSPICE in Fig. 7 showing
for different values of
, with good accuSCCT versus
is given in Appendix B.
racy. The mathematical derivation of
Finally, the energy associated with SCCT for a rising input is
computed as
(22)
Fig. 7. Short-circuit charge transfer versus coupling capacitor for various
values of C in a 0.35-m technology.
V. TRANSIENT DISSIPATION
The transient energy is dissipated when the output node is discharged. Conceptually this contribution can be subtracted from
the short-circuit energy given that only the short-circuit charge
flows through the short-circuiting transistor (that is the pMOS
(nMOS) transistor for a low to high (high to low) input transition). In the buffer model of Fig. 1 the charge at the output node
is stored in both the output and coupling capacitances, leading
.
to
As discussed in Section II, overshooting has two main effects:
first, it raises the voltage from which the output is discharged
(say
), and second, part of the charge
beyond
through
initially stored at the output node is transferred to
the pMOS (this charge was referred to as the overshoot charge
). The overshoot charge does not contribute to the transient
energy in the same way as the charge that goes to ground since
the overshoot charge flows through a smaller voltage drop
(see Fig. 2). Therefore, the energy expression associated with
the discharge of the output node must contain only a fraction of
the charge initially stored in the output capacitances. The energy
dissipated by the nMOS transistor for a high-to-low output tran(energy dissipated for
sition is given by
a constant discharging capacitance).
is the charge transferred from the output node to ground through the nMOS tranis the voltage swing given by
.
sistor and
Thus, the discharging energy is expressed as
(23)
is the charge at the output node at time (when
where
is the charge
the nMOS transistor starts to conduct),
stored at the output node when the output transition is finished,
is the overshoot charge transferred from the output
and
node capacitances through the pMOS transistor (and therefore
not dissipated in the nMOS transistor) during time that both
). The output voltage swing
transistors are conducting (
is
We write
considering
at the output node is equal to the
that the charge for
charge at that node at the beginning of the input transition
) minus the charge that has
(
through the pMOS
been transferred from the output to
transistor until the nMOS transistor starts to conduct (defined
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 4, APRIL 2002
as
). Since
charge transferred is
and the total overshoot
, (23) takes the form
with
(30)
(24)
If the parasitic input–output capacitance is neglected (
), the overshooting and overvoltage vanish (
and
) and the well-known expression
for the transient energy is obtained as
(25)
To compute the transient energy in (24) we derive an expresand the overvoltage
.
sion for the overshoot charge
A. Overshoot Charge Transfer
The overshoot charge transfer differs for fast and slow input
transitions since in the first case the pMOS transistor is off when
overshooting ceases and in the second case this device is still
conducting. We compute the overshoot charge for the slow and
and
, respectively) and then comfast input transitions (
bine both equations in a unified expression.
, i.e., the
1) Slow Input: In this case
has not reached
at
. The
input
is given
charge stored at the output node at time
, while at the
by
beginning of the transition the charge stored at the output
. The difference
node is
is the overshoot charge plus the charge
. Therefore, the
that passed through the nMOS until
overshoot charge expression is
where the parameter defines the transition between the two
regions.
2) Fast Input: For a high-speed transition the pMOS is off
(i.e.,
) and the overshoot charge is
before
calculated from the current passed through the pMOS. We use
(9) neglecting the velocity saturation effect of the gate voltage
) with neither of the quadratic or higher order terms
(
(the drain voltage of the pMOS during overshooting is
of
small) leading to
(31)
Given that
(32)
is computed from (1)
At the beginning of the transition
),
neglecting the nMOS and the pMOS current (
which are negligible with respect to the current injected through
that is proportional to
which is large for fast inputs). So in this case (1) simplifies to
(33)
from (33), the pMOS drain voltage takes the form
, thus (32) leads to
(26)
is close to , therefore the
For a slow input transition
is still valid and the integral over the
approximation
nMOS transistor current can be neglected.
The term into the parenthesis of (26) corresponds to the input
voltage swing that determines the amount of charge flowing
through the pMOS transistor during overshooting and cannot go
since for these values the pMOS is off. The
beyond
can go beyond
leading to an overestimation in
time
the input voltage swing. Therefore, we correct the expression of
in (26) with a time
.
(27)
must be equal to the overshoot time
for
Knowing that
for large ones, we use
small values and that saturates to
the following expression:
(28)
is a function that saturates to
where
and is equal to
when
when
, defined as
(29)
, we obtain
(34)
and
: Equations
3) Combining Expressions for
(27) and (34) are unified into a single analytical expression
for high-speed
for the overshoot charge that is equal to
for slow inputs
transitions and to
(35)
Fig. 8 shows the charge transferred through the pMOS tranfor
sistor for a high-to-low output transition as a function of
different nMOS channel widths. Squares are HSPICE simulations while solid lines correspond to the charge model developed
). The charge transferred for high-speed transitions is
(
mostly due to overshooting (a total negative charge is obtained)
while for slow-input transitions the short-circuit component is
dominant (overall positive charge). The curves in Fig. 8 show
a good fit to (35) and (21) to describe the charge through the
pMOS.
B. Overvoltage Evaluation
computing the
We obtain the maximum overvoltage
. We adjust this expression to meet the
output voltage at
limit of an ideal step input using charge conservation.
ROSSELLÓ AND SEGURA: CHARGE-BASED ANALYTICAL MODEL FOR EVALUATION OF POWER CONSUMPTION
Fig. 8. pMOS charge transference versus input rise time for three different
channel widths for a 0.35-m technology (Symbols: HSPICE simulations, solid
lines: Model proposed).
The derivation of
441
Fig. 9. Maximum overvoltage versus input rise time for various values of C
for 0.35-m technology.
requires solving
(36)
where
Equation (36) is derived from (1) and is valid for
is neglected since the nMOS is off. To get an analytical so, we take the pMOS curlution of (36) and compute
rent expression with the approximations of small drain voltage
and neglect gate saturation effects (31). We also take an average
as
leading to
value of
(37)
We solve (36) using (37) and compute the overvoltage when
the nMOS transistor starts to conduct (
) obtaining
(38)
Equation (38) provides a partial description of the maximum
output voltage.
For an ideal step input, the maximum overvoltage is obtained
from charge conservation as
(39)
. The maxThis result is not provided by (38) when
imum overvoltage is also determined by the discharging nMOS
current and the capacitance being discharged ( ). To account
for these effects we define an effective resistance for the nMOS
and incorporate an additional
transistor as
term to (38) to estimate the maximum overvoltage beyond
(40)
Equation (40) is an empirical expression that provides an excellent agreement with HSPICE simulations as shown in Fig. 9.
The plot presents the overvoltage versus the input rise time for
(from
to 50
).
different values of
Fig. 10. Power dissipation versus input-to-output transition time ratio for
0.18-m technology. Three different capacitance values (C , 3C ,
and 5C ) driven by three different buffers (I , 3I , and 5I ) are
considered.
VI. RESULTS
We compare the model predictions versus HSPICE simulations for 0.35- and 0.18- m technologies considering energy
versus input transition time, output capacitance, channel length,
supply voltage, temperature, and the pMOS to nMOS channel
width ratio. For each plot we include results from the models
in [10], [11], or [14], depending on which best fits the energy
consumption for the parameter considered.
Fig. 10 plots the energy dissipated per cycle versus the
input-to-output time ratio for the 0.18- m technology. The
output time is taken from HSPICE simulations as an average value of the rise and fall times at the buffer output
), where
and
are proportional to the time
(
at the output ( ) to 0.1
at the output ( )
from 0.9
). Three different design scenarios
(i.e.,
are considered: a minimum inverter driving a minimum sized
m
m
)
inverter (
and 5
) with output capaciand two scaled inverters (3
and 5
, respectively. The input time ranges
tances of 3
from 20 ps to 1 ns (0.5 to 3.5 in the plot) covering both fast
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 4, APRIL 2002
Fig. 11. Power dissipation versus input time to output time ratio for three
different inverter sizes in 0.18-m technology. Different W =W ratios are
considered.
Fig. 12. Power dissipation versus output capacitance for three different input
rise times for 0.18-m process technology with W = 1 m and W = 2 m.
The model is compared to HSPICE simulations and a recently published model
[14].
and slow input transitions. Simulation results show that both
models (the model proposed and the model in [10]) provide a
good description of the energy for the whole design space considered.
Fig. 11 plots the power dissipation versus the input-to-output
and
time ratio for five inverters, three with
ratios
m
m
m
m and
m
m and two with
and
ratios
m
m and
m
m for 0.18- m technology. The input
times range from 20 ps to 1 ns. The model presented reports
better fitting with respect to previous works (we include results
only from [14] as the model better describing the energy for
this parameter) maintaining an accurate description of power
.
for different values of
Fig. 12 shows the power dissipation dependence with the
ps,
output capacitance for three input rise time values (
ns, and
ns) for a 0.18- m technology CMOS
m
m. The model proposed and
inverter with
the model in [14] are compared to HSPICE simulations showing
similar accuracies, thus verifying the accuracy of the proposed
model to describe the short-circuit and transient components.
Fig. 13.
Energy dissipation versus input-to-output time ratio for different
ratios for 0.35-m technology. When t =t
> 1 the short-circuit
component is dominant while for t =t
< 1 the overvoltage contribution
increases the total power.
W =W
Fig. 14. Energy dissipation versus channel length for 0.35-m technology.
This graph shows the behavior of the proposed model when varying the velocity
saturation index () and the coupling capacitance.
Fig. 13 plots the energy dissipated per one cycle period
versus the input-to-output time ratio for 0.35- m technology.
Four different inverters are considered with different values
ratio and two values of the output capacitance
of the
(all the values specified in the graph). The input time ranges
from 20 ps to 1.5 ns. Results show that the model presented
describes correctly HSPICE simulations under all the parameter
combinations considered representing an improvement over
previous models.
Fig. 14 compares the energy versus channel length with
and a minimum channel
HSPICE for different values of
m). This graph shows good accuracy of the
width (
model proposed for different velocity saturation index values
( ) since this parameter is strongly dependent on the channel
length. As the device length decreases, the conductance of the
transistors is reduced leading to lower values of SCCT; this is
ns. The power contribution due to the
the case for
coupling capacitance increases with channel length for shorter
input transitions.
ROSSELLÓ AND SEGURA: CHARGE-BASED ANALYTICAL MODEL FOR EVALUATION OF POWER CONSUMPTION
Fig. 15. Energy dissipated versus power supply for 0.35-m technology. The
model developed provides a good description for the entire range considered.
443
Fig. 17. Energy versus temperature for three supply voltages for 0.35-m
technology.
Fig. 18. Energy versus pMOS width with W = 3 m and C = 10C
for 0.18-m technology. This graph shows the behavior of the model when
nonsymmetrical buffers are considered in the deep-submicron regime.
Fig. 16. Energy dissipated versus power supply for 0.18-m technology. The
model proposed describes the entire range considered.
The energy variation with the power supply voltage is shown
m,
m,
in Fig. 15 for a CMOS buffer with
and different input rise
an output capacitance of
times (from 50 ps to 1 ns). HSPICE simulations are compared
to the proposed model and the model in [11]. Energy models
require good accuracy with supply voltage since it is one of the
key parameters used to control power consumption. Simulations
show that the model proposed represents a contribution in describing this dependence.
The energy versus power supply for 0.18- m technology is shown in Fig. 16 for a CMOS buffer with
m
m,
, and
ps, 500
ps, and 1 ns. The model proposed provides a good description
in all the range considered.
Fig. 17 plots the energy versus temperature for three different
supply voltages. The MOSFET Model 9 temperature dependence [2] is included in the basic parameter set. The model accuracy is maintained over the whole period considered ( 50
to 150C) showing that the low voltage regime is less sensitive
to temperature variation. Fig. 18 plots the energy in one cycle
versus the pMOS channel width for a fixed value of the nMOS
channel width for 0.18- m technology. Different values of the
are considered (from 50 ps to 1 ns). Fig. 18 reinput times
flects the accuracy of the model to describe the time at which
the maximum short-circuit current takes place as the maximum
dc current location is dependent on the buffer symmetry.
Fig. 19 shows the energy dissipated by a CMOS buffer driving
a long interconnect line. We considered a 1- m width level
model [20] for 0.35- m tech2 metal simulated using a
nology. For this technology the metal 2 to well capacitance per
m its fringing caunit of area is
m, and its square resistance is
pacitance is
m sq. The total output capacitance (used in the
, where
model) was computed as
is the output capacitance of the buffer,
is the parais the input capacitance
sitic interconnect capacitance, and
of the driven gate. We compared HSPICE simulations (squares)
to the model developed and a specific model for long interconnect lines [13] for two different input times of 50 ps and
1 ns. The model derived in this work reports good fitting for
interconnect lines lengths below 5 mm, leading to energy underestimation for higher wire lengths. This underestimation is
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 4, APRIL 2002
TABLE I
AVERAGE ERROR OF ENERGY ESTIMATION
VERSUS HSPICE FOR 0.18- AND 0.35-m TECHNOLOGY
TABLE II
PERCENTAGE OF ENERGY DUE TO COUPLING CAPACITANCE EFFECTS
( E ) AND TO SHORT-CIRCUIT CURRENTS ( E ) WITH RESPECT
TO THE TOTAL POWER
%
Fig. 19.
line.
%
Power consumption for a CMOS buffer driving a long interconnect
due to the increase of the line resistance with its length. When
the line resistance becomes comparable to the buffer output
resistance, part of the output capacitance is shielded from
the buffer, thus decreasing the gate delay and increasing the
short-circuit dissipation [21], [22]. We compare this result with
the model developed by Nikolaidis et al. [13] (dashed line in
Fig. 19). That model provides an accurate description for the
delay of an inverter driving an RC line but uses a fixed value
for the time at which maximum short-circuit takes place (set
). Therefore, the dependence of this time
as
with the output capacitance increase (Fig. 5) is not described,
leading to a underestimation of the energy dissipated as shown
in Fig. 19.
We calculated the mean deviation of the Energy versus input
time, channel length, supply voltage, output capacitance, and
pMOS channel width from HSPICE simulations for the models
in [10], [11], and [14] and the model proposed for the 0.18- and
0.35- m technologies considered. The percentage deviations
are reported in Table I showing the improvement achieved by the
model proposed with an overall accuracy within 5% of HSPICE
simulations, thus representing an improvement over previous
works. The model in [10] provides the better agreement with
HSPICE simulations for the 0.18- m technology rather than the
0.35- m technology since it was developed for deep-submicron
technologies.
Table II reports the percentage of energy due to coupling ca) and short-circuit currents (
) with
pacitance effects (
is kept constant
respect to the total power. The ratio
for the two technologies considered and the input time is se). The percentage
lected to be equal to the output time (
of the short-circuit power is nearly the same for the two technologies (as predicted in [14]) while the influence of the coupling capacitance on the total power increases for the 0.18- m
technology.
Finally, we computed the power dissipation for 10 transitions with HSPICE and the analytical models on a Pentium
III processor-based computer. Simulation times are reported in
Table III showing that the models in [5], [6], [10], [14], and the
proposed model are up to three orders of magnitude faster than
HSPICE, while the models in [11] and [13] are two orders of
magnitude faster than the simulator. The numerical approaches
TABLE III
COMPUTATION TIME FOR 10 TRANSITIONS
used in [11] to obtain the time at which the maximum short-circuit current takes place (using the bisection method) and the
complex equations in [13] to model the RC line at the output
of the buffer increase computation considerably.
VII. CONCLUSION
We have developed an analytical expression for the energy
dissipation in CMOS buffers by solving the dynamics of the circuit and considering a physically based -power law MOSFET
model. The various energy components are discussed and modeled in detail highlighting the parameters involved and their
interrelationship. Several nonlinear problems are solved with
simple and accurate formulas to avoid time-consuming numerical procedures. Exhaustive comparisons to HSPICE results are
provided to demonstrate the validity and accuracy of the model
for both submicron (0.35 m) and deep-submicron (0.18 m)
technologies. This model is expected to remain valid for scaled
technologies as long as the subthreshold leakage component
does not dominate active power, since the main submicron effects are accounted at the device level. It represents an improvement over previous models since results show an overall high
accuracy in describing the energy for all the parameters considered (Figs. 10–19), while previous models maintain accuracy
only for some parameters or technologies. The model proposed
has an average error within 5% of HSPICE simulations for a
wide range of parameter variation.
ROSSELLÓ AND SEGURA: CHARGE-BASED ANALYTICAL MODEL FOR EVALUATION OF POWER CONSUMPTION
445
The model presented underestimates energy when the resistance of the line driven by the buffer is comparable to the effective resistance of the transistors in the buffer. Additional efforts
are required to account for these resistive effects [22].
APPENDIX A
COMPUTATION OF THE MAXIMUM SHORT-CIRCUIT CURRENT
Maximum Current for Unloaded Buffers
When the output capacitance is small (i.e., when the shortcircuit current has a greater impact [4]) the circuit behavior is
.
close to the inverter dc operation in the sense that
At the beginning of the transition, the pMOS transistor drives a
current equal to the nMOS saturation current, while at the end of
the transition the pMOS is saturated. In this particular case, the
. Using (7) and
maximum current takes place when
for the nMOS and
(2) and using
for the pMOS,
leads to
(A1)
is the time at which the short-circuit current is
where
is
maximum for unloaded buffers and
Fig. 20. HSPICE and (A3) comparison for 0.35-m technology of the time at
which the short-circuit current is maximum for lightly loaded buffers. Different
inverters with different W =W ratios are considered.
taken as
while the input voltage is described
with a linear ramp [see (2)].
Under these assumptions and neglecting overshooting effects
(that will be included later), (1) becomes
(A6)
(A2)
We found a good approximation to the solution of (A1) for
(which is the range for these parameters) as
given by (7) and
with
using (7) and (2) obtaining
. We solve (A6)
(A7)
(A3)
where
(A8)
where
(A4)
Equation (A7) is used for the linear expression of the pMOS
) in the alpha-power law MOSFET model
current (
(6) with
Equation (A3) leads to the exact solution of (A1) when
, or
, or
,
. Equation (A3) also
. A comgives an accurate description for the case
parison of (A3) to HSPICE simulations is shown in Fig. 20 for
) ratio for
various buffers with different values of the (
0.35- m technology. Once the maximum time is obtained we
derive the maximum short-circuit current for unloaded buffers
from (7), using (2) and (A3)
as
(A9)
(A5)
that are obtained from (A7), (2), and (8), respectively, leading
to
Computation of the Maximum Current for Heavily Loaded
Buffers
values. In this case,
Equation (A3) is inaccurate for large
the current through the pMOS transistor can be neglected and
(A10)
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 4, APRIL 2002
with
(A11)
The time at which the maximum current takes place for
is obtained solving
heavily loaded buffers
(A12)
where
and
take the form
(A13)
Fig. 21. HSPICE simulations of t and t
in 0.18- and 0.35-m process
technologies for a minimum-sized inverter driving another minimum-sized
inverter. Different input rise times are considered.
Now we obtain the maximum short-circuit current for heavily
given by (A13).
loaded buffers computing (6) at
We take into account only the linear dependence of on
to simplify the expression. This approach is justified since the
drain voltage swing during the input transition is not large for
heavily loaded buffers. The result is
(A14)
Combining Both Expressions
and , respecEquations (A12) and (A14) diverge to
. We construct an expression for the maximum
tively, for
and time
that leads to
short-circuit current
and
for large values of
and to
and
for
.
function must be a constant for small output loads
The
is load independent) while for large loads it must
(since
, i.e., a function of the
show the same dependence as
form
(A15)
where is load-independent. An asymptotic function that follows the required limits is
Fig. 22. Overshoot time variation with input rise time for various values of the
output capacitor. The parameter t is nearly independent of C as predicted
by (B5).
The function for the time at which the short-circuit is maximum must lead to (A12) for heavily loaded buffers and to (A3)
for unloaded buffers. Equation (A12) is a function of the form
(where both
and are load-in(independent). We define the linear transformations and
and
version and translation) as
and the linear transformation
(a translation
followed by an inversion). With this transformation we obtain a
function similar to (A15) from
(A16)
(A18)
is the constant value of
where
fore, the equivalent expression for
is
for
in terms of
Thereand
(A17)
is applied to (A3). We define
The same transformation
and
and then obbetween
in (A18) and
tain a smoothing function
using (A16). Then we transform
with the inverse of
ROSSELLÓ AND SEGURA: CHARGE-BASED ANALYTICAL MODEL FOR EVALUATION OF POWER CONSUMPTION
447
(B4)
transformation
function between
(
and
) to obtain a smoothing
Since
, we then have (B4), shown at the top
of the page. The solution of (B4) is
(A19)
(B5)
as
with
,
and
Given that
for the maximum current time, (A19) leads to
(B6)
(A20)
APPENDIX B
OVERSHOOT TIME COMPUTATION
with HSPICE for different
Fig. 22 is a comparison of
. It is shown that this time is almost independent
values of
of the load capacitance as predicted by (B5).
ACKNOWLEDGMENT
An accurate description of the overshoot time requires a detailed modeling of the device behavior; for this reason we use
the MOSFET Model 9 (MM9) [1], [2] to calculate the overshoot
used in (21) and (26).
time
is a nonlinear problem. To avoid
The solution of (1) to get
numerical procedures we compute the time at which the overand relate
to this value.
shoot current is at maximum
and
for a 0.18Fig. 21 shows HSPICE simulations of
and 0.35- m process technology obtained from a minimumsized inverter driving another minimum-sized inverter showing
a linear relationship. The different simulations correspond to
different input rise time values. This relationship can be expressed as
(B1)
since its analytical derivation is simWe will compute
pler than the derivation of
The maximum overshoot time is obtained from (1) neglecting
the nMOS transistor
the short-circuit current. Since at
, (1) is reduced to
is saturated and
(B2)
Using the long-channel approximation of the saturation voltage
[2], [19] and neglecting the
in the denominator of (9) as a first
product term
approximation, the drain saturation current of the nMOS is
(B3)
The authors wish to thank the anonymous reviewers for their
constructive comments.
REFERENCES
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[12] T. Sakurai and R. Newton, “A simple MOSFET model for circuit analysis,” IEEE Trans. Electron. Devices, vol. 38, pp. 887–894, Apr. 1991.
[13] S. Nikolaidis, A. Chatzigeorgiou, and Kyriakis-Bitzaros, “Delay and
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in Proc. IEEE Int. Symp. Circuits Systems, vol. VI, Monterey, CA, May
1998, pp. 368–371.
[14] K. Nose and T. Sakurai, “Analysis and future trend of short-circuit
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Sept. 2000.
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[15] K. O. Jeppson, “Modeling the influence of the transistor gain ratio and
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[16] T. Sakurai and R. Newton, “Delay analysis of series-connected
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[17] U. Weidenmueller, E. O’hAnnaidh, S. Healey, and K. McCarthy, “Implementation of direct extraction methods for compact model parameters. Part I: The FORTRAN code,” Philips Research, Nat. Lab., Unclassified Report 010/97, 1997.
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law MOSFET model,” in Proc. 15th Design Circuits and Integrated Systems Conf., Montpellier, France, Nov. 21–24, 2000, pp. 65–70.
[19] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd
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VLSI. New York: Addison-Wesley, 1990.
[21] J. Qian, S. Pullela, and L. Pillage, “Modeling the effective capacitance
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Power and Timing Modeling. Optimization and Simulation PATMOS
2001, Yverdon-Les-Bains, Switzerland, Sept. 26–28, 2000, paper 4.2.
José Luis Rosselló (M’02) received the M.S. and Ph.D. degrees in physics from
the Balearic Islands University, Spain, in 1996 and 2002, respectively.
He is a Teaching Assistant in the Physics Department, Balearic Islands University. His research interests include device and circuit modeling, CMOS IC
testing, and low-power design.
Jaume Segura (M’94) received the M.S. and Ph.D. degrees from the Balearic
Island University and the Polytechnic University of Catatonia in Spain, respectively.
Since 1993, he has been an Associate Professor in the Physics Department,
Balearic Islands University (UIB), Palma de Mallorca, Spain. He was on leave
from UIB in 1994 and 2001 as an Invited Reasearcher at Philips Semiconductors, USA, and Intel Corporation, respectively. His research interests include
device and circuit modeling and VLSI design and testing.
Dr. Segura has served on the technical program committee of a number of
conferences including the Design and Test in Europe (DATE), the International
On-Line Testing Workshop (IOLTW), and the International workshop on current and Defect Based Testing (DBT). He is also member of the organizing committee of the VLSI Test Symposium (VTS) and served as General Co-Chair of
the IOLTW in 2000.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 7, JULY 2004
1301
An Analytical Charge-Based Compact Delay Model
for Submicrometer CMOS Inverters
José Luis Rosselló and Jaume Segura
Abstract—We develop an accurate analytical expression for
the propagation delay of submicrometer CMOS inverters that
takes into account the short-circuit current, the input–output
coupling capacitance, and the carrier velocity saturation effects, of
increasing importance in submicrometer CMOS technologies. The
model is based on the th-power-law MOSFET model and computes the delay from the charge delivered to the gate. Comparison
with HSPICE level 50 simulations and other previously published
models for a 0.18- m and a 0.35- m process technologies show
significant improvements over previous models.
Index Terms—Analytical model, circuit modeling, delay estimation, submicrometer MOSFETs.
I. INTRODUCTION
T
IMING analysis is one of the most critical topics in very
large-scale integration (VLSI) design. The nonlinear
behavior of CMOS gates requires numerical calculations for
accurate timing analysis at the expenses of large computation
times. Moreover, the impact of design parameters such as
fan-in, fan-out, or transistor sizes on the propagation delay
are difficult to understand and optimize using numerical
procedures.
The dynamic behavior of submicrometer CMOS inverters depends on several nonlinear effects like the velocity saturation of
carriers due to the high electric fields in submicrometer technologies, the short-circuit current appearing when both pMOS
and nMOS transistors conduct simultaneously [1], and the additional effect of the input–output coupling capacitance [2].
Several methods have been proposed to derive the delay
of CMOS inverters [2]–[8] as a first step to describe more
complex gates [9], [10]. Cocchini et al. [3] obtained a piecewise
expression for the propagation delay based on the Berkeley
short-channel IGFET model (BSIM) MOSFET model [11]. The
model included overshooting effects (due to the input-to-output
coupling capacitance) while the short-circuit current was
neglected. Jeppson in [2], and Bisdounis et al. in [4], presented
a model for the output response of CMOS inverters using a
quadratic current-voltage dependence for MOSFET devices
which is not longer valid for submicrometer technologies.
Daga and Auvergne [5] obtained an empirical expression for
Manuscript received May 25, 2003; revised August 31, 2003. This work
was supported in part by the Spanish Ministry of Science and Technology,
in part by the Regional European Development Funds (FEDER) under EU
Project TIC2002-01238, and in part by Intel Laboratories-CRL. This paper was
recommended by Associate Editor A. I. Karsilayan.
The authors are with the Physics Department, Balearic Islands University,
07071 Palma de Mallorca, Spain (e-mail: [email protected]; jaume.segura@
uib.es).
Digital Object Identifier 10.1109/TCSI.2004.830692
the propagation delay taking into account both overshooting
and short-circuit currents.
Hirata et al. [6] derived a propagation delay model with
numerical procedures based on the th-power-law MOSFET
model [12] considering both short-circuit and overshooting
currents. The model provides an accurate description of the
propagation delay but the numerical procedures used in their
analysis increase the computation time considerably. Bisdounis
et al. [7] developed a piecewise solution with seven operation
regions for the transient response of a CMOS inverter based
on the -power-law MOSFET model [13] including both
overshooting and short-circuit currents. Recently, Kabbani
et al. obtained, in [8], a transition time model considering
a quadratic relationship between the saturation current and
the gate–source voltage (assumption only valid for micronic
devices) without considering the effect of the input–output
coupling capacitance. In [9], Sakurai and Newton obtained a
simple expression for the propagation delay of CMOS gates
based on their th-power-law MOSFET model neglecting both
short-circuit and overshooting currents.
In this paper, we propose an analytical model to accurately
compute the propagation delay of a CMOS inverter accounting
for the main effects of submicrometer technologies like the
input–output coupling capacitance, carriers velocity saturation
effects and short-circuit currents. The model is based on an
accurate physically-based th-power-law MOSFET model [14]
and on a previous power dissipation model for CMOS inverters
[15]. The model can be applied to compute the propagation
delay of CMOS inverters and represents a valuable approach
for the evaluation of delay in complex gates as these can be
collapsed to a single equivalent inverter for delay evaluation
[10]. Comparisons with previously published models and
HSPICE simulations using the Philips MOSFET Model 9
(MM9) for 0.18- m and 0.35- m process technologies show
significant improvements in terms of accuracy.
This paper is organized as follows. In Section II, we describe
briefly the switching characteristics of CMOS inverters and
introduce the MOSFET device model used in this work. In
Section III, we derive an analytical charge-based expression
for the switching response of a single pMOS/nMOS transistor
charging/discharging a capacitor, that are generalized to CMOS
inverters in Section IV by including overshooting and short-circuit effects. Section V presents an analytical model for the
output transition time based on the delay model developed. The
model proposed is compared to HSPICE simulations and other
previously published models for a 0.35- m and a 0.18- m
process technology in Section VI. Finally, in Section VII, we
conclude the paper.
1057-7122/04$20.00 © 2004 IEEE
1302
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 7, JULY 2004
dependence of the propagation delay with design parameters is
nonlinear and difficult to model given that (1) cannot be solved
in a closed form even using the simple Shockley MOSFET
model [17]. Moreover, carrier saturation effects become important with technology scaling, thus requiring more complex
MOSFET models accounting for such effects.
The th-power-law MOSFET model [12] is a widely used
short-channel drain-current model, and will be used in this work
to derive the propagation delay and the output transition time of
CMOS inverters. The drain current is given by
Fig. 1. CMOS inverter model.
(3)
II. ANALYSIS OF CMOS INVERTER
SWITCHING CHARACTERISTICS
The dynamic behavior of the CMOS inverter in Fig. 1 is described by
with
(4)
(1)
where
is the output capacitance that is composed by the
drain capacitances of both nMOS and pMOS transistors, the
output node wiring capacitance, and the input capacitance of
and
are the
the gates connected to the inverter output.
are the
output and input voltages, respectively, while and
is the input-topMOS and nMOS currents, respectively.
output coupling capacitance, which is strongly voltage depenwhen the input is low (
) is comdent. The static value of
puted considering the overlap capacitances of both transistor
drains and the gate-to-drain capacitance of the pMOS transistor
that operates in the linear region [16]
(2)
with
and
being the effective channel width of
is the effective channel
pMOS and nMOS, respectively,
length of pMOS, while
and
are the gate–drain underdiffusion for the nMOS and pMOS transistors, respectively. For
is obtained similarly.
a static input high, the capacitance
Fig. 2 illustrates the input and output voltages evolution
of the inverter along with the current through the nMOS
and pMOS transistors for a low-to-high input transition. The
current through the pMOS transistor ( in Fig. 2) has two
components clearly distinguished by the sign of the current.
The negative pMOS current is due to a partial discharge of the
output capacitance from the output node toward the supply
rail and appears when the input–output capacitance drives the
) at the beginning
output voltage beyond the supply value (
of the transition [2]. This effect is known as overshooting and
the time during which the output voltage is beyond the supply
. When the nMOS
value is defined as the overshoot time,
device starts to conduct, it pulls the output voltage down.
, the pMOS current is
Once the output voltage goes below
positive corresponding to the short-circuit component due to
the simultaneous conduction of both devices.
for a high-to-low
The propagation delay (defined as
output transition) is typically defined as the time interval from
voltage input to the 50%
voltage output. The
the 50%
where
,
, and
are the gate, supply, and saturation
is the drain current at
voltages, respectively, and
. The parameter is the velocity saturation index
that ranges between 2 (long-channel devices) and 1 (shortchannel) [12], and describes the channel length modulation.
is given by
The saturation voltage
(5)
is the saturation voltage at
,
The parameter
and
are empirical parameters [12]. These
while
equations are mathematically simpler than physically-based
MOSFET models such as BSIM3v3 or MM9 with the disadvantage that, in the original model developed by Sakurai and
Newton, the relationship between the empirical parameters
and the process parameters supplied by manufacturers is not
provided. Therefore, the variation of th-power-law model
predictions with key parameters like the supply voltage are
not taken into account in the original formulation performed
by Sakurai and Newton, where each parameter must be
recomputed if the supply voltage or any device dimension
change. In this paper, we use the physical formulation for
the th-power-law MOSFET model proposed in [14] and
used in [15]. This physical formulation provides an analytical
relationship between the th-power-law parameters and the
foundry-provided MOSFET parameters.
III. CHARGE-BASED PROPAGATION DELAY OF SINGLE nMOS
DISCHARGING TRANSISTOR
The analysis of discharging a capacitor through a nMOS transistor is developed in Appendix A (for a pMOS charging a capacitor the analysis is equivalent). Four cases are considered depending on the input voltage state (rising or static high) and the
nMOS region of operation (ohmnic or saturation). In this section
we use the output voltage expressions obtained in Appendix A
to evaluate a charge-based expression for the propagation delay.
We state initially some definitions that will be used extensively
during the development of the model.
ROSSELLÓ AND SEGURA: ANALYTICAL CHARGE-BASED COMPACT DELAY MODEL
Fig. 2.
1303
Output voltage and current evolution in the nMOS and pMOS transistors for a rising input linear voltage.
In the context of this work, a fast-output transition refers to
the cases were the nMOS transistor enters in its linear region
while the input is changing. Otherwise (if the nMOS is saturated
), the output transition is considered to be slow.
while
We also define the discharging time
up to a given voltage
as the time interval from the beginning of the input transition
until the instant at which the output is discharged at
(an arbitrary voltage value between 0 and
).
Finally, the propagation delay (
) is defined as the time
to
(See Fig. 2). If
interval from
is defined as the input transition time, the propagation delay
as
is related to for
(6)
In this section, we first obtain an analytical expression of the
discharging time for slow outputs, and then, we correct this
expression to account also for fast outputs. The discharging time
will be expressed in terms of the charge transferred through the
and equal to
).
nMOS transistor (defined as
This charge is expressed in terms of four components
(7)
where
and
are the charges transferred while the input
is rising and the nMOS is in saturation and linear region, respecand
are defined similarly but when the input is
tively.
static high (i.e.,
). The discharging time expression
will be given in terms of these four charge components.
A. Slow-Output Transitions
For a slow-output transition, the nMOS transistor is saturated
during the whole input transition and the output voltage evolution is given by (A6) (see Appendix A). Once the input is high,
the output voltage is described by (A2) and (A4) since the nMOS
is initially saturated and enters the linear region at the end of the
output transition. We express the time needed to discharge the
until
(discharging time) as a funcoutput from
,
,
tion of the charge transferred during each region (
and
) using (A2), (A6), and (A4)
(8)
where
, and
is the velocity saturation index
of nMOS [in general, a subindex
denotes a parameter for
the nMOS(pMOS) ].
,
, and
, we define the saturation
To obtain
, and the linear charge
as the total charge
charge
transferred when the nMOS transistor is in the saturation and in
the linear region respectively. From these definitions, it follows
that
(9)
where
is the maximum charge that can be transferred
through the nMOS transistor operating in the saturation region,
given by
where
as
is the output capacitance. We obtain
from
(10)
where
is given by (9) and
is the maximum charge
that can be transferred through the saturated nMOS transistor
during the input transition. The value of this maximum charge
1304
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 7, JULY 2004
is obtained integrating the nMOS current during the rising input
transition
is obtained by computing the discharging
The value of
time (14) at the end of the input transition (that is, when
). For this special case, we can set that
(11)
Therefore, part of the saturation charge (
) is transferred
), and the other part is transferred
while the input is rising (
while the input voltage remains high (defined as
)
(16)
(12)
After some algebra, (16) leads to
Finally, for the slow-output ramp case we have that
, since by definition, the input is high when the device enters
the linear region.
B. Inclusion of Fast-Output Transition Range
Equation (8) is valid only if the nMOS transistor is saturated
during the whole rising input period (for this case, the term
is zero). For fast-output transitions, the case in which the nMOS
enters in its linear region while the input is rising has no analytical solution (see Appendix A), and an approximation is required for an analytical description of the discharging time.
The delay components of in (8) show mathematical analogies among the terms corresponding to the period during which
the input is rising (the two first terms), and those corresponding
to the input being static high (the two last). The time during
which the nMOS is saturated and the input is high is given by
) while the time during
the third term in (8), (that is,
which the nMOS is saturated but the input is rising also contains
) but corrected with
the same charge to current ratio (
an expression that depends on the transition time and the saturation velocity
(13)
When the output transition is fast, the linear charge is nonzero
), and must appear in the
when the input is rising (i.e.,
in assuming
delay expression of . We include the term
that the charge component due to the static and dynamic input
periods are of the same form
(17)
In (17), we use
because the input transition is
) and
achieves its maximum value. The
finished (
is obtained solving (17)
value of
(18)
where
is given by (11). Finally,
is obtained from
(19)
In Fig. 3, we plot HSPICE simulations of the output response
of a single discharging nMOS transistor for a 0.35- m technology showing very good accuracy. Both slow- and fast-output
transitions are simulated for various output capacitance values
to
, where
is the input capacitance of
(from
a minimum sized inverter). From (14), the propagation delay is
obtained applying (6).
IV. PROPAGATION DELAY FOR CMOS INVERTER
In this section, we consider a whole inverter (and not only
a charging/discharging transistor) and include the effect of
the short-circuit (due to the pMOS/nMOS transistor during
the discharging/charging process) and overshooting currents
). Their
(due to the input–output coupling capacitance
contribution is included as additional charges to be transferred
through the charging/discharging transistor. We develop only
the discharging case as the charging case is equivalent.
A. General Equation
(14)
From (14), we must evaluate the parameters
and
.
Similar to the previous analysis of the saturation charge, the
)
linear charge transferred during the rising input transition (
that is the maximum
is bounded by a maximum value
charge that can be transferred through the nMOS transistor operating in the linear region while the input is rising
(15)
The charge transferred from the output capacitances (both
and
in Fig. 1) through the nMOS transistor ( ) is computed from the difference between the charge initially stored at
and the charge remaining in
the output node
this node when the output voltage reaches the desired value .
, we have
Assuming that
(20)
where
and
are the sum of the
output capacitances when the input is low and high, respectively.
and
, while, when
, we
Initially,
ROSSELLÓ AND SEGURA: ANALYTICAL CHARGE-BASED COMPACT DELAY MODEL
Fig. 3. Falling transition for a W=L
assume that
is
charge
1305
=2-m/0.35-m nMOS transistor with different output loads (the input rise time is fixed to 200 ps).
. From (20), the maximum saturation
(21)
For the evaluation of the propagation delay, we are interested
in the charge transferred only from the output capacitances
and
through the nMOS transistor. Therefore, we use the
same terms defined in the previous section for charges
,
,
, and
. It is important to remark that, by definition, these charges come from the capacitances connected to
the output node and therefore do not include short-circuit con, the maximum value of saturation
tribution. Therefore,
charge during the rising input, is obtained from (11) by substracting the short-circuit charge transferred (SCCT)
(22)
where
is the SCCT for a rising input transition. The expression of this component is taken from [15].
The charge transferred through the nMOS transistor comes
from the output capacitances ( ) and the power supply through
the pMOS transistor (SCCT). The propagation delay is computed considering both contributions by including an additional
charge (a fraction of the SCCT) to the charge transferred from
the output capacitances. Therefore, from (6) and (14), the propagation delay expression is given by
is a fraction of the SCCT (
) and is defined as
where
.
the SCCT during the time interval such that
This short-circuit charge is added to the saturation charge
for simplicity. The expression used for the evaluation of
is
,
,
computed in the Appendix B while parameters
and
are computed at
.
V. OUTPUT TRANSITION TIME COMPUTATION (
)
The effective output transition time
can be related to a
percentage of the
derivative at the half
point. Using
from the 70% of
this property, Sakurai et al. approximate
derivative [9]. From SPICE simulations, we observed
the
that the output voltage shape is different depending on the relative switching speed between the input an the output voltages.
For fast-output transitions (see Fig. 4), the output voltage evolution is close to the dc voltage characteristics of the inverter and
(since the
the output transition slope is strongly dependent of
). For slow-output
nMOS conductance mainly depends on
transitions (see Fig. 5), the output voltage slope is nearly conalmost from the
stant since the nMOS gate voltage is at
beginning of the output transition. Therefore, the percentage of
derivative at
that must be used to compute
the
depends on the relative switching speed of
and
, varying
from 90% to 40% for a slow or fast-output transitions respectively. We use an empirical expression for the output transition
that takes into account this effect
time
(24)
(23)
ratio provides the information of the relawhere the
tive switching speed between the two nodes. This ratio is close
to 0 or greater than 1 for fast and slow output transitions reand
is given in Apspectively. The exact definition of
used in (24) shows an expendix B. The expression for
cellent agreement with respect to HSPICE simulations for both
1306
Fig. 4.
and t
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 7, JULY 2004
Comparison between HSPICE simulations of inverter output switching characteristics and model predictions for a fast-output transition (C
= 600 ps).
Fig. 5. Comparison between HSPICE simulations of inverter output switching characteristics and model predictions for a slow-output transition (C
and t = 50 ps).
slow and fast-output transitions. In the analysis for the evaluaderivative at
the short-circuit and overtion of the
shooting currents are neglected for simplicity.
is obtained from the discharging time
The derivative
as
=C
= 100C
depending on the transistor state at
. For the special case in which the input is high, the
discharging time derivative is
(25)
where
. The derivative
must be
. At this time point, the transistor
computed for
can be in the linear or saturation region and the input can be
rising or already at the high value. Therefore,
Note that when
, we obtain the case in
, see (14)], and
which the nMOS is saturated [that is,
the device is in the linear region when
when
and (25) leads to
.
ROSSELLÓ AND SEGURA: ANALYTICAL CHARGE-BASED COMPACT DELAY MODEL
Fig. 6.
1307
Propagation delay versus input rise time for different values of the configuration ratio.
If the input voltage is rising when the output is at
can be simplified to
discharging time at
, the
(26)
where
is given by
(27)
Therefore,
is given by
(28)
Since
is similar to (25), then
We use the following expression for
(25) and (29) for each case:
(29)
that leads to
(30)
Note that the power term in (30) is equal to 1 when
and (25) is recovered. Finally, the derivative
at
is
of
(31)
This expression is valid for both fast- and slow-output
transitions.
VI. RESULTS
We plotted model results versus HSPICE level 50 simulations
for a 0.35- m and for a 0.18- m technology. Results show that
the propagation delay versus the input transition time, the supply
voltage, and the
ratio.
In Figs. 4 and 5, we show the output waveform of a CMOS
inverter driven by a slow and a fast input transition, respectively
(with parameters
fF,
600 ps and
500 fF,
50 ps, respectively). Both figures show that the model
developed for the propagation delay and the output time approximate the output response of the inverter with very good
accuracy.
In Fig. 6, we plot the propagation delay
versus the
input time
for different values of the
ratio for a
0.35- m technology. HSPICE simulations (dots) are compared
to the model proposed and to a previous model [3]. Since the
short-circuit current is not taken into account in the model in
[3], the propagation delay is underestimated. The model in
[3] proposes a piecewise solution of the propagation delay,
i.e., depending on the input transition (fast or slow input
transitions) it uses an approximated or an exact expression.
The approximated propagation delay is used when the nMOS
transistors change from the saturation to the linear region and
the input is rising [3, eq. (11)]. Otherwise, an exact expression
for the output response is used. This leads to a discontinuity
in the propagation delay when changing between regions (see
Fig. 6).
Fig. 7 plots the propagation delay versus the input rise time
for a 0.18- m technology. When the
ratio is small the
propagation delay decreases for increasing input rise times. The
model in this work (solid lines) provides an excellent approximation to HSPICE simulations (dots) while previously published models [6], [7], that account for both overshooting and
short-circuit currents, lead to underestimations.
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 7, JULY 2004
Fig. 7. Propagation delay versus input rise time for different values of the configuration ratio for a 0.18-m technology.
Fig. 8.
Propagation delay versus supply voltage for a 0.18-m technology.
Fig. 8 is a plot of HSPICE simulations (dots) and model predictions of the propagation delay versus the supply voltage.
The model proposed in this paper provides a much better fit
of the delay than the models in [6] and [7], especially for the
low-voltage regime. The model in [7] shows discontinuities because it uses different expressions (Taylor series expansions)
for the output response depending on the operation region of
transistors.
In Fig. 9, we show the propagation delay variation with
temperature for three different supply voltage values. Different
trends can be appreciated for each supply voltage value when
increasing temperature. The propagation delay increases for
1.8 V, while for
0.9 V, the propagation
delay decreases. This effect is described properly by the
proposed model since we are using the physically-based
th-power-law MOSFET model developed in [14] that relates
the th-power-law parameters to physical parameters (that are
temperature-dependent) as the carrier mobility. For a more
detailed description of this model, the reader is referred to [14],
[15].
Fig. 10 plots the output switching response of a CMOS in,
verter for different output loads (
and
) for a 0.18- m technology. It is shown that
the model provides an excellent description of the gate delay, as
the deviation of the output voltage with respect to the simulais very small.
tions at
Table I compares the model with HSPICE simulations of
the propagation delay for a 60-CMOS inverters chain with
ROSSELLÓ AND SEGURA: ANALYTICAL CHARGE-BASED COMPACT DELAY MODEL
Fig. 9.
Fig. 10.
1309
Propagation delay versus temperature. Different delay trends versus temperature can be appreciated at different supply voltages.
Comparison between HSPICE simulations of inverter output switching characteristics and model predictions.
TABLE I
DELAY VALUES OF 60-INVERTER CHAIN FOR 0.18-m TECHNOLOGY AT
DIFFERENT SUPPLY VOLTAGES
10 m 5 m and
m for different
power supply values. A 1-GHz input signal drives the first
inverter input. This experiment is used to check both the output
transition time and the propagation delay model developed
since the propagation delay of each stage is dependent on its
of
input rise time , that is, the output transition time
the previous stage. The proposed model provides very good
accuracy with respect to HSPICE.
In Table II, we show the mean error of the model proposed
and the models in [6] and [7] with respect to HSPICE simulations performed in Figs. 6–8. As can be appreciated, the model
proposed provides a better accuracy than previously published
models for scaled technologies. Table III compares the comcalculations of the propagaputation time used to perform
tion delay of one single inverter with different analytical models
and HSPICE simulations using a Pentium-III 500-MHz pro-
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 7, JULY 2004
TABLE II
MEAN ERROR FOR PROPOSED MODEL AND PREVIOUSLY PUBLISHED MODELS
FOR 0.35-m AND 0.18-m TECHNOLOGIES
subindex
that
is referring to the nMOS value of
). Assuming
, then, the solution of (A1) leads to
(A2)
CASE 2: nMOS in the Linear Region and
: This
case is more complex since the nMOS current depends on the
output voltage. Using the linear expression for the nMOS current (3), then
(A3)
We solve (A3) with the initial condition
obtaining
TABLE III
COMPUTATION TIME OF 10 TRANSITIONS WITH PENTIUM–III
PROCESSOR@500 MHz
(A4)
CASE 3: nMOS Saturated and the Input is Rising: We model
a rising input transition as a linear function of the form
(A5)
cessor. As expected, analytical models are much more faster
than HSPICE (about three orders of magnitude). The model in
[6] leads to a greater computation time due to the use of numerical procedures.
VII. CONCLUSION
An accurate analytical expression to compute the propagation delay and the output transition time of CMOS inverters
based on charge analysis has been presented. The main effects
present in current submicrometer CMOS technologies like the
input–output coupling capacitance, carriers velocity saturation
effects and short-circuit currents are taken into account in a
single analytical expression. The model is compared to HSPICE
simulations (using the MM9 model) and to other previously
published works for a 0.18- m and a 0.35- m process technology reporting a high degree of accuracy. It provides an analytical relationship of the delay to design parameters (device
dimensions), input transition time, supply voltage, and temperature. The model is an accurate tool to compute the propagation delay and the input rise/fall time. It provides up to 15%
and 100% of improvement in computing time with respect the
models presented in [7] and [6], respectively, and a 1000
factor with respect to HSPICE simulations.
APPENDIX A
DERIVATION OF OUTPUT RESPONSE OF SINGLE nMOS
DISCHARGING TRANSISTOR
The differential equation to be solved is derived from (1)
(A1)
The output voltage evolution depends on the nMOS current
expression and the initial condition at
. Therefore, there
depending on the input
will be different solutions for
voltage evolution and the operation region of the transistor
(linear or saturation). We derive the analytical solution for each
case.
CASE 1: nMOS Saturated and
: For this case,
the nMOS current expression is fixed at
(where the
where
is the input rise time. At the beginning of the
. When the
transition, the nMOS is off and
input voltage goes beyond the nMOS threshold voltage (i.e.,
), the nMOS transistor starts to
conduct in the saturation region. The initial condition is given
. We solve (A1) using (4) and (A5) and
by
neglecting channel-length modulation as a first approach
(A6)
is the velocity saturation index of nMOS.
where
CASE 4: nMOS in the Linear Region and the Input is
Rising: For this case, the differential equation (A1) has no
analytical solution.
APPENDIX B
DERIVATION OF SHORT-CIRCUIT CHARGE TRANSFERRED AT
The propagation delay, defined as the time interval between
the time points at which the input and output voltages are at
, depends on the SCCT during this interval. This charge
(for a rising input transition, for a falling input
is defined as
transition we use the notation ) and is a fraction of the total
SCCT during the transition. We obtain an empirical expression
as a function of the total SCCT (
) developed in [15].
of
This empirical relationship is developed considering both fast
and slow-output transitions.
For slow-output transitions, the input is high before
and
can be considered to be equal to
. For fastoutput transitions the short-circuit current is maximum when
and the SCCT at this time point ( ) can be
).
approximated to the half value of the total SCCT (
is dependent on the relative switching
Therefore, since
as
speed of the input with respect to the output, we express
a function of the ratio
, where parameters
and
depends on the output and the input transition time and
and
.
are defined as
the input is considered slow and the SCCT
If
is taken as
. If
we consider that
ROSSELLÓ AND SEGURA: ANALYTICAL CHARGE-BASED COMPACT DELAY MODEL
the input is fast and the expression for the short-circuit charge
is
. The parameter
is derived from
at
(14) (considering the nMOS transistor in saturation, neglecting
for
the short-circuit charge and assuming that
simplicity)
(B1)
Therefore, the relative switching speed
is
(B2)
An empirical expression is used for
as a function of
. A linear relationship of
with respect to the ratio
is used for an output response with a value of
lower than a threshold time
. Otherwise, we take
constant and equal to
(B3)
Parameter is taken such that
is the time at which
the pMOS transistor enters in the off state (that is, when
, the short-circuit current ceases and we can consider that
). From this restriction, we find parameter to be
(B4)
and
expressed
The empirical relationship between
in (B3) is found to be with a good agreement with HSPICE
simulations over a wide variation of inverter configurations and
transistor sizes.
The total SCCT is obtained from the model in [15]
(B5)
is the overshoot time (see Fig. 2),
is the time
where
at which the short-circuit current is maximum,
is the time
is the maxduring which the short-circuit takes place and
imum short-circuit current.
The input–output coupling capacitance is taken into account
in the exponential term while the maxthrough parameter
takes into account both slowimum short-circuit current
and fast-output transitions. The detailed description of all parameters involved are extensively explained in [15].
REFERENCES
[1] H. Veendrick, “Short-circuit dissipation of static CMOS circuitry and
its impact on the design of buffer circuits,” IEEE J. Solid-State Circuits,
vol. SC-19, pp. 468–473, Aug. 1984.
[2] K. O. Jeppson, “Modeling the influence of the transistor gain ratio and
the input-to-output coupling capacitance of the CMOS inverter delay,”
IEEE J. Solid-State Circuits, vol. 29, pp. 646–654, June 1994.
1311
[3] P. Cocchini, G. Piccinini, and M. Zamboni, “A comprehensive submicrometer MOST delay model and its application to CMOS buffers,”
IEEE J. Solid-State Circuits, vol. 32, pp. 1254–1262, Aug. 1997.
[4] L. Bisdounis, S. Nikolaidis, and O. Koufopavlou, “Propagation delay
and short-circuit power dissipation modeling of the CMOS inverter,”
IEEE Trans. Circuits Syst. I, vol. 45, pp. 259–270, Mar. 1998.
[5] J. M. Daga and D. Auvergne, “A comprehensive delay macro modeling
for submicrometer CMOS logics,” IEEE J. Solid-State Circuits, vol. 34,
pp. 42–55, Jan. 1999.
[6] A. Hirata, H. Onodera, and K. Tamaru, “Estimation of propagation delay
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[7] L. Bisdounis, S. Nikolaidis, and O. Koufopavlou, “Analytical transient
response and propagation delay evaluation of the CMOS inverter
for short-channel devices,” IEEE J. Solid-State Circuits, vol. 33, pp.
302–306, Feb. 1998.
[8] A. Kabbani, D. Alkhalili, and A. J. al-Khalili, “Technology portable analytical model for DSM CMOS inverter transition time estimation,” IEEE
Trans. Computer-Aided Design, vol. 22, pp. 1177–1187, Sept. 2003.
[9] T. Sakurai and R. Newton, “Delay analysis of series-connected
MOSFET circuits,” IEEE J. Solid-State Circuits, vol. 26, pp. 122–131,
Feb. 1991.
[10] J. L. Rosselló and J. Segura, “Simple and accurate propagation delay
model for submicron CMOS gates based on charge analysis,” Electron.
Lett., vol. 38, no. 15, pp. 772–774, 2002.
[11] D. Foty, MOSFET Modeling with SPICE. Principles and Practice.
Englewood Cliffs, NJ: Prentice-Hall, 1997.
[12] T. Sakurai and R. Newton, “A simple MOSFET model for circuit analysis,” IEEE Trans. Electron Devices, vol. 38, pp. 887–894, Apr. 1991.
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[13]
inverter delay and other formulas,” IEEE J. Solid-State Circuits, vol. 25,
pp. 584–594, Apr. 1990.
[14] J. L. Rosselló and J. Segura, “A physically-based nth power-law
MOSFET model for efficient CAD implementation,” in Proc. 18th
Design of Circuits and Integrated Systems Conf. (DCIS’03), Ciudad
Real, Spain, Nov. 19–21, 2003, pp. 380–383.
[15]
, “Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers,” IEEE Trans. Computer-Aided
Design, vol. 21, pp. 433–448, Apr. 2002.
[16] J. E. Meyer, “MOS models and circuit simulation,” RCA Rev., vol. 32,
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1365–1376, Nov 1952.
José Luis Rosselló received the M.S. and Ph.D. degrees in physics from the University of the Balearic
Islands, Palma de Mallorca, Spain, in 1996 and 2002,
respectively.
He is currently an Associate Professor at the same
university. His research interests include device and
circuit modeling, very large-scale integration design
and test, and low-temperature CMOS design.
Jaume Segura received the M.S. and the Ph.D.
degreed from the University of the Balearic Islands
(UIB), Palma de Mallorca, Spain, in 1989 and 1992,
respectively.
He has been an Associate Professor at UIB since
1993. He was an Invited Researcher at Philips Semiconductors, Hilsboro, OR, in 1994, and Intel Corporation, Hilsboro, OR,, in 2001, on sabbatical from the
UIB. His research interests include device and circuit
modeling and very large-scale integration design and
test.
Prof. Segura is the Chairman of the IEEE Circuits and Systems Spanish
Section.
Transient Current Testing Based on Current (Charge) Integration
I. de Patil, R. Picas, J.L. Rossell6, M. R.oca, E. Isern, J. Segura and C. F. Hawkins*
Physics Depa.rtment, Balearic Islands University, 07071 Palma de Ma,llorca,, SPAIN
* EECE Dept., The U niversity of New Mexico and Sandia. Na.tional Labs.,
Albuquerque, NM 57131, ‘IISA
Abstract
We present experimental data from a. test, chip
where several defects can be activated. The transient
current was measured and t,he integrated value of the
charge computed. ‘This work analyzed the sensitivity
of the met.hod t.o defect location, circuit topology, and
input stimuli. The next sect,ion describes the experimental met,hods. Section 3 discusses result,s, while
Section 4 summarizes the work.
We evaluated a technique that uses power supply
charge as the test observable. Charge was c o m p u t e d
from the measured supply transient current waveform.
Data shorn that this method is eficient to detect those
defects that prevent current elevation (mainly “hard”
opens) and therefore represents a valid extension of
IDDQ
1
2
Introduction
The experiments used an &bit shift, register in
which several mask defects were designed. We evaluated the charge based test, technique to detect hard
opens (i.e. those t#hat prevent current elevation).
Transmission gates were connected to selected nodes
of the circuit to emulate t,he presence of open defects,
and were controlled with a 5 to 132 decoder t,o reduce
circuit PIN count. Each decoder input, combination
activated a unique open defect by turning off a given
transmission gate. When a t,ransmission ga.te is off
(i.e. it does not propa.gate signal), we say that its corresponding open defect is activated. The code 00000
does not activat,e any defect and was used t,o obt,a.in a
reference measure from the fault. free circuit. Fig l(a)
is a schematic of t.he 8 bit shift register with the t,ra.nsmission gates labeled for ea.ch defect,. Fig l(b) shows
a detailed design of the single flip-flops composing the
shift register.
The circuit was designed with ES2 n-well dual
metal 1.0 p m technology. Separate PADS were used
for the B-bit. shift register core I,,>0 supply, the decoder and the input/output PADs. Measurements
were taken at the 1’0~ circuit pin to avoid ground
noise from input/output PADS and decoder switching.
Current was measured by sensing the voltage drop at)
a very-low inductive MP930 Caddok 300 R resistor
with a Tektronix P6247 1 GHz bandwidth differential
probe connected to a TDS640 ‘Tektronix scope with a
2 Gs/s sampling rate. A dedicat,ed board with differ-
Current testing (or IDDQ testing) is a widely used
method to verify digital CMOS ICs. The main advantage of IDDQ is the high observability that allows a
high defect coverage with a relatively small set of test,
vectors. Opens can leave internal nodes at intermediate voltages, and cause quiescent current elevation
that is easily detected with this technique. Despite
this, IDDQ has limitations in detecting those defects
that prevent current elevation (mainly certain opens).
Several techniques are under development. to overcome these limitations and extend the use of current
monitoring. Most of t#he t,echniques point toward dynamic current testing that monitors the power consumption not only during the quiescent periods, but
also during the transients.
Different transient techniques have been proposed.
Beasley et al. [l] analyzed the idd signature when pulsing both VDD and GND levels from an intermediate
value to their nominal values. Maki et al. [2] analyzed the change in the transient current peaks to
detect defect,s in the circuit, while Plusquelic [3] and
Vinnakota [4] considered both time and frequency domains while monitoring the signal. Cole et al. [5] measured the transient 2100 signature to detect defects.
Our work used the power supply charge driven into
the circuit during a single transition or a set of transitions as the observable for test. This parameter is
directly related to the transient current. The principles of this technique were given in [6].
26
O-8186-9191-3/98 $10.00 0 1998 IEEE
Experimental Methods
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Loaded value
STTVHI
0 ~~l~O~l~O~l~~~l~0~
STTVDZ
0 +(o~l~ollfo~l~o~l~
STTVD3
0 -+~0~0~1~0f1~0~1~0~
STTVD4
0 +[o(o~oll~ollloll~
STTVDS
0 +[ololololllolllo]
STTVD6
0 +(o~o~olo~o~llo~l
STTVD, 0 + o~ololo~ololl~o
MASTER :
SLAVE
STTVD8
0 + o~o~olo~ololo~l~
STTVK
0 +~o~o~o~o(o~olo~o~
Figure 2: S T T V s u s e d lo detect each defect. The
charge is measured at the rising or falling clock edge
- Class-a. Opens preventing data propagation at
the output of one flip-flop (t,ransmission gates labeled as Oi).
- Class-b. Opens preventing clock propagat,ion
from the defect site t,o the end of t,he regist,er
(transmission gates labeled as Ki).
Figure 1: &bit shift register used to measure the charge
(a). The flap-flop d esign is reported
in
(b).
- Class-c. Opens preventing clock signal t,o a single
latch wit,hout, affecting clock propagation to ot,her
cells of the register (transmission gates labeled as
Hi or 1i)
ent supply planes for core and PADS, and two ground
planes connected with a low frequency bridge to avoid
loop currents [7] was designed to minimize switching
(high frequency) noise. Measurements were compared
to HSPICE simulations from the extracted layout to
evaluate the noise contribution. 50 waveform currents
were measured and averaged for each test, vector. The
charge was computed by numerical integration of the
current waveform.
The appropriate test vectors for each defect were
generated following the procedure in [6]. Since this
technique monitors the transient current, the test vectors were calculated to induce a given transition rather
than setting a static input. For this reason we refer
to State Transition Test Vectors (STTV) instead of
static test vectors. STTVs were chosen to induce a
current path in the fault free circuit that is missing in
the defective one because of the defect. This depends
on the defect site and its effect on the circuit. The
mask generated defects shown in Fig l(a) can be put
into three classes:
The charge difference bebween the faulty and t,he
fault-free circuit can be maximized by shifting a STTV
into the chain that:
1. Does not change the stat,e of the flip-flops located
between the chain input and the defect site, and
2. Induces a state transition t,o all the flip-flops between the defect site and the output.
This maximizes the charge difference between the
fault, free and faulty circuit. Following this rule we derived one STTV for each defect (Fig. 2). The STTV
derived for defect d (STTL’~) was used to measure the
transient current at the rising and falling edge of t#he
clock transition with data settled (Fig. 2).The STTV
that complements all bits of each STTl/d (referred to
as STTVd) was also used following rules 1 and 2 described before.
We measured the transient current through the circuit power supply. A difference bet,ween idd(t) a.nd
27
0. I m/div
0
t (SW)
I eon
lOn/div
Figure 3: Transient current waveforms for circuit of
Fig.1 measured at the rising and falling clock edges
when no defect activated.
b)
IDDQ is that, for a given vector, the current signature
differs if it is measured at the power supply or at the
ground rail, because of the charge contribution coming from the logic gate output capacitor loads. Additionally different charge values will be obtained when
sensing the current at the rising or falling edge of the
clock. This is shown in Fig. 3 where two waveform
currents measured at the rising and falling edges of
the clock for the same STTV are reported.
3
/
i ’
I’
_.
K7
K4
0
IOon
I Onfdiv
t (see)
Figure 4: Transient current waveforms measured for
the same STTV at the good circuit and activating def e c t s Ii’2 to I& ( a ) , and their corresponding charge
values with time (b).
Results and Discussion
Figure 4(a) shows eight current waveforms measured for STTVK (Fig 2) when Ka, . . , Ii’s are activated and for the fault free configuration. Current
contributions are due to switching of the flip-flop clock
inverters (Fig. 1.b) since STTVK does not, change any
register data values. The largest current peak was obtained for the fault free configuration because all flipflops are driven by the clock. A smaller current, peak
was obta.ined when defect 1<s was activated. This defect isolates the last flip-flop (FF8 in Fig. l(a)) from
the clock signal, so tha.t the corresponding inverters
do not change, and therefore do not contribute to the
transient current. Defect I<7 isolates flip-flops FF7
and FF8 from the clock further reducing circuit activity that leads to a smaller current peak (Fig. 4). Less
activity is observed when the active defect is closer
to t,he input clock signal which is consistent wit,h the
successively smaller current waveforms.
Figure 4(b) shows the charge variation with time for
each current waveform in Fig. 4(a). The charge corresponds to the area produced by each current waveform. The stable cha.rge value as an observable for test
provides an efficient way of comparing current peaks,
as current waveform shapes can vary significantly even
for the same STTV (Fig 3).
The values of the charge used to distinguish good
and bad circuits were estimat,ed taking int,o account
the charge resolution of the measurement system and
fabrication process parameter variations.
The resolution measurement is given by the instrumentation as
AQmeas =
to,
AK,, + Vau At,,,
R SenS
(1)
where t,, is the average width of the current peak,
V,, is tha average voltage drop at the resistor, At,,,
is the minimum time resolution of the oscilloscope,
and AV,,, its minimum vertical resolution. R,,,, is
the resistor used for the measurement.. In our case
t,, = 40 ns, V,, = 150 mV, At,,, = 500 ps, AV,,, =
5 mV, and R,,,, = 300 R f l%, giving a resolution
of 916.6 fC.
28
Table 1: Charge values fin pC) for class a) defects.
Clock transition
Q (DC1 11
s
”
-
Active
Low -+ High
defect
QnO def 1 Qdej
L
,-
,
Table 2: Charge values (in PC) for class b) deft
”
Q
Q no dej
13.2
12.7
D4
D5
12.0
12.4
Ds
11.7
D7
11.1
D8
10.8
12.9
D3
12.6
II
11.8
‘TVI<
- 0.3
11.8
- 0.3
11.8
- 0.1
2.8
13.1
0.6
3.8
11.8
10.4
11.8
10.1
19.9
12.1
10.1
17.5
12.0
11.6
1.2
1.9
1.7
5.0
3.7
6.8
7.1
9.2
-ll
11.8
“TVI;
- 0.5
STTVD,
D2
Clock transition
Qdej
STTV:,
D2
D3
(PC) I/
High -+ Low
12.2
1.3
2.0
D4
12.2
10.1
17.6
12.0
2.8
D5
11.8
13.1
15.7
14.5
3.9
Ds
11.3
10.0
15.4
12.1
5.3
D7
10.9
9.9
14.0
12.2
7.2
DS
10.4
10.0
13.8
12.2
I 9.7
’ STTV~a as listed in Fig. 2 for each defect
‘* bit a bit complement of STTVs as listed in Fig. 2
difference in this case required minimizing circuit activity from FFl to FF7, while maximizing activity of
FF8. The results are consistent because:
The second factor to account for is current variation
with process deviations. We estimated this variation
by simulation using corner parameters supplied by the
manufacturer. We obtained AQpar = 0.83 PC, therefore we choose the charge resolution AQfes = 1 PC.
If Q iT;y, is the charge obtained for STTVi when
no defect is activated, and Qz,‘,T:’ the charge obtained
when defect j is activated, we consider such defect is
detectable if
IQ
STTV, _
def j
STTV1
Qno
d e j (>
AQ,.es
Since the transient current was measured at r/bn,
more charge occurrs when the output load capacitance is charged, i.e when the output changes
from zero to one. Therefore we must know which
is the largest output capacitance in the cell and
induce such a transition at that node.
The larger charge transference involved in FF8
will occur when the slave changes from zero to
one, as its output capacitance is much larger than
the output capacitance of the master cell. The
output of FF8 changes from zero to one at the
falling clock edge of STTVD, and the defect is
only detected in this case.
(2)
Tables 1, 2, and 3 report the charge values measured for defect classes a, b and c respectively, and
the fault free circuit. When a defect, is activated its
corresponding STTV in Fig. 2 and STTV is used. In
those cases where (2) did not hold, values are shown
in bold indicating that the defect was not detected.
For class-a defects we used a different STTV for
each Di. Results showed that defects D5, D7 and Dg
were not detected by their corresponding STTV at the
rising clock edge. However 05 and D7 can be detected
by the same STTV if current is measured at the falling
clock edge. Detection of Dg can only be achieved by
measuring the transient current at the falling edge of
STTVD, (AQ = 1.6 PC). Defect Dg was initially expected to be hard to detect because the activity difference between the fault free and the faulty circuit
is due only to a single flip-flop. A measurable charge
All class-b defects were tested with the same STTV.
Results show that all defects can be detected at the
rising or falling clock transition while using STTVK
or its complement. Charge differences are large for
defects close to the clock input and decrease as the
defect is close to the output as expected.
Class-c defects were initially thought to be hard
to detect, as they isolate the clock signal to a single
latch of the chain without affecting the others. Results
show that Hi defects are easier to detect than 4 defects, since most of them can be detected at the rising
and t#he falling clock edge. Ha was interesting since it
29
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Threshold voltage variation with channel length
Alpha-exponent variation with channel length
0.8
1.7
VTO (Hspice Lev 50)
VTH (Sakurai fitting)
0.78
1.6
p-MOS
0.76
0.74
n-MOS
1.5
p-MOS
1.4
alpha
VTH (V)
0.72
0.7
0.68
n-MOS
Model
Sakurai et al.
1.3
n-MOS
0.66
1.2
0.64
p-MOS
1.1
0.62
0.6
0
0.5
1
1.5
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2
2.5
3
1
0
0.5
1
1.5
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2
2.5
3
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hii
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3.5
3
5
4. 4.
2
1.5
1
+;,
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Model
Sak
HSPICE
2.5
Isat (mA)
5 Lgv @ Yjw Ygvdw Ygvdw
5
Yjw
56 Yjw 4
5
+<,
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
Vgs(V)
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p
vdwxudwlrq fxuuhqw iru d 3168
ghylfh
zlwk h{suhvvhg dv=
p-MOS Saturation current vs. gate voltage (L=0.35um,W=1..6um)
@4.
7
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4 N .
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iru vwurqj lqyhuvlrq dqg Y VE[ lv d yrowdjh ri wudq0
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dqg YG3 iurp htxdwlrq +:, dqg +<, e| xvlqj YG3 @
Ygvdw +Yjv @ YGG , dqg LG3 @ Lgv +Yjv @ YGG , =
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ri wkh wkuhvkrog yrowdjh lv rewdlqhg e| vroylqj +6,
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Ywk @ YWK 3 3YGG
+44,
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wdnhq dv=
1.4
&
4
4
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Ouhi
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4
4
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Z
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hii
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ohqjwk ghshqghqfh ri wkh wkuhvkrog yrowdjh/ dqg VZ
lv wkh zlgwk ghshqghqfh sdudphwhu ri wkh wkuhvk0
rog yrowdjh1 Ilqdoo|/ Ouhi dqg Zuhi duh d uhihuhqfh
1.2
Model
Sak
HSPICE
1
Isat (mA)
%
0.8
0.6
0.4
0.2
0
0
0.5
1
1.5
2
2.5
3
3.5
Vgs(V)
Iljxuh 7 ~ s0PRV
p
vdwxudwlrq fxuuhqw iru d 3168
ghylfh
fkdqqho ohqjwk dqg zlwk iru d jlyhq whfkqrorj|1 Doo
wkh sdudphwhuv frqvlghuhg duh lqfoxghg lq wkh PRV0
IHW prgho < surfhvv sdudphwhuv vhw dqg dffrxqw
iru vhyhudo vkruw0fkdqqho hhfwv dv wkh gudlq0lqgxfhg
eduulhu orzhulqj ru wkh wkuhvkrog yrowdjh uroo0xs1
D vlpsoh dqg xvhixo irup wr h{suhvv wkh h{sr0
qhqw lq whupv ri yhorflw| vdwxudwlrq frhflhqwv lv=
@ 4 . hii 3 Yjv @YGG
+46,
zkhuh hii lv wkh hhfwlyh prelolw| frhflhqw jlyhq
e| +;,1 Ht1 +46, lv yhu| hhfwlyh lq ghvfulelqj wkh
uhodwlrqvkls ehwzhhq wkh vdwxudwlrq fxuuhqw dqg wkh
jdwh yrowdjh1 Ht1 +46, dovr erxqgv wkh ydoxhv
n-MOS Saturation current vs. gate voltage (L=3.0um,W=1..6um)
p-MOS Saturation current vs. gate voltage (L=3.0um,W=1..6um)
0.9
0.18
0.8
0.16
0.7
0.5
0.14
0.12
Model
Sak
HSPICE
Isat (mA)
Isat (mA)
0.6
Model
Sak
HSPICE
0.4
0.1
0.08
0.3
0.06
0.2
0.04
0.1
0.02
0
0
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
Vgs(V)
Iljxuh 8 ~
q0PRV vdwxudwlrq fxuuhqw iru d 613
1
1.5
2
2.5
3
3.5
Vgs(V)
p
Iljxuh 9 ~
p
s0PRV vdwxudwlrq fxuuhqw iru d 613
ghylfh
ghylfh
olnh wkh ruljlqdo Doskd0srzhu prgho vlqfh iru orqj0
fkdqqho wudqvlvwruv/ @ 5 +vlqfh hii @ 3 , zkloh
iru vkruw0fkdqqho wklv h{suhvvlrq whqgv wr 41 Ilj1 5
vkrzv d frpsdulvrq ehwzhhq htxdwlrq +46, dqg +7,
iru ydulrxv ydoxhv ri fkdqqho ohqjwk vkrzlqj wkdw
wkhuh lv d forvhg uhodwlrqvkls ehwzhhq wkh wzr iru0
pxodwlrqv1
fdofxodwlrqv1 Phdq dqg pd{lpxp huuruv +fdofxodwhg
, duh vkrzq lq Wdeoh 41
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3
e L_i* hit*|t
Zh frpsduhg wkh doskd0srzhu odz PRVIHW
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Sakurai's model fitness with HSPICE (p-MOS and n-MOS) L={0.35um..3um}
Model
3
Model
3
2.5
2.5
Ids(mA) (Model)
Ids(mA) (Traditional model)
Model fitness with HSPICE simulations (p-MOS and n-MOS) L={0.35um..3um}
2
1.5
1
0.5
2
1.5
1
0.5
0
0
0
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0.5
1
1.5
2
Ids(mA) (HSPICE)
2.5
3
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0
83
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1
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2
Ids(mA) (HSPICE)
2.5
3
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Delay time evaluation
500
Tdelay (ps)
400
300
Model
Sakurai et al.
HSPICE tpLH
HSPICE tpHL
200
100
0
50
100
150
200
250
300
Tin (ps)
350
400
450
500
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Delay time evaluation
450
HSPICE tdHL
HSPICE tdLH
Sakurai et al.
Model
400
Tdelay (ps)
350
300
250
200
150
0
0.5
1
1.5
Channel length (um)
2
2.5
3
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Geometry extraction of Qsc from Qsc(CM=0) and tov
B
50
40
E
Q sc 0
Current ( µ A)
30
20
Q sc r
10
D
0
t ov
A
C
-10
-20
0
20
40
60
80
100
t (ps)
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:
450
0.18um Design Rule
0.35um Design Rule
Eq. (24)
400
350
t ov (ps)
300
250
200
150
100
50
0
0
50
100
150
tov max (ps)
200
250
300
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<
Energy vs. line resistance(CL=0.2pF tin=300ps)
0.14
Short-circuit energy/Cycle (pJ)
0.12
0.1
0.08
0.06
0.04
Wp/Wn=5um/10um
Wp/Wn=7.5um/7.5um
Wp/Wn=10um/5um
Model
[5]
0.02
0
0
200
400
600
800
1000
R ( Ω)
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`R *`? duh frqvlghuhg1
Energy vs. input time (CL=1pF)
12.4
12.2
Wp/Wn=10um/10um R=0
Ω
Wp/Wn=10um/10um R=1k
Wp/Wn=6um/14um R=0
Ω
Wp/Wn=6um/14um R=1k
Model
Energy/Cycle (pJ)
12
11.8
11.6
11.4
11.2
11
400
600
800
1000
tin (ps)
1200
1400
1600
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wudqvlwlrq lv qlvkhg1
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dqg Trxw +4, dv=
O
YGG
Trxw +3, @ FO . FP
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K
Trxw +4, @ FP YGG
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kljk wr orz rxwsxw wudqvlwlrq lv=
5
4
K
O
+8,
YGG
FO . FP
. FP
5
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wkh ordg fdsdflwru FO +vhh Ilj1 4,1 Wkh hqhuj| ri
d glvfkdujlqj fdsdflwru lv H @ TY @5/ zkhuh Y lv
wkh yrowdjh vzlqj dqg T wkh fkdujh lqlwldoo| vwruhg
lq wkh fdsdflwru1 Wkh yrowdjh vzlqj dw wkh rxwsxw
qrgh ri wkh exhu lv htxdo wr wkh vxsso| yrowdjh YGG
zkloh wkh fkdujh wudqvihuuhg fdq eh ghulyhg xvlqj
fkdujh frqvhuydwlrq e| frpsxwlqj wkh fkdujh dw wkh
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5
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fdq eh rewdlqhg
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dv=
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O
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YGG
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5
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gw
gw
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D1
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LGV
;
? 3
+5 YYGV
, YGV L 3
@
G3 3 YG3 3 G3
= 3
LG3
+YJV _ YW K ,
3
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,
3
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,
+:,
zlwk
3
LG3 @ LG3
YJV YW K
YGG YW K
q
+;,
Current through the short-circuiting transistor
800
Increasing CM
600
Isc (uA)
400
200
0
-200
t=tov
-400
-600
0
0.05
0.1
Time (ns)
0.15
0.2
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3
lv jlyhq e|=
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3
YG3
@ YG3
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p
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wkh vkruw0flufxlw frpsrqhqw gxh wr wkh vlpxowdqhrxv
frqgxfwlrq ri erwk ghylfhv1
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wkh frxsolqj fdsdflwdqfh1 Li wkh lqsxw yrowdjh lv eh0
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djh, dw w @ wry / wkhq wkhuh zloo eh d vkruw0flufxlw fxu0
uhqw shulrg iurp wklv wlph xqwlo wkh sPRV lv wxuqhg
r1 Rwkhuzlvh wkh rxwsxw yrowdjh lv vwloo eh|rqg
YGG zkhq wkh lqsxw uhdfkhv YGG . YW S dqg wkh
vkruw0flufxlw fxuuhqw lv qrw suhvhqw1
Ilj1 5 vkrzv wkdw ryhuvkrrwlqj glvsodfhv wkh
vkruw0flufxlw fxuuhqw wr wkh uljkw/ pdlqwdlqlqj wkh
fxuuhqw vorshv lqyduldqw1 Dv fdq eh dssuhfldwhg/ wkh
vkruw0flufxlw fkdujh wudqvihuuhg +srvlwlyh fxuuhqw, lv
ixuwkhu uhgxfhg zkloh wkh ryhuvkrrwlqj fkdujh wudqv0
ihuuhg +qhjdwlyh fxuuhqw, lqfuhdvhv1 Wkhuhiruh/ ryhu0
vkrrwlqj hhfwv fdqqrw eh qhjohfwhg zkhq frpsxw0
lqj wkh vkruw0flufxlw frpsrqhqw1
Lq wklv zrun/ ryhuvkrrwlqj hhfwv rq wkh vkruw0
flufxlw fxuuhqw vkdsh duh lqfoxghg wkurxjk wkh wlph
dw zklfk ryhuvkrrwlqj fxuuhqw ydqlvkhv wry 1 Dq hp0
slulfdo uhodwlrqvkls ehwzhhq wkh vkruw0flufxlw fkdujh
wudqvihuuhg +Tuvf , dqg wkh ydoxh ri wklv fkdujh
zkhq wkh frxsolqj fdsdflwru lv qhjohfwhg +T3vf Tuvf +FP @ 3,, lv rewdlqhg wkurxjk wry dv=
w 5
5 wry
W q
Tuvf @ T3vf h
vf
+43,
zkhuh wq lv wkh wlph dw zklfk wkh qPRV wudqvlvwru
vwduwv wr frqgxfw dqg Wvf lv wkh wlph gxulqj zklfk
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d olqhdu wudqvlwlrq lv dvvxphg dw wkh lqsxw ri wkh
w
exhu zlwk lqsxw ulvh wlph wlq +Ylq @ YGG wlq
, zh
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Wvf
WQ
wq @ wlq YYGG
WQ . YWS
@ wlq 4 YYGG
YGG
+44,
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wq , wkhq Tuvf @ T3vf lq ht1 +43,1 Zkhq ryhuvkrrw0
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fkdujh ydqlvkhv Tuvf 31 Dq dqdo|wlfdo h{suhvvlrq
iru T3vf fdq eh rewdlqhg iurp wkh prgho lq ^7` zkhuh
d vlpsoh forvhg0forvhg irup h{suhvvlrq iru VFFW dv0
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lwdqfh iru ydulrxv ydoxhv ri wkh rxwsxw fdsdflwru
+iurp Fplq wr 83Fplq > zkhuh Fplq lv wkh plqlpxp
fdsdflwru doorzhg e| wkh whfkqrorj|, iru d 3=68p
whfkqrorj|1 Dv fdq eh dssuhfldwhg/ wkh prgho gh0
yhorshg lv forvh wr KVSLFH vlpxodwlrqv1
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ulvlqj lqsxw hgjh lv frpsxwhg dv=
u
Hvf
@ Tuvf YGG
F1
+45,
Ryhuvkrrw wlph
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ohp dqg qr0forvhg irup h{suhvvlrq fdq eh irxqg iru
wklv wlph1 Wr dyrlg qxphulfdo surfhgxuhv zh frp0
sxwh wkh wlph dw zklfk wkh ryhuvkrrw fxuuhqw lv pd{0
lpxp wpd{
ry > dqg uhodwh wry wr wklv ydoxh1
Short-circuit charge vs. CM (Wn=3um Wp=6um L=0.35um Tin=0.2ns)
Energy vs. input time
20
1.8
HSPICE
Model proposed
18
W p /W n =6 µ m/6 µ m
W p /W n =4 µ m/8 µ m
W p /W n =4 µ m/2 µ m
W p /W n =2 µ m/4 µ m
[4] (Original)
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219
A Compact Charge-Based Propagation Delay
Model for Submicronic CMOS Buffers
José Luis Rossello and Jaume Segura
Departament de Física, Universitat Illes Balears, 07071 Palma de Mallorca, Spain
Abstract. We provide an accurate analytical expression for the propagation delay and the output transition time of submicron CMOS buffers
that takes into account the short-circuit current, the input-output coupling capacitance, and the carrier velocity saturation effects, of increasing importance in deep-submicron technologies. The model is based on
the nth-power law MOSFET model and computes the propagation delay from the charge delivered to the gate. Comparison with HSPICE
level 50 simulations and other previously published models for a 0.35µm
and a 0.18µm process technologies show significant improvements over
previously-published models.
1
Introduction
Timing analysis is one of the most critical topics in VLSI design. The nonlinear behavior of CMOS gates requires numerical procedures for accurate timing
analysis at expenses of large computation times. Moreover, the impact of design
parameters such as fan in, fan out or transistor sizes on the propagation delay
are difficult to understand and optimize using numerical procedures.
The dynamic behavior of submicron CMOS buffers depends on several nonlinear effects like the velocity saturation of carriers due to the high electric fields
in submicron technologies, the short circuit current appearing when both pMOS
and nMOS transistors are conducting simultaneously [1], and the additional effect of the input-output coupling capacitance [2].
Several methods have been proposed to derive the delay of CMOS buffers [2][7] as a first step to describe more complex gates [8,9]. Cocchini et al. [3] obtained
a piece-wise expression for the propagation delay based on the BSIM MOSFET
model [10]. The model included overshooting effects (due to the input-to-output
coupling capacitance) while the short-circuit current was neglected. In [2] and
[4] K.O Jeppson and L. Bisdounis presented a model for the output response
of CMOS buffers using a quadratic current-voltage dependence for MOSFET
devices, which is not longer valid for submicron technologies. Daga et. al. [5]
obtained a simple empirical expression for the propagation delay taking into account both overshooting and short-circuit currents using six fitting parameters.
The relative error of this model was 19% for a 0.6µm technology as reported in
[5]. Hirata et al. [6] derived a delay model based on the nth-power law MOSFET model [11] considering both short-circuit and overshooting currents and
B. Hochet et al. (Eds.): PATMOS 2002, LNCS 2451, pp. 219–228, 2002.
c Springer-Verlag Berlin Heidelberg 2002
220
J.L. Rossello and J. Segura
using numerical procedures . The model provides an accurate description for the
propagation delay but the numerical procedures used increases the computation
time considerably. Bisdounis et al. [7] developed a piece-wise solution with seven
operation regions for the transient response of a CMOS inverter based on the
α-power law MOSFET model [12] including both overshooting and short-circuit
currents. In [8] T. Sakurai et. al. obtained a simple expression for the propagation
delay of CMOS gates based on their nth-power law MOSFET model neglecting
both short-circuit and overshooting currents.
In this work we propose a compact analytical model to accurately compute
the propagation delay and the output transition time of a CMOS buffer accounting for the main effects of submicron technologies as the input-output coupling
capacitance, carriers velocity saturation effects and short-circuit currents. The
model is based on an accurate physically-based nth-power law MOSFET model
[13] and on a power dissipation model for CMOS inverters [14]. Comparisons with
HSPICE level 50 simulations and previously published models for a 0.35µm and
a 0.18µm process technologies are reported showing significant improvements in
terms of accuracy.
Fig. 1. In this figure we show the CMOS current and voltage switching characteristics.
This paper is organized as follows: In Section 2 the CMOS buffer switching characteristics are analyzed with detail and the MOSFET model used is
presented. The delay and the output transition time models are developed in
Section 3 and compared to HSPICE simulations and other previously published
models for a 0.35µm and a 0.18µm process technology in section 4. Finally in
section 5 we conclude the work.
A Compact Charge-Based Propagation Delay Model
2
221
Analysis of the CMOS Buffer Switching Characteristics
The dynamic behavior of a CMOS buffer is described by the next equation:
(CL + CM )
dVin
dVout
= Ip − In + CM
dt
dt
(1)
where CL is the output capacitance, Vout and Vin are the output and input
voltage respectively, while Ip and In are the current that crosses the pMOS and
the nMOS transistor respectively. CM is the input to output coupling capacitance
L
which is voltage dependent. The static value of CM when the input is low (CM
)
is computed considering the side-wall capacitances of both transistor drains and
the gate to drain capacitance of the pMOS transistor that operates in the linear
region as:
Wpef f Lpef f
L
CM
(2)
= Cox
+ LDp Wpef f + LDn Wnef f
2
with Wpef f and Wnef f being the effective channel width of pMOS and nMOS
respectively, Lpef f is the effective channel length of pMOS, while LDn and
LDp are the gate-drain underdiffusion for the nMOS and pMOS transistors reH
spectively. For a static input high the capacitance CM
is obtained similarly.
In this work
a
mean
value
for
the
coupling
capacitance
during the transition
L
H
) will be used.
(CM = 0.5 CM
+ CM
Fig. 1 illustrates the input and output voltage evolution of the buffer along
with the current through the nMOS and pMOS transistors for a low to high
input transition. The current through the pMOS transistor (Ip in Fig. 1) has two
components clearly distinguished by the sign of the current. The negative pMOS
current is due to a partial discharge of the output capacitance from the output
node toward the supply rail and appears when the input-output capacitance
drives the output voltage beyond the supply value (VDD ) at the beginning of
the transition [2] (this effect is known as overshooting). When the nMOS device
starts to conduct, it pulls the output voltage down. Once the output voltage
goes below VDD , the pMOS current is positive corresponding to the short-circuit
component due to the simultaneous conduction of both devices.
The propagation delay (defined as tpHL for a high to low output transition)
is typically defined as the time interval from the 50% VDD input voltage to the
50% VDD output voltage. The dependence of the propagation delay with design
parameters is non-linear and difficult to model given that eq.(1) can not be solved
in a closed form even using the simple Shockley MOSFET model [15]. Moreover
carrier saturation effects become important with technology scaling and more
complex MOSFET models accounting for such effects must be considered.
The nth-power law MOSFET model [11] is a widely used short-channel drain
current model, and will be used in this work to derive the propagation delay and
the output transition time of CMOS inverters. The drain current is expressed
as:
222
J.L. Rossello and J. Segura
ID

0
= (2 −
 ID0
VDS VDS ) V ID0
VD0
D0
with
ID0
= ID0
(VGS VT H )
)
(VDS < VD0
(VDS VD0 )
VGS − VT H
VDD − VT H
(3)
n
(4)
where VGS ,VDD , and VD0
are the gate, supply, and saturation voltage respectively and ID0 is the drain current at VGS = VDS = VDD . The parameter n is
the velocity saturation index that ranges between 2 (long-channel devices) and
1 (short-channel) [11]. The saturation voltage VD0
is given by:
m
VGS − VT H
= VD0
(5)
VD0
VDD − VT H
The parameter VD0 is the saturation voltage at VGS = VDD , while m and
VT H are empirical parameters [11]. These equations are mathematically simpler
than physically-based MOSFET models such as BSIM3v3 or MM9 with the disadvantage that, in the original model developed by Sakurai and Newton, the
relationship between the empirical and the process parameters supplied by manufacturers is not provided. Therefore the variation of nth-power law model predictions with key parameters like the supply voltage are not taken into account
in the original formulation performed by Sakurai and Newton, where each parameter must be recomputed if the supply voltage or some device dimension are
changed. In this work we use the physical formulation proposed in [13] and used
in [14]. This physical formulation provides an analytical relationship between the
nth-power law parameters and the more accurate MM9 model parameters (that
take into account the parameter variations with the supply voltage, MOSFET
dimensions and temperature).
3
Delay Model
We compute the propagation delay when the input voltage switches. The shortcircuit and overshooting currents are first neglected and incorporated later. Assuming a linear variation of the input voltage with rise time tin then Vin (t)
is:
t − tn
Vin (t) = VT N + (VDD − VT N )
(6)
tin − tn
where VT N is the nMOS threshold voltage, tn is the time when the nMOS chain
starts to conduct (tn = VT N tin /VDD ) and tin is the input rise time. At the
beginning of the transition the nMOS is off and Vout = VDD . At t = tn , the
nMOS starts to conduct and the output voltage is obtained solving:
CL
dVout
= −In
dt
(7)
where CL is the total output capacitance of the gate, and In is the current
through the nMOS transistor. An analytical solution to (7) is possible if the
A Compact Charge-Based Propagation Delay Model
223
nMOS transistor is assumed to be in the saturation region (valid while Vout >
VD0
):
n
n+1
ID0n
t − tn
tin − tn
Vout = VDD −
(8)
CL
tin − tn
n+1
Equation (8) is used to obtain the propagation delay from the input at
0.5VDD to the output at 0.5VDD .
tpHL1
Qf (n + 1)
= tn +
ID0n
1
1+n
n
(tin − tn ) n+1 −
tin
2
(9)
where Qf = CL VDD /2 is the charge transferred by the nMOS transistor when the
output reaches VDD /2 while parameters ID0n and n are the maximum saturation
current and the velocity saturation index of nMOS respectively. Equation (9) is
valid for slow inputs (defined when tpHL ≤ tin /2). If Qf0 is defined as the total
charge transferred through the nMOS transistor when tpHL = tin /2 then eq.
(9) is valid in the interval Qf < Qf0 . The parameter Qf0 is obtained equating
tpHL1 = tin /2 and solving Qf0
Qf0 =
ID0n
(tin − tn )
(n + 1)
(10)
If the input reaches the supply voltage before the output is at VDD /2 then
Qf > Qf0 and eq. (9) is no longer valid. The propagation delay when tpHL ≥
tin /2 (fast input range) can be obtained by solving (7) for In = ID0n leading to:
tpHL2 =
Qf − Qf0
tin
+
2
ID0n
(11)
Equation (11) is valid when Qf > Qf0 (fast input range). For simplicity,
the proposed model for the propagation delay (eqs. (9) and (11)) does not take
into account the fact that the nMOS transistor is in the linear region when
Vout > VD0
. For the evaluation of the output fall time (tf ) we first compute
n
the output voltage slope at VDD /2 from (8)
dVout =
dt VDD /2 n
n+1
I
V
Qf (n+1)
DD
 − D0n
(12)
(Qf < Qf0 )
2Qf
(tin −tn )ID0n
 − ID0n VDD
(Q > Q )
f
2Qf
f0
For the evaluation of the output fall time we use:
tf =
VDD
dVout dt
VDD /2
(13)
The value of the output fall/rise time is important since this parameter is
used as the input fall/rise time of the gates driven by the buffer.
224
3.1
J.L. Rossello and J. Segura
Including Short-Circuit Currents
The model proposed cannot be used for static CMOS gates since short-circuit
currents are not considered. In this work we include the short-circuit current contribution to the delay as an additional charge that must be transferred through
the pull-down (pull-up) network during an output falling (rising) transition. This
additional charge is computed from the short-circuit power model presented in
[14].
Therefore, for an output falling transition, the charge transferred through the
f
f
nMOS transistor is computed as Qf = CL VDD /2+qsc
, where qsc
is defined as the
short-circuit charge transferred during the falling output transition until Vout =
f
is complex given that this parameter
VDD /2. The analytical derivation of qsc
depends on the relative switching speed between the input and the output. For
f
an input transition faster than the output, qsc
can be modeled as the total shortf
circuit charge transferred (defined as Qsc ) given that when Vout = VDD /2 the
input is high and the short-circuit current ceased. For an input transition slower
f
f
than the output then qsc
< Qfsc . For both cases we assume that qsc
= κQfsc ,
where κ is an empirical parameter that must be optimized for each technology.
For the 0.35µm and the 0.18µm technologies considered we obtained κ = 0.45
and κ = 0.73 respectively.
3.2
Including Overshooting Effects
Similarly to the short-circuit currents case, overshooting currents effects are included into the delay model as an additional charge to be transferred through
the nMOS transistor. For fast inputs, the charge injected through the coupling
capacitor (CM ) when Vout = VDD /2 is Qov = CM VDD . For simplicity we assume the same value for Qov in the slow-input case. Therefore, the total charge
that must be transferred through the nMOS transistor during a falling output
transition is:
Qf = 0.5 [(CL + 2CM ) VDD ] + κQfsc
(14)
Equation (14) must be used in eqs. (9), (11) and (13).
4
Results
We plotted model results vs. HSPICE level 50 simulations for a 0.35µm and
a 0.18µm technologies. Results show the propagation delay for different values
of the input transition time tin , the configuration ratio Wp /Wn and the supply
voltage VDD .
In Fig. 2 we plot the propagation delay tpHL vs. the input time tin for different values of the Wn /Wp ratio for a 0.35µm technology. HSPICE simulations
(dots) are compared to the model proposed and to a previous model [3]. Shortcircuit currents are not taken into account in [3] leading to an underestimation
of the propagation delay. The model in [3] provides a piece-wise solution of the
propagation delay: depending on the input transition (fast or slow input transitions) it uses an approximated or an exact expression for the propagation delay.
A Compact Charge-Based Propagation Delay Model
225
The approximated propagation delay is used when the nMOS transistor changes
from the saturation to the linear region and the input is rising (eq.(11) in [3]),
otherwise an exact expression for the output response is used. This pice-wise
solution leads to a discontinuity in the propagation delay when changing from
one region to the other (see Fig. 2).
Fig. 2. Propagation delay vs. input rise time for different values of the configuration
ratio. Short-circuit currents are not taken into account in [3]
Fig. 3 plots the propagation delay vs. the input rise time for a 0.18µm technology. When the Wp /Wn ratio is small the propagation delay decreases when
increasing the input rise time. The model proposed in this work (solid lines)
and the previously-published in [6,7] provide a good approximation to HSPICE
simulations (dots).
Fig. 4 is a plot of HSPICE simulations (dots) and model predictions of the
propagation delay vs. the supply voltage. The model proposed in this work provides a better fitting than the models in [6,7]. The model in [7] uses Taylor
series expansions for the output response. For large supply voltage values the
input transition is slow with respect the output response and the output voltage crosses VDD /2 when both nMOS and pMOS transistors are in saturation,
(called region 3 in [7]) and the output response used to compute the propagation delay is described through a Taylor series expansion. For the voltage range
(0.6V < VDD < 1V ) the propagation delay is obtained computing the output
voltage when the nMOS is saturated, the pMOS off and Vin < VDD (region 4 in
[7]) and a quadratic Taylor series expansion of the output voltage around time
tp|
tn
t1−p = tin 1 − VVDD
is used to compute the propagation delay. As VDD
− |V
VDD
is further reduced, the accuracy of the approximated output voltage decreases
because the time point t1−p used in the Taylor expansion is reduced. For low
226
J.L. Rossello and J. Segura
Fig. 3. Propagation delay vs. input rise time for different values of the configuration
ratio for a 0.18µm technology
Fig. 4. Propagation delay vs. supply voltage for a 0.18µm technology.
values of the supply voltage, VDD < 0.6V , the propagation delay is computed
for the nMOS saturated and Vin = VDD (region 5A ) and an exact solution for
the output response is used. Therefore, there are two discontinuities: between
regions 4-5A (VDD = 0.6V ) and between regions 3 and 4 (VDD = 1V ).
In Fig. 5 we plot HSPICE simulation of the output transition time tf for
different values of the input rise time tin and the configuration ratio Wp /Wn .
A Compact Charge-Based Propagation Delay Model
227
A maximum relative error of 15% is obtained between model predictions and
HSPICE simulations. In general a good agreement is obtained with the proposed
model.
Fig. 5. Propagation delay vs. supply voltage for a 0.18µm technology.
5
Conclusions
An accurate analytical expression to compute the propagation delay and the
output transition time of CMOS buffers has been presented. The main effects
present in current submicron CMOS technologies like the input-output coupling
capacitance, carriers velocity saturation effects and short-circuit currents are
taken into account in the analysis. The model is compared to HSPICE simulations (level 50) and other previously published works for a 0.18µm and a 0.35µm
process technology reporting a high degree of accuracy. The model represents an
improvement with respect to previously published works.
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J.L. Rossello and J. Segura
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Model
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0.24
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1.6
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Model
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Ph.D. Thesis entitled “Power and Timing Modeling of Sub-micron CMOS Gates”
developed by Jose L. Rosselló, [email protected]. Directed by: Jaume Segura.
Power dissipation emerged as a major concern in digital IC design during the last decade becoming a
design parameter as important as performance and area. Many low power design techniques at different
levels (technological, design and architectural) were developed, all of them requiring accurate power
estimation tools to achieve high-performance low-power digital systems.
Electrical level simulation methods are impractical to evaluate full chip performance for huge designs due
to the enormous computation time required. The complex non-linear dependencies of logic gates delay with
process and design parameters in traditional technologies are aggravated in deep-submicron ICs due to new
physical effects that come into the picture. The traditional description of logic gates delay based on
simplified linear models used by logic simulators (that are much more faster than electrical simulators) are
not accurate enough to describe the behavior of present technology ICs.
In the Ph.D. thesis we develop new power and timing analytical models for sub-micron and deep
sub–micron CMOS gates. These analytical models are of high interest for low-power digital design since
they provide an explicit relationship between power/delay and process/design parameters (identifying the
parameters with greatest influence on the circuit performance and power disipation). These analytical
models can be also incorporated in simulation tools to obtain accurate (very close to SPICE simulations)
power/delay estimations for huge circuits.
The Thesis is organized in three parts devoted to: MOSFET devices, CMOS buffers and complex CMOS
gates respectively. In the first part, a simple physically based MOSFET model [1] is developed. This model
is a variation of the widely-used nth-power law MOSFET model developed by Sakurai and Newton that
was oriented to circuit analysis. The proposed formulation allows a direct and simple relationship between
physical and nth-power law parameters.
In the second part of the thesis, power and delay models [2,3] for sub-micron CMOS buffers are developed
based on the physical nth-power law MOSFET model and on the charge transfer mechanisms involved in
gate transitions. These models take into account short-channel effects of MOSFETs and can incorporate the
effect of the interconnect line resistance [4]. Finally, in the third part we develop an nth-power law model
for series-connected MOSFETs. This model is used to obtain a delay model of complex CMOS gates [5]
and for power-delay optimization of dynamic gates [6].
The accuracy of the power/delay models developed in this thesis are within 5% of SPICE simulations for a
wide range of circuit configurations and switching conditions.
[1] J.L.Rosselló and J.Segura, “A physical modeling of the alpha-power law MOSFET model”, In Proc. of
the XV Design of Circuits and Integrated systems Conference (DCIS’00) . Montpellier, Nov.2000, pp. 6570
[2] J.L. Rosselló and J. Segura, "Charge-based analytical model for the evaluation of power consumption in
sub-micron CMOS buffers" IEEE Transactions on Computer Aided Design of Integrated Circuits and
Systems, vol. 21, no. 4, pp.433-448, April 2002
[3] J.L Rosselló and J.Segura, “A compact charge-based propagation delay model for submicronic CMOS
buffers”, XII International Workshop on Power and Timing Modeling (PATMOS 2002), Sevilla, Spain,
September 2002, pp. 219-228
[4] J.L Rosselló and J.Segura, “A simple power consumption model of CMOS buffers driving RC
interconnect lines”, In Proc. of the XI International Workshop on Power and Timing Modeling (PATMOS
2001), Yverdon-Les-Bains, Switzerland September 2001, paper no. 4.2
[5] J.L. Rossello and J. Segura, "Simple and accurate propagation delay model for submicron CMOS gates
based on charge analysis" Electronics Letters, Vol. 38, no. 15 , pp. 772-774, Jul 2002
[6] J.L Rosselló and J.Segura, “Power-delay modeling of Dynamic CMOS gates for circuit optimization”,
In Proc. the International Conference on Computer Aided Design (ICCAD’01) . San Jose, CA, Nov.2001,
pp. 494-499
Power and Timing Modeling of Submicron CMOS Gates
José L. Rosselló, University of the Balearic Islands, Spain
Ph.D. Director: Jaume Segura
Ph.D. dissertation defended on February 2002
Development of power and timing models for sub-micron CMOS gates
ACCURATE POWER MODELS FOR SUB-MICRON CMOS GATES
•Physical α-power law model for
series-connected transistors
•The α-power law model is suitable for
circuit analysis
•The empirical nature of parameters
involved implies a lack in physical
meaning
•A relationship between physical and
α-power law parameters is provided
• Easier extraction of
power and delay models
for sub-micron CMOS
gates
•A physical meaning for
these power and delay
models is provided
•The model is extended
to stacked transistors
Charge-based power models for
CMOS gates taking into account:
• Short-channel effects
• Short-circuit power
• Overshooting effects
• Resistance of the interconnect
line
•Temperature of operation
R
Vin
Vout
C2
C1
ACCURATE DELAY MODELS FOR SUB-MICRON CMOS GATES
APPLICATIONS
POWER-DELAY OPTIMIZATION
Charge-based analytical models
for the propagation delay and the
output transition time of CMOS
gates taking into account:
• Short-channel effects
• Short-circuit power
• Overshooting effects
• Temperature of operation
CROSSTALK ESTIMATION
SKEW
ts
Vin,a
Vout,a
AGGRESSOR LINE
CL,a
CC
Vin,v
Vout,v
VICTIM LINE
CL,v
Delay (tpHL)
Current and future work
•Estimation of the self-heating
effect in MOSFET devices and
interconnections
(Temperature of operation as
a function of power dissipated)
•Estimation of thermal
interactions inside the IC.
•Development of a compact IC
electro-thermal simulation
(Power, delay, crosstalk and
temperature estimation inside
the IC)
•Development of optimization
techniques (Power, delay,
crosstalk and temperature
optimization inside the IC)
BASIC BIBLIOGRAPHY
POWER
J.L. Rosselló and Jaume Segura, "Charge-based analytical model for the
evaluation of power consumption in sub-micron CMOS buffers" IEEE
Transactions on Computer Aided Design of Integrated Circuits and
Systems , vol. 21, no. 4, pp.433-448, April 2002
•Development of CAD tools
using all the analytical
models developed.
•Technology transfer to the
IC industry
J.L Rosselló and J.Segura, “A simple power consumption model of
CMOS buffers driving RC interconnect lines”, In Proc. of the XI
International Workshop on Power and Timing Modeling (PATMOS
2001), Yverdon-Les-Bains, Switzerland September, 26-28,2001, paper
no. 4.2
DELAY
J.L. Rossello and J. Segura, "Simple and accurate propagation delay
model for submicron CMOS gates based on charge analysis" Electronics
Letters, Vol. 38, no. 15 , pp. 772-774, Jul 2002
J.L Rosselló and J.Segura, “A compact charge-based propagation delay
model for submicronic CMOS buffers”, XII International Workshop on
Power and Timing Modeling (PATMOS 2002), pp. 219-228 Sevilla,
Spain September 11-13, 2002
APPLICATIONS
J.L Rosselló and J.Segura, “Power-delay modeling of Dynamic CMOS
gates for circuit optimization”, In Proc. the International Conference on
Computer Aided Design (ICCAD’01) . San Jose, CA, Nov.2001, pp. 494499.
J.L Rosselló and J.Segura, “A compact charge-based crosstalk induced
delay model for submicronic CMOS gates ”, Accepted for publication in
the XIII International Workshop on Power and Timing Modeling
(PATMOS 2003), Torino, Italy, September 10-13, 2003
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800
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600
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400
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200
0
0
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C C /C L
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0.8
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tpHL,sd
tpHL,su
tpHL,sd
Propagation delay t
pHL
(ns)
0.7
Model
Wn=1um
Wn=1um
Wn=3um
Wn=3um
0.6
0.5
0.4
0.3
0.2
0.1
0
-1
-0.8
-0.6
-0.4
-0.2
0
time skew (ns)
0.2
0.4
0.6
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80
HSPICE
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V DD =0.9V
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30
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50
100
150
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