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energies Article Control Strategy of Single-Phase Three Level Neutral Point Clamped Cascaded Rectifier Xiaoqiong He, Xiaolan Lin, Xu Peng *, Pengcheng Han, Zeliang Shu and Shibin Gao School of Electrical Engineering, Southwest Jiaotong University, Chengdu 610031, China; [email protected] (X.H.); [email protected] (X.L.); [email protected] (P.H.); [email protected] (Z.S.); [email protected] (S.G.) * Correspondence: [email protected]; Tel.: +86-28-8763-4940 Academic Editor: Jose Fernando Alves da Silva Received: 20 March 2017; Accepted: 22 April 2017; Published: 28 April 2017 Abstract: Single-phase 3-level neutral point clamped cascaded rectifier (3LNPC-CR) has been successfully made its way into traction drive system as a high-voltage traction converter. In this passage, the control issue of the 3LNPC-CR is considered. A transient current control strategy, combined with proportional integral (PI) controllers, is adopted to achieve unity power factor, satisfactory sinusoidal grid current, regulated overall dc voltage, and even efficient voltage balance between each module. Besides, with regard to the instinct voltage fluctuation problem among dc-link capacitors in one 3-level neutral point clamped (3LNPC) rectifier module, a phase shift carrier space vector pulse width modulation (PSC-SVPWM) worked along with a reasonable redundancy selection scheme is addressed. In addition, two auxiliary balancing circuits for a single-phase 3LNPC rectifier is proposed. The voltage balancing capacity of these internal-module balancing schemes are analyzed and compared. Finally, the control performance of these proposed strategies are verified by simulations and experiments. Keywords: 3-level neutral point clamped cascaded rectifier (3LNPC-CR); phase shift carrier space vector pulse width modulation (PSC-SVPWM); capacitor voltage balancing; mutual-module voltage balancing 1. Introduction Multilevel converters have successfully made their way into the high-power application area and are considered to be a proven technology [1,2]. By increasing the number of modules connected in a series, it is possible to generate more voltage levels to synthesize the input terminal voltage, which makes the voltage and current harmonics significantly decrease [3,4]. The cascaded multilevel converter has received increased attention due to its advantages over other topologies. Firstly, the series rectifiers are able to share the overall input voltage, featuring power semiconductors with a lower voltage rating [5]. Thus, with more modules connected in series, the voltage that applied at the converter terminals could be higher. Secondly, a proper choice of the electronic components and the number of cascaded modules allows removing of the heavy, bulky and expensive step-down transformer [6–9]. Last but not least, cascaded multilevel converters feature high modularity degree that makes it possible to operate the converter even under faulty conditions by immediately replacing the faulty module [10]. In this way, the reliability of this system is increased. A Hani Packed U-cell (HPUC) is introduced to generate a multi-level voltage waveform at the input in [11]. Moreover, a single-phase Three level neutral point clamped cascaded rectifier (3LNPC-CR) is hired due to its ability to deal with the high voltage in traction power system [12]. Energies 2017, 10, 592; doi:10.3390/en10050592 www.mdpi.com/journal/energies Energies 2017, 10, 592 2 of 16 In order to properly operate a cascaded converter with n modules connected in series, the control of the grid current and the respective dc-link voltages are necessary [13]. In fact, each module must interact with the others to obtain a regulated grid current, notwithstanding all of the modules transfer power independently. In addition, the dc-link loads of each module may be different. However, the voltage on each dc-link load has to be equalized and stabilized even if the loads are unequal. In order to equalize the output voltages of the dc-terminals, the redundancy-based voltage balancing scenarios are presented [14]. In [15], a PI-based balancing control strategy is achieved. Besides, an improved PI-based balancing strategy is adopted as the multi-module voltage balancing strategy [16]. As the number of separate modules increases, the complexity arises for the necessity of the voltage regulation across these dc-links. In comparison with the traditional H-bridge rectifier, the 3LNPC rectifier generates more voltage levels [17]. In this paper, 3LNPC rectifiers are connected in series to obtain a staircase waveform, which allows for the number of cascaded modules to be decreased [18]. Besides, the demerits of 3LNPC converters cannot be neglected. The neutral-point voltage fluctuation is an urgent problem requiring solution. Inductor-based auxiliary circuit and capacitor-based auxiliary circuit [19,20] are able to extend the stable area and avoid neutral-point voltage fluctuation. However, both of them will cause additional hardware cost. Software based balancing strategy is a more cost-effective way that also manages to balance the dc-link capacitor voltages without installing any additional hardware. An algorithm adjusts the charging/discharging status of dc-link capacitors by selecting redundant [21]. Another algorithm includes regulating on-times of the redundant vectors is presented in [22]. These software-based strategies demonstrate efficient voltage balancing ability and have been applied to single-phase 3LNPC converter. The main analysis has been focused on the control issue of the 3LNPC-CR. Normally, these control strategies are to fulfill a quadruple task. • • • • To obtain sinusoidal grid current; To achieve unity power factor; To regulate and equalize voltages across the output terminals; To balance the dc-link capacitor voltages in each module. Each of these tasks corresponds with one of the common problems in the 3LNPC-CR. The first task is to avoid problems arouse by distorted currents and erroneous failure detection. Completion of the second task allows much lower reactive power requirements. The third task aims to enhance the stability of this system. Besides, the last ensures normal operation of all the 3LNPC rectifiers [23,24]. In this paper, an overall control strategy combined with a PI-based multi-module balancing scheme is proposed to control one grid current plus n dc terminal voltages [25]. The reference modulation signal generated by the overall control strategy is added by a factor that depends on the dc-link voltages in each module. The multi-module voltage balance boundaries are analyzed and the results are verified by experiment. With regard to neutral point voltage fluctuation problem in each module, a redundancy-based strategy used along with phase shift carrier space vector pulse width modulation (PSC-SVPWM) and two hardware-based balancing auxiliary circuits, including inductor-based auxiliary circuit and capacitor-based auxiliary circuit, are adopted to balance the voltages across the dc capacitors in each module. The feasibility and effectiveness of the inductor-based auxiliary circuit is validated by simulation and experiment. This paper is organized as follows. First, the 3LNPC cascaded topology and its working principle is presented in Section 2. Then, the modulation scheme is explained in Section 3. The control strategies are introduced in detail in the fourth section. The last section shows the simulation and experimental results that validate the proper operation of the converter. 2. Topology A basic structure of a single phase 3LNPC is illustrated in Figure 1. All the rectifiers with their respective LC filters are connected in series, sharing the common AC voltage source us and the input Energies 2017, 10, 592 3 of 16 inductance Ls . The internal-module balancing auxiliary circuit is in parallel connection with the dc-link capacitors within Energies 2017, 10, 592 each module. 3 of 15 Sa2 Sb2 C1 O Sa3 Sb3 Sa4 Sb4 C2 Ls Uab DC-DC Module 1 + Uab2 - Us Module 2 Vo2 DC-DC Module n Von DC-DC . . . - Vc2 Vo1 Load + Uab1 - + VC1 Is LC Filter Sb1 Voltage Balancing Auxiliary Circuit Sa1 + Uabn - Figure Figure1.1.Circuit Circuitconfiguration configurationofofSingle Singlephase phase3LNPC-CR. 3LNPC-CR. A single-phase 3LNPC rectifier is composed of two bridge legs Sa and Sb. Each of the bridge leg, A single-phase 3LNPC rectifier is composed of two bridge legs Sa and Sb . Each of the bridge made up of IGBTs with antiparallel diodes and clamped diodes, generates three switching states: leg, made up of IGBTs with antiparallel diodes and clamped diodes, generates three switching states: positive (p), negative (n), or neutral (o). The switching states of bridge leg Sa and Sb are determined positive (p), negative (n), or neutral (o). The switching states of bridge leg Sa and Sb are determined by by the following relation: the following relation: p, S i 1 and S i 2 are on ; Si 3 and S i 4 are off areon on; ;S Si3 and are off S i p, i4 off o,Si1S i and andSSi2 are and Si 4 S are (i a or b ) 2 i3 i1 Si = (i = a or b) o, Si2 and Si3 are on ; Si1 and Si4 are off and Si 4 are on ; S i 1 and S i 2 are off n, n,S S iand 3 Si4 are on ; Si1 and Si2 are off i3 (1) (1) Therefore, the number of total switching states in a single rectifier, contributed by 2 bridge legs, Therefore, the3.number of total switching states singlephase rectifier, contributed bridge legs, is 9, the square of All available voltage vectors forina asingle 3LNPC rectifierby are2 covered in is 9, the square of 3. All available voltage vectors for a single phase 3LNPC rectifier are covered in Table 1. Suppose the voltages on capacitor C1 and C2 are the same and equal to Vo. As shown in Figure 2, Tablevectors 1. Suppose voltages on capacitor C1 and C2 voltage are the usame and equal to V o . As shown in o/2, 0, −Vo/2, −Vo) represent the input ab with 5 voltage levels. these (Vo, Vthe Figure 2, these vectors (V o , V o /2, 0, −V o /2, −V o ) represent the input voltage uab with 5 voltage levels. Table 1. Switching states when Is > 0. Table 1. Switching states when Is > 0. Vectors Sa VectorsV1 Sa p V 1 V2 p p V 2 V3 p o V 3 V4 o p V4 p V5 o V5 o V 6 V6 n n V 7 V7 o o V 8 V8 n n V9 V9 n n Sb Sbp po on nn n o o oo pp pp n n uab C1 C2 Categories 0uab no effectC1 no effect C2 ZCategories VC10 Charge no effect SP no effect no effect Z V C1 Charge charge no effect SP SP VC2 no effect no effectchargecharge LP SP VC1 +VVC2C2 charge V C1 + V C2 charge charge LP 0 no effect no effect Z 0 no effect no effect Z −V−C2VC2 no effect discharge no effect discharge SN SN −V−C1VC1 discharge no effect discharge no effect SN SN −C1 V C1 −C2V C2discharge discharge discharge LN LN −V −V discharge no effect no effect Z 0 0 no effect no effect Z Energies 2017, 10, 592 Energies 2017, 10, 592 4 of 16 4 of 15 V Vo Vo 2 0 - V2o ωT 2 ωT t - Vo Figure 3LNPC rectifier. rectifier. Figure2.2.Voltage Voltagevectors vectorsfor foraasingle single phase 3LNPC Taking into accountthe theintrinsic intrinsicneutral neutral point point voltage voltage fluctuation fluctuation problem, Taking into account problem,the thecharging chargingoror discharging status dc-linkcapacitors capacitorswhile while the the grid grid current current iis is in the positive direction is also discharging status ofof dc-link s is in the positive direction is also covered in Table 1. The dc-link capacitor voltages V C1 and VC2 are assumed to be the same in normal covered in Table 1. The dc-link capacitor voltages V C1 and V C2 are assumed to be the same in normal conditions. Thus, as it is described in Table 1, these voltage vectors can be divided into 5 categories conditions. Thus, as it is described in Table 1, these voltage vectors can be divided into 5 categories according to their effects on the terminal voltage uab: according to their effects on the terminal voltage uab : Zero (Z) vector: V1, V5 and V9. For these vectors, the dc-link capacitors are neither charged Zero (Z) vector: V 1 , V 5 and V 9 . For these vectors, the dc-link capacitors are neither charged nor discharged. nor discharged. Small positive (SP) vector: V2 and V3. Considering that VC1 equals to VC2 when the internalSmall positive (SP) vector: V and V 3 . Considering that V C1 equals to V C2 when the internalmodule voltage balancing scheme2 is accomplished, these switching states generate the same terminal module voltage scheme accomplished, thesestatus switching generate the are same terminal voltage (Vo/2).balancing Even though, the is charging/discharging of thestates dc-link capacitors different. voltage Even though, the charging/discharging the dc-link capacitors are different. o /2). For V(V 2, the grid current would charge C1 but has no effectstatus on C2,ofwhile for V3, the grid current would Forcharge V 2, theCgrid current would charge C but has no effect on C , while for V , the grid current would 1 2 3 2 but has no effect on C1. charge CLarge but has no effect on C . 2 positive (LP) vector:1 V4. The switching state of this vector is unique. The dc-link capacitors Large positive (LP) vector: V 4by . The state of switches this vector The capacitors are connected in series, charged theswitching grid current is via Sa1is , Sunique. a2, Sb3 and Sb4dc-link . are connected in series,(SN) charged by V the gridVcurrent is via switches , S , S and S . Small negative vector: 6 and 7. Considering that VC1 Sequals to V C2 when the internala1 a2 b3 b4 Small voltage negative (SN) vector: Vaccomplished, that V C1generate equals the to same V C2 terminal when the module balancing scheme is these switching states 6 and V 7 . Considering voltage (−Vo/2).voltage Even ifbalancing these twoscheme switching states are redundant while the neutral point voltage is internal-module is accomplished, these switching states generate the same balanced, the charging/discharging status areswitching opposite. V 6 would C2 but hasthe no neutral effect onpoint C1, terminal voltage (−V o /2). Even if these two states aredischarge redundant while whileisVbalanced, 7 would discharge C1 but has no effectstatus on C2. are opposite. V 6 would discharge C2 but has no voltage the charging/discharging 8 . Opposite to no LPeffect vector, Sa3, Sa4, Sb1 and Sb2 are on to Large negative (LN) vector: V effect on C1 , while V 7 would discharge C1 but has onSwitches C2 . provide discharge loopvector: for dc-link capacitors to C1 LP andvector, C2. Large anegative (LN) V 8 . Opposite Switches Sa3 , Sa4 , Sb1 and Sb2 are on to According to the switching states identified before, the input voltage of each module uabi provide a discharge loop for dc-link capacitors C1 and C2 . (i According = 1, 2,…, n) can be described as follows. to the switching states identified before, the input voltage of each module uabi (i = 1, 2, . . . , n) can be described as follows.u ab i ( S a S b ) Voi (2) Considering n cells with the same dc-link voltage, 5 voltage levels will be generated by each uabi = (Sa − Sb ) · Voi (2) module and the repeated (n − 1) zero voltages should be removed. That is to say, the rectifier can ab with 5n − (n − 1) levels. synthesize an input voltage Considering n cells withuthe same dc-link voltage, 5 voltage levels will be generated by each n module and the repeated (n − 1) zero voltages should be removed. That is to say, the rectifier can U ab uabi (3) synthesize an input voltage uab with 5n − (n − 1) levels. i 1 n Thus, according to the Kirchhoff laws, the grid-side dynamic behavior of the system can be Uab = ∑ uabi (3) described as: i =1 U s - j Ls is U ab (4) Thus, according to the Kirchhoff laws, the grid-side dynamic behavior of the system can be described as: 3. Modulation Scheme Us − jωLs is = Uab (4) Among various modulation techniques for a 3LNPC rectifier, SVPWM is an attractive candidate 3. Modulation Schememerits. It has a more explicit physical meaning, and is more suitable for digital due to the following signal processor The modulation wave of module is an represented as uabi* Among various implementation. modulation techniques for a 3LNPC rectifier, SVPWMi is attractive candidate due to the following merits. It has a more explicit physical meaning, and is more suitable for Energies 2017, 10, 592 5 of 16 Energies 2017, 10, 592 5 of 15 digital signal processor implementation. The modulation wave of module i is represented as uabi * (i (i == 1, 1, 2, 2, …, . . . ,n). n).The Themodulation modulationwaveform waveformfor foreach eachmodule moduleisisdivided dividedinto into four four sectors sectors according according to to V ref , the instantaneous value of u abi *. That is: V ref , the instantaneous value of uabi *. That is: Sector 1; 1; Sector 1: 1: 0.5 0.5 <<VVrefref≤ ≤ Sector 2: 0 < V ref ≤ 0.5; Sector 2: 0 < V ref ≤ 0.5; Sector Vref < 0;< 0; Sector 3: 3: −0.5 −0.5≤≤ V ref Sector 4: −1 < V ref ≤ −0.5. Sector 4: −1 < V ref ≤ −0.5. The upup of of four sectors is shown in Figure 3. Each borderline of these The space spacevector vectordiagram diagrammade made four sectors is shown in Figure 3. Each borderline of four sectors corresponds with certain voltage vectors discussed above. The selection of the switching these four sectors corresponds with certain voltage vectors discussed above. The selection of the state is determined only afteronly identifying the sector, which the modulation wave wave works. The switching state is determined after identifying the in sector, in which the modulation works. reference vector V ref can be composed by the two nearest voltage vectors V a and V b . For example, The reference vector V ref can be composed by the two nearest voltage vectors V a and V b . For example, when ref is is composed byby V4 V and V2 when the the modulation modulation wave waveworks worksin inthe thesector sector1,1,the thereference referencevector vectorVV composed 4 and ref (or V3).VSince V 2 and V 3 are redundant to each other, either of them has a chance to be adopted, and V 2 (or ). Since V and V are redundant to each other, either of them has a chance to be adopted, 3 2 3 both of them working alone with V4 will be be able to to generate the same and both of them working alone with V 4 will able generate the samereference referencevector. vector.However, However, the the selection selection of of V V22 or or VV33will willaffect affectthe thebalance balancebetween betweenthe the dc-link dc-link capacitor capacitor voltages, voltages, which which will will be be discussed in next section. discussed in next section. 1 (Charge C1) V2 V1 (Discharge C1)V6 Vre f V4 0.5 0 V3 (Charge C2) V5 - 0.5 -1 V9 V7 (Discharge C1) V8 Figure Figure3. 3.Voltage Voltage vectors vectors diagram diagram for for aa single single phase phase 3LNPC 3LNPC rectifier. rectifier. On-time calculation is based on the volt-second balance equation and time balance equation. On-time calculation is based on the volt-second balance equation and time balance equation. Vref Ts Va Ta Vb Tb (5) VrefT · TsT=V Tba · Ta + Vb · Tb (5) a s Ts = Ta + Tb Va and Vb are the voltage vectors selected to synthesis the reference voltage vector Vref, V a and V b are theTbvoltage vectors selected tothe synthesis reference vector V ref correspondingly, Ta and stands for the duty time of relevantthe voltage vector.voltage Since the choice of, correspondingly, T and T stands for the duty time of the relevant voltage vector. Since the choice of a b voltage vectors varies in different sector, the on-time calculation results change with the position of voltage vectors varies in different sector, the on-time results charging/discharging change with the position of the reference vector. Since the redundant vectors will calculation produce different status the reference vector. Since the redundant vectors will produce different charging/discharging status of the dc-link capacitors. It is obvious that the SP and SN vector could be the main reason for the of the dc-link fluctuation capacitors. problem. It is obvious the SP and SN vector be the main reason for the neutral-point Thethat redundant vectors in SP could and SN vector categories have neutral-point fluctuation problem. The redundant vectors in SP and SNofvector categories have different different effects on the dc-link capacitors. Hence, the performance the internal-module voltage effects on the dc-link capacitors. Hence, the performance of the internal-module balancing scheme significantly depends on the selection of these switching states. voltage balancing scheme significantly onofthe of these switching states. In this paper, andepends extension theselection single phase 3LNPC rectifier SVPWM technique is adopted in In this paper, an extension of the single phase 3LNPC rectifier SVPWM technique adopted in cascaded multilevel rectifier. The harmonic content of the output voltage waveform canis be reduced cascaded multilevel rectifier. The harmonic content of the output voltage waveform can be reduced by by shifting the relative phases of the triangular carrier employed in each NPC rectifier. For a cascaded shifting with the relative of the triangular employed in each NPC rectifier. For a cascaded rectifier 3 powerphases cells, the carrier waves carrier between adjacent cells have a phase-angle difference of rectifier with 3 power cells, the carrier waves between adjacent cells have a phase-angle difference of 2π/3 as shown in Figure 4. So that the three-module 3LNPC-CR have thirteen voltage levels to reduce 2π/3 as shown in Figure 4. So that the three-module 3LNPC-CR have thirteen voltage levels to reduce the voltage stress and harmonic contents. the voltage stress and harmonic contents. ( Energies 2017, 10, 592 Energies Energies 2017, 2017, 10, 10, 592 592 6 of 16 66 of of 15 15 2π 2π Voltage(V) Voltage(V) 11 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 00 00 0.002 0.002 0.004 0.004 0.006 0.006 0.008 0.01 0.008 0.01 Time(s) Time(s) 0.012 0.012 0.014 0.014 0.016 0.016 0.018 0.018 0.02 0.02 Figure 4. Phase-shifted carrier-based SVPWM technique. Figure Figure 4. 4. Phase-shifted Phase-shifted carrier-based carrier-based SVPWM SVPWM technique. technique. 4. Balancing Strategy 4. Balancing Strategy In contrast to its advantageous modularity, each module of the cascaded multilevel rectifier In contrast to its advantageous modularity, each module of the cascaded multilevel rectifier cannot cannot be considered as a separate structure to control. The main difficulties of implementing the be considered as a separate structure to control. The main difficulties of implementing the single phase single phase 3LNPC-CR concentrate on its control algorithm. 3LNPC-CR concentrate on its control algorithm. 4.1. 4.1. Overall Overall Control Control In the same ACAC current. Thus, the the sumsum of the In fact, fact, nnrectifiers rectifiershave havetotobeberegulated regulatedthrough through the same current. Thus, of dcthe terminal voltages could be considered as an overall output voltage u o,sum . In order to obtain the grido,sum dc-terminal voltages could be considered as an overall output voltage uo,sum . In order to obtain the side unity power factor and a dc-side satisfactory load voltage regulation, the transient current grid-side unity power factor and a dc-side satisfactory load voltage regulation, the transient current control control is is adopted. adopted. The The basic basic structure structure of of the the proposed proposed scheme scheme is is depicted depicted in in Figure Figure 5. 5. The The control control scheme includes 2 loops: a current loop and a voltage loop. The current loop is adopted scheme includes 2 loops: a current loop and a voltage loop. The current loop is adopted to to improve improve the the dynamic dynamic response response of of system system and and is is necessary necessary for for generating generating aa sinusoidal sinusoidal input input current current with with unity unity power factor. A phase locked loop is adopted to lock the voltage phase and, in addition, to power factor. A phase locked loop is adopted to lock the voltage phase and, in addition, to generate generate the the synchronized synchronized outputs. outputs. By By multiplying multiplying aa reference reference input input current current amplitude amplitude IIsss** with with the the sinusoidal sinusoidal signal in phase with the grid voltage, a suitable instantaneous reference grid current i ss* is obtained. signal in phase with the grid voltage, a suitable instantaneous reference grid current is * is obtained. The The error error between between iisss** and and iisssisissent sentto tothe theProportional Proportional(P) (P)current currentcontroller. controller. In In this this case, case, aasatisfactory satisfactory grid current, who takes the path of the input voltage could be reached. The reference amplitude grid current, who takes the path of the input voltage could be reached. The reference amplitude of of the the input input current current is is derived derived from from the the voltage voltage loop. loop. A A controller controller is is employed employed in in the the outer outer control control loop loop to thethe desired reference value uo,sum *. The error of the o,sum at at o,sum to maintain maintain the thedc-link dc-linkoverall overallvoltage voltageuuo,sum desired reference value uo,sum *. The error of dcthe o,sum link overall voltage is controlled through a Proportional dc-link overall voltage is controlled through a ProportionalIntegral Integral(PI) (PI)voltage voltagecontroller. controller. The The output output value value of of the the PI PI voltage voltage controller controller is is chosen chosen as as the the amplitude amplitude of of the the reference reference gird gird current current amplitude amplitude IIss*.*.Finally, the output of the overall controller, which is supposed to work as the overall modulation s Finally, the output of the overall controller, which is supposed to work as the overall modulation signal ab*, signal uuab *,isisgiven givenby bythe thegrid gridside sideKVL KVLequation. equation. ab Figure Figure 5. 5. Control Control scheme scheme for for grid grid current current and and overall overall voltage. voltage. 4.2. Mutual-Module Voltage Balancing Strategy Cascaded multilevel converter aims to establish equal dc voltages across the dc terminals, which can become difficult if the loads attached to each module are not equal, or the series rectifiers have Energies 2017, 10, 592 7 of 16 4.2. Mutual-Module Voltage Balancing Strategy Energies 2017, 10, 592multilevel Cascaded 7 of 15 converter aims to establish equal dc voltages across the dc terminals, which can become difficult if the loads attached to each module are not equal, or the series rectifiers various characters. A PI-based solution is presented for voltage balancing of distinct dc terminals in have various characters. A PI-based solution is presented for voltage balancing of distinct dc terminals cascaded multilevel rectifier to prevent the mutual-model voltage fluctuation. in cascaded multilevel rectifier to prevent the mutual-model voltage fluctuation. The mutual-module voltage balancing scheme is addressed to ensure that the respective dc-side The mutual-module voltage balancing scheme is addressed to ensure that the respective dc-side voltage uoi of module i (i = 1, 2, …, n) converge to the respective reference value uoi*. As illustrated in voltage uoi of module i (i = 1, 2, . . . , n) converge to the respective reference value uoi *. As illustrated Figure 6. This PI-based voltage balancing scheme is basically adjust the modulation waves for each in Figure 6. This PI-based voltage balancing scheme is basically adjust the modulation waves for module. The output voltage of each module uoi is compared with the reference voltage uoi*. The error each module. The output voltage of each module uoi is compared with the reference voltage uoi *. between uoi and uoi* is sent into a PI regulator to derive the amplitude of the compensating current. The error between uoi and uoi * is sent into a PI regulator to derive the amplitude of the compensating In order to obtain the simultaneous grid current error (∆ei), the output of each PI controller is current. In order to obtain the simultaneous grid current error (∆ei ), the output of each PI controller multiplied with a unit sinusoidal signal in phase with the grid voltage. The modulation signals of is multiplied with a unit sinusoidal signal in phase with the grid voltage. The modulation signals of each module uabi* are derived from the sum of corresponding grid current error (∆ei) and the overall each module uabi * are derived from the sum of corresponding grid current error (∆ei ) and the overall modulation signal (uab*). Therefore, the modulation wave in each module is adjusted so that the real modulation signal (uab *). Therefore, the modulation wave in each module is adjusted so that the real power distribution can be changed according to the instantaneous output voltage. For the module power distribution can be changed according to the instantaneous output voltage. For the module with a lower output voltage, the real power transmitted to this module will be increased. In addition, with a lower output voltage, the real power transmitted to this module will be increased. In addition, the real power transmitted to the module with a higher output voltage will be decreased. In this way, the real power transmitted to the module with a higher output voltage will be decreased. In this way, the output voltages of all the cascaded modules can be balanced. the output voltages of all the cascaded modules can be balanced. Figure 6. Mutual-module voltage balancing scheme. Figure 6. Mutual-module voltage balancing scheme. According to thethe modulation depth of each shows shows the connection between According to the thedefinition, definition, modulation depth of module each module the connection the peak value of the input voltage and the output voltage in each module. As shown in the following between the peak value of the input voltage and the output voltage in each module. As shown in the equation, equation, mi represents the modulation depth of module = 1, 2, .i .(i. =, n). following mi represents the modulation depth ofi (i module 1, 2, …, n). √ 2Uabi m 2U mi i V· oVi oi abi = (6)(6) The The input input inductance inductanceisis neglected neglectedsince sinceitit has has little little effect effect on on input input voltage. voltage. Thus, Thus, the the effective effective value of the grid voltage is represented as: value of the grid voltage is represented as: nM V U s U ab nM · oVo 2 √ (7) (7) 2 M equals to the modulation depth of a 3LNPC-CR with n modules. Thus, the relationship M equals modulation depth between mi andtoMthe could be derived as of a 3LNPC-CR with n modules. Thus, the relationship between mi and M could be derived as Us ≈ Uab = n nM V o n m i V o (V o V oi ) i 1 (8) nM · Vo = ∑ mi · Vo (Vo = Voi ) (8) 1 module 1 has the minimum admittance y1 and the After the load change, suppose the loadi=of loads of the rest modules are of the same admittance value, which could be described as: After the load change, suppose the load of module 1 has the minimum admittance y1 and the y 2 y 3 value, y nwhich could be described as: loads of the rest modules are of the samey1admittance (9) The real power transmitted to each y1 <module y2 = y3 should = · · · =be yn proportional to its load admittance. (9) Without the mutual-module balancing scheme, the load with a smaller admittance has a higher voltage while loadstransmitted with largertoadmittance haveshould lower voltage. This change will be reflected in The real the power each module be proportional to its load admittance. the modulation waveforms of balancing each module. Under effect of mutual-module balancing Without the mutual-module scheme, thethe load with a smaller admittance has scheme, a higher the power transmitted towith each larger module is correspondingly changed. The realchange powerwill transmitted to the voltage while the loads admittance have lower voltage. This be reflected in module with a higher voltage will be linearly decreased and the real power transmitted to the module with lower voltage will be linearly increased. In this way, the output voltages of the dc-link terminals will be balanced. However, under the condition of over-modulation, the operation of the modulator will be extended into non-linear regions and will cause significant low-frequency harmonic components. Thus, the balancing strategy will manage to maintain the output voltages only if the Energies 2017, 10, 592 8 of 16 the modulation waveforms of each module. Under the effect of mutual-module balancing scheme, the power transmitted to each module is correspondingly changed. The real power transmitted to the module with a higher voltage will be linearly decreased and the real power transmitted to the module with lower voltage will be linearly increased. In this way, the output voltages of the dc-link terminals will be balanced. However, under the condition of over-modulation, the operation of the modulator will be extended into non-linear regions and will cause significant low-frequency harmonic components. Thus, the balancing strategy will manage to maintain the output voltages only if the modulation depth of each module is between 0 and 1. Otherwise, the change of input power will not be enough to compensate the voltage rise or drop. ( 0 < m1 < 1 0 < m2 = m3 = · · · = m n < 1 (10) The modulation depth of module 2 to module n can be represented by the modulation depth of module 1, as shown in Formula (11). m2 = m3 = · · · = m n = nM − m1 n−1 (11) As mentioned above, in order to maintain the dc-link voltage balanced, the modulation depth of each module is limited between 0 and 1. When the loads of each module are unbalanced, only one circumstance is considered. As derived in Formula (9), the load in module 1 is the only load different from the others. Suppose y1 is of the minimum load admittance, when the loads are unbalanced, the unbalance degree is defined as: n·y ∆y = n 1 (12) ∑ yi i =1 When the loads are balanced, the unbalance degree (∆y) equals to 1. When the load of module 1 is cut off, the unbalance degree (∆y) equals to 0. Suppose the power losses on the transmission circuit is neglected, the input real power transmitted to module 1 is: P1 = m1 · Vo · Is = Vo 2 · y1 (13) Thus, the modulation depth of module 1 is derived as: m1 = Vo · y1 Is (14) Suppose there is no real power loss during the transmission process, the total input power of the cascaded 3LNPC-CR can be represented as: n P = n · M · Vo · Is = Vo 2 ∑ yi (15) i =1 Thus, the grid current can be yield as: Is = n Vo · ∑ yi n · M i =1 (16) Substitute the Is in (14) with (16), the modulation depth of module 1 can be described as: m1 = n · y1 n ∑ yi i =1 · M = ∆y · M (17) Energies 2017, 10, 592 9 of 16 Substitute the m1 in (11) with (18), the modulation depth of module 2 to module n is derived as: m2 = m3 = · · · = m n = n − ∆y ·M n−1 (18) Combine the Formula (18) with the modulation depth limitation shown in Formula (10), the boundary of unbalance degree is derived: nM − n + 1 < ∆y M (19) 4.3. Internal-Module Voltage Balancing Strategy To eliminate the neutral-point voltage fluctuation in each module, several methods, including balancing scheme based on software and hardware, have been proposed. Software-based balancing scheme reallocates the redundant switching states to eliminate the fluctuation of the neutral-point voltage in each module. This voltage balancing scheme should be used along with the SVPWM. As mentioned above, the SVPWM is achieved only after these following steps: • • • Determining the location of the reference signal; The calculation of on-times; Determination and selection of redundant vectors. The redundant vectors have different effects on the dc-link capacitors. Thus, by suitably selecting and executing the redundant vectors during respective on-times, V C1 and V C2 could be balanced by adjusting the charging/discharging status of each dc-link capacitors. Power flow signal, worked as a redundancy selection signal, is vital to this process. The voltage difference between dc-link capacitors C1 and C2 , along with the grid current are measured to derive a power flow signal. Therefore, the redundant switching states chosen according to the power flow signal are listed in Table 2. Table 2. The principle of internal-module voltage balancing. V C1 > V C2 , is > 0 V C1 > V C2 , is < 0 V C1 < V C2 , is < 0 V C1 < V C2 , is > 0 SP = V3 SN = V7 SP = V2 SN = V6 SP = V3 SN = V7 SP = V2 SN = V6 Two kinds of voltage balancing auxiliary circuits, including one based on inductor and the other based on capacitor, are addressed as hardware-based balancing scheme. The balancing operation based on the additional capacitor Ca1 is described in Figure 7. When Sa1 , Sa3 are turned on and Sa2 , Sa4 are turned off, energy will exchange between the upper capacitor C1 and the additional capacitor Ca1 via the path highlighted in Figure 7a. C1 charges Ca1 or Ca1 charges C1 when vC1 > vCa1 or vC1 < vCa1 . If Sa1 , Sa3 are off and Sa2 , Sa4 are on, the energy exchange happens between the lower capacitor Ca2 and the additional capacitor Ca1 via the current path highlighted in Figure 7b. In this case, C2 charges Ca1 if vC2 > vCa1 or Ca1 charge C2 while vC2 < vCa1 . Therefore the additional Ca1 is important to temporarily store electric power between C1 and C2 . A resistor is connected in series with the additional capacitor Ca1 to limit the magnitude of the charge/discharge current. However, compared to its merits of limiting the rush current, the extra resistor will result in unexpected power loss. In order to avoid the short circuit fault, switch Sa1 , Sa3 and switch Sa2 , Sa4 should be alternately turned on. Finally, the voltages on C1 and C2 will be equalized. In this case, C2 charges Ca1 if vC2 > vCa1 or Ca1 charge C2 while vC2 < vCa1. Therefore the additional Ca1 is important to temporarily store electric power between C1 and C2. A resistor is connected in series with the additional capacitor Ca1 to limit the magnitude of the charge/discharge current. However, compared to its merits of limiting the rush current, the extra resistor will result in unexpected power loss. In2017, order to avoid the short circuit fault, switch Sa1, Sa3 and switch Sa2, Sa4 should be alternately Energies 10, 592 10 of 16 turned on. Finally, the voltages on C1 and C2 will be equalized. Figure 7. Capacitor-based voltage balancing scheme: (a) (a) C1 C charges Ca1;Cand (b) (b) Ca1 C charges C2. C2 . Figure 7. Capacitor-based voltage balancing scheme: 1 charges a1 ; and a1 charges Energies 2017, 10, 592 10 of 15 As illustrated illustrated in in Figure Figure 8, 8, an an inductor-based inductor-based auxiliary auxiliary circuit circuit enables enables energy energy transmission transmission from from As one capacitor to the other via the auxiliary inductor L . Two serial switches and the serial dc-link a1 one capacitor to the other via the auxiliary inductor La1. Two serial switches and the serial dc-link capacitors C C11,, CC22 are are connected connected in in series, series, with with aa resonant resonant inductor inductor L La1 connected between between their their a1 connected capacitors midpoints. Three Threesteps stepsare aretaken takentotoaccomplish accomplishthe thetransfer transfer process. example, when C2 , midpoints. process. ForFor example, when vC1v>C1vC2>, vthe the first step is to transfer the energy stored in the upper capacitor C to the additional inductor L a1 first step is to transfer the energy stored in the upper capacitor C1 to 1the additional inductor La1 via Sa1depicted as depicted by the highlighted path Figure8a. 8a.The Theinductor inductorcurrent currentiiLa1 increaseswhile while the the La1increases Svia a1 as by the highlighted path in in Figure capacitor voltage voltage vvC1 decreasesduring duringthe thefirst first step. step. Secondly, Secondly, as as shown shown in in Figure Figure 8b, 8b, the the inductor inductor L C1decreases capacitor La1 a1 is connected to the lower capacitor C via the anti-parallel diode D . The energy stored in auxiliary a2. The energy stored in auxiliary is connected to the lower capacitor C22 via the anti-parallel diode Da2 inductorisistransferred transferredtotocompensate compensatethe thelack lack power storage in the lower capacitor C2 . During inductor ofof power storage in the lower capacitor C2. During this this step, the inductor current i decreases while, in contrast, the voltage of the lower capacitor La1 step, the inductor current iLa1 decreases while, in contrast, the voltage of the lower capacitor vC2 vC2 increases. inductor current decreases zero, theprevious previousconducted conductedpath pathwill will block block increases. OnceOnce the the inductor current decreases to to zero, the reversely until until next next period. period. In In this this way, way, the and vvC2 isaccomplished. accomplished. C2 is reversely the voltage voltage balancing balancing between between vvC1 C1 and The balancing process is similar when v < v . In order to properly execute the auxiliary circuit, the the C2. In order to properly execute the auxiliary circuit, The balancing process is similar when vC1 C1 < vC2 adjacent two series switches in one unit cannot be turned on at the same time. adjacent two series switches in one unit cannot be turned on at the same time. Figure vC1vC1 > v>C2v : C2 (a): C(a) 1 charges La1; and Figure 8. 8. Inductor-based Inductor-basedvoltage voltagebalancing balancingscheme schemewhen when C1 charges La1 ; (b) andLa1(b) La1 charges C 2 . charges C2 . The auxiliary balancing circuits are totally independent form the main circuit. Therefore, the The auxiliary balancing circuits are totally independent form the main circuit. Therefore, neutral-point voltage is settled with the characteristics of the main circuit remain uninfluenced. the neutral-point voltage is settled with the characteristics of the main circuit remain uninfluenced. 5. 5. Simulation Simulation and and Experiment Experiment To verify the the performance performance of of the the proposed proposed control control strategies. strategies. The To verify The three-module three-module single-phase single-phase 3LNPC-CR MATLAB/Simulink (MathWorks, 3LNPC-CR is is modeled. modeled. The The simulation simulation is is carried carried out out in in MATLAB/Simulink (MathWorks, Natick, Natick, MA, USA). MA, USA). The capacitor voltages in one single-phase 3LNPC rectifier module is shown in Figure 9. During the first 0.3 s, the capacitor voltages are balanced using inductor-based auxiliary balancing circuit. To highlight the effect of auxiliary circuit, a resistor connected in parallel with one of the capacitors is switched on at 0.3 s. Obviously, the balance between these two capacitor voltages is broken. However, the voltages on the upper capacitor and the lower capacitor become stabilized and equalized in 0.3 s. 25 5. Simulation and Experiment To verify the performance of the proposed control strategies. The three-module single-phase 3LNPC-CR is modeled. The simulation is carried out in MATLAB/Simulink (MathWorks, Energies 2017, 10, 592 11 ofNatick, 16 MA, USA). The capacitor voltages in one single-phase 3LNPC rectifier module is shown in Figure 9. During The capacitor voltages in one single-phase 3LNPC rectifier module is shown in Figure 9. During the first 0.3 s, the capacitor voltages are balanced using inductor-based auxiliary balancing circuit. To the first 0.3 s, the capacitor voltages are balanced using inductor-based auxiliary balancing circuit. highlight the effect of auxiliary circuit, a resistor connected in parallel with one of the capacitors is To highlight the effect of auxiliary circuit, a resistor connected in parallel with one of the capacitors is switched on at 0.3 s. Obviously, the balance between these two capacitor voltages is broken. However, switched on at 0.3 s. Obviously, the balance between these two capacitor voltages is broken. However, the voltages on the upper capacitor capacitorbecome become stabilized equalized the voltages on the upper capacitorand andthe thelower lower capacitor stabilized andand equalized in 0.3ins.0.3 s. Voltage (V) 25 20 A 10 Ω resistor connected in parallel with one capacitor is switched on 15 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Time (s) Figure 9. Capacitor voltages with inductor-based auxiliary balancing circuit. Energies 2017, 10, 592Figure 9. Capacitor voltages with inductor-based auxiliary balancing circuit. 11 of 15 Figure 10 shows shows the the characteristic characteristic of of the the input inputvoltage voltageof ofthree-module three-modulesingle-phase single-phase3LNPC-CR. 3LNPC-CR. The thirteen-level thirteen-level staircase staircase voltage is generated using phase-shifted phase-shifted SVPWM SVPWM strategy strategy shown shown in Figure 4. 150 Voltage (V) 100 50 0 -50 -100 -150 0 0.005 0.01 0.015 0.002 Time(s) 0.025 0.03 0.035 0.02 Figure Figure 10. 10. Input Input voltage voltage of of three-module three-module 3LNPC-CR. 3LNPC-CR. Two different cases have been simulated to verify the multi-module control strategy. During the Two different cases have been simulated to verify the multi-module control strategy. During the first 0.3 s, the loads of each module are balanced. The output voltage of each module becomes constant first 0.3 s, the loads of each module are balanced. The output voltage of each module becomes constant and all of them converge to 50 V at 0.12 s. At 0.3 s, the load of module 1 is changed from 20 Ω to 50 Ω, and all of them converge to 50 V at 0.12 s. At 0.3 s, the load of module 1 is changed from 20 Ω to which means the output voltages are supposed to be different without the balancing scheme. 50 Ω, which means the output voltages are supposed to be different without the balancing scheme. As shown in Figure 11, the voltage balancing scheme is accomplished by immediately modifying the As shown in Figure 11, the voltage balancing scheme is accomplished by immediately modifying the modulation depth of each rectifier module. After little voltage fluctuation during a few switching modulation depth of each rectifier module. After little voltage fluctuation during a few switching periods, the output voltages managed to converge to 50 V. Thus, the internal-voltage balancing periods, the output voltages managed to converge to 50 V. Thus, the internal-voltage balancing scheme scheme is verified. is verified. 70 Voltage (V) 60 50 Load Change (20Ω to 50Ω ) 40 Start Up 30 0 m=0.78 0.1 Load Unalance Load Balance 0.2 0.3 Time (s) 0.4 0.5 0.6 and all of them converge to 50 V at 0.12 s. At 0.3 s, the load of module 1 is changed from 20 Ω to 50 Ω, which means the output voltages are supposed to be different without the balancing scheme. As shown in Figure 11, the voltage balancing scheme is accomplished by immediately modifying the modulation depth of each rectifier module. After little voltage fluctuation during a few switching periods, the output voltages managed to converge to 50 V. Thus, the internal-voltage balancing Energies 2017, 10, 592 12 of 16 scheme is verified. 70 Voltage (V) 60 50 Load Change (20Ω to 50Ω ) 40 Start Up 30 0 m=0.78 0.1 Load Unalance Load Balance 0.2 0.3 Time (s) 0.4 0.5 0.6 Figure Figure 11. 11. Output Output voltages voltages using using multi-module multi-module balancing balancing scheme. scheme. As shown in Figure 12, a three-module single phase 3LNPC-CR prototype has been built on the As shown in Figure 12, a three-module single phase 3LNPC-CR prototype has been built on laboratory setup. The three-module single phase 3LNPC-CR works on the occasion of 50 Hz 75 V the laboratory setup. The three-module single phase 3LNPC-CR works on the occasion of 50 Hz input voltage. When the loads are balanced, each dc-link terminal could obtain 50 V output voltage. 75 V input voltage. When the loads are balanced, each dc-link terminal could obtain 50 V output The controller of the 3LNPC-CR is based on the EP3C55F484C8 FPGA chip. The parameters are voltage. The controller of the 3LNPC-CR is based on the EP3C55F484C8 FPGA chip. The parameters reported in Table 3. are2017, reported Energies 10, 592in Table 3. 12 of 15 Figure 12.12. Prototype singlephase phase 3LNPC-CR. Figure Prototypeof ofthree-module three-module single 3LNPC-CR. Table ofexperiment. experiment. Table3.3.Parameters Parameters of Parameter Name Parameter Name Number of modules Number of modules Voltage source Voltage source dc-link dc-link capacitor capacitor Inductance circuit Inductanceof of auxiliary auxiliary circuit Inductance of of LC Inductance LC filter filter Capacitance of of LC Capacitance LC filter filter Switching frequency Switching frequency Parameter Value Parameter Value 3 3 75 V/50 Hz 75 V/50 Hz 2200 µF 2200 µF 1 mH mH 11 mH mH 2200 2200 µF µF 2 kHz 2 kHz experiment results of the internal-modulevoltage voltagebalancing balancing strategy strategy are The The experiment results of the internal-module areshown shownininFigure Figure13.13. Energies 2017, 10, 592 Voltage source dc‐link capacitor Inductance of auxiliary circuit Inductance of LC filter Capacitance of LC filter Switching frequency 75 V/50 Hz 2200 μF 1 mH 1 mH 2200 μF 2 kHz 13 of 16 (a) Switch on the inductorbased auxiliary circuit (c) (b) Switch off the inductorbased auxiliary circuit (d) Figure 13. Experiment Figure 13. Experiment results: results: (a) (a) dc‐link dc-link capacitor capacitor voltages voltages and and input input voltage voltage of of 3LNPC 3LNPC rectifier rectifier without (CH1: the CH3: the without auxiliary auxiliary circuit circuit (CH1: the input input voltage voltage of of 3LNPC 3LNPC rectifier, rectifier, CH3: the dc‐link dc-link voltage voltage on on capacitor C capacitor C11, CH4: the dc‐link voltage on capacitor C , CH4: the dc-link voltage on capacitor C22); (b) dc‐link capacitor voltages and input voltage ); (b) dc-link capacitor voltages and input voltage when auxiliary circuit is implemented (CH1: the input voltage of 3LNPC rectifier, CH3: the dc‐link when auxiliary circuit is implemented (CH1: the input voltage of 3LNPC rectifier, CH3: the dc-link voltage on capacitor C voltage on capacitor C11, CH4: the dc‐link voltage on capacitor C , CH4: the dc-link voltage on capacitor C22); (c) dynamic waveform of dc‐link ); (c) dynamic waveform of dc-link capacitor voltages (CH1: the dc‐link voltage on capacitor C 1, CH2: the dc‐link voltage on capacitor capacitor voltages (CH1: the dc-link voltage on capacitor C1 , CH2: the dc-link voltage on capacitor C2 ); and (d) dynamic waveform of dc-link capacitor voltages (CH1: the dc-link voltage on capacitor C1 , CH2: the dc-link voltage on capacitor C2 ). Figure 13a,b shows the waveforms of dc-link voltages and ac-side input voltage in one single-phase 3LNPC rectifier module before and after the inductor-based auxiliary circuit is implemented. To assess the system dynamic performance, two types of tests have been considered. The first test switched on the inductor-based auxiliary circuit to balance the unbalanced dc-link capacitor voltage. Figure 13c shows the dynamic waveforms of dc-link capacitors when the inductor-based auxiliary balancing circuit is activated. It is obvious that the dc-link capacitor voltages converge to the reference value after several periods. In the second test, the auxiliary circuit is switched off. Figure 13d demonstrates the transient voltage of dc-link capacitors when the auxiliary balancing circuit is suddenly switched off. It is obvious that the dc-link capacitor voltages become unbalanced without the auxiliary circuit. In this way, both of these two tests verified the effectiveness of the inductor-based auxiliary circuit. The Five-level wave form shown in Figure 14a is typical of input voltages of a 3LNPC rectifier. A Thirteen-level overall input voltage waveform is generated via the phase shift technology. It is obvious that the input voltage is identical with the simulation result. Figure 14b illustrates the grid voltage and the grid current. It is possible to notice that the grid current keeps well in phase with the grid voltage. That is to say, unity power factor is achieved. The perfect agreement between these experimental results and the former analysis is reached. A Thirteen-level overall input voltage waveform is generated via the phase shift technology. It is obvious that the input voltage is identical with the simulation result. Figure 14b illustrates the grid voltage and the grid current. It is possible to notice that the grid current keeps well in phase with the grid voltage. That is to say, unity power factor is achieved. The perfect agreement between these Energies 2017, 10, 592 14 of 16 experimental results and the former analysis is reached. Module 1 Module 2 Input voltage Grid voltage Module 3 Grid current Input voltage (a) (b) Figure 14. Experiment results: Input voltagesof ofthe the 3LNPC 3LNPC rectifier three-module 3LNPC-CR Figure 14. Experiment results: (a)(a) Input voltages rectifierand and three-module 3LNPC-CR (CH1: the input voltage of module 1, CH2: the input voltage of module 2, CH3: the input voltage of of (CH1: the input voltage of module 1, CH2: the input voltage of module 2, CH3: the input voltage module 3, CH4: the input voltage of the three-module 3LNPC-CR); and (b) AC-side voltage and current module 3, CH4: the input voltage of the three-module 3LNPC-CR); and (b) AC-side voltage and of the three-module 3LNPC-CR (CH2: the grid voltage of the three-module 3LNPC-CR, CH3: the grid current of the three-module 3LNPC-CR (CH2: the grid voltage of the three-module 3LNPC-CR, CH3: current of the three-module 3LNPC-CR, CH4: the input voltage of the three-module 3LNPC-CR). the grid current of the three-module 3LNPC-CR, CH4: the input voltage of the three-module 3LNPC-CR). In order to verify the viability of mutual-module voltage balancing control strategy, an experiment In order to verify the viability of mutual-module voltage balancing control strategy, an experiment has been carried out based on the 3LNPC-CR prototype. The resistor R is dynamically changed has been carried out based on the 3LNPC-CR prototype. The resistor R1 is1dynamically changed while while the resistors R2 and R3 remains 20 Ω to create the unbalance of dc-loads, so that the real power the resistors R2 and R3 remains 20 Ω to create the unbalance of dc-loads, so that the real power transmitted to module 1 is different from module 2 and module 3. According to Formula (19), the load transmitted to 1 is different from module 2 and module to Formula unbalancemodule degree limit of a three-module 3LNPC-CR depends3.onAccording its modulation index. (19), Thus,the theload unbalance degree limit three-module 3LNPC-CR depends on its Thus, the calculation results of of theamaximum load unbalance limit are verified by modulation implementingindex. 3LNPC-CRs calculation resultsmodulation of the maximum with different indexes.load unbalance limit are verified by implementing 3LNPC-CRs Since modulation the input inductance with different indexes. is ignored during the calculation, the balancing boundary is an approximate result. In fact, the is mutual-module balancing strategy is still to balance the dc-linkis an Since the input inductance ignored during the calculation, theable balancing boundary voltages when the unbalance degree slightly exceeds the calculation result. However, if the unbalance approximate result. In fact, the mutual-module balancing strategy is still able to balance the dc-link degree exceeds the calculated boundary by a large margin, the balancing strategy will fail to balance voltages when the unbalance degree slightly exceeds the calculation result. However, if the unbalance the dc-link voltages. When the three-module 3LNPC-CR works in the modulation depth of 0.7, degree exceeds the calculated boundary by a large margin, the balancing strategy will fail to balance the reference voltage of each dc terminals is 47 V. According to the Formula (19), this mutual-module the dc-link voltages. When the three-module 3LNPC-CR works in the modulation depth of 0.7, the balancing strategy is effective when ∆y > 0.14. The maximum degree of load unbalance happens reference voltage of each dc terminals is 47 V. According to the Formula (19), this mutual-module when the load resistor R1 is 200 Ω while R2 and R3 equal to 20 Ω. As shown in Figure 15a, after the balancing strategy effective when ∆ y > 0.14. The maximum degree of loadbalancing unbalance happens load change, theisdc-link voltage of module 1 increased. With the mutual-module strategy, Ω while R2 and Rto3 47 equal to 20 this Ω. As shownthe in grid Figure 15a,isafter whenthe the load voltages resistor become R1 is 200 dc-link steady and converge V. During transition, current not the load changed change, the dc-link voltage increased.The With the mutual-module balancing strategy, except a reduction ofof themodule current 1amplitude. balancing boundary of the three-module 3LNPC-CR with abecome modulation depth 0.8 is also to verified. The mutual strategy functions the dc-link voltages steady andofconverge 47 V. During thisbalancing transition, the grid current is well on the premise that ∆y > 0.5. The maximum load resistor R within the balancing boundary 1 not changed except a reduction of the current amplitude. The balancing boundary of the threeis 50 Ω, as shown in Figure 15b. The mutual-module balancing strategy is still able to balance the dc-link terminal voltages when R1 is 50 Ω while R2 and R3 equal to 20 Ω. As demonstrated in Figure 15c, with a modulation depth of 0.9, the reference value of the dc-link terminals are 41 V. The unbalance degree boundary calculated according to Formula (19) is ∆y > 0.78. The mutual-module balancing strategy managed to balance the dc-link terminal voltages when the load resistor R1 is 30 Ω. The experimental results are in accordance with the calculation results. In this way, the calculation result of the balancing boundary is verified. in Figure 15c, with a modulation depth of 0.9, the reference value of the dc-link terminals are 41 V. The unbalance degree boundary calculated according to Formula (19) is ∆ y > 0.78. The mutualmodule balancing strategy managed to balance the dc-link terminal voltages when the load resistor R1 is 30 Ω. The experimental results are in accordance with the calculation results. In this way, the Energies 2017, 10, 592 15 of 16 calculation result of the balancing boundary is verified. R1 Load change From 20Ω to 50Ω R1 Load change From 20Ω to 200 Ω M=0.7 (a) R1 Load Change From 20Ω to 30Ω M=0.8 (b) M=0.9 (c) Figure 15. Experiment results: 0.7,RR1 1changes changes from from 20 (CH1: dc-link voltage of of Figure 15. Experiment results: (a)(a) MM= =0.7, 20ΩΩtoto200 200Ω Ω (CH1: dc-link voltage module 1, CH2: dc-link voltage of module2, CH3: dc-link voltage of module3, CH4: grid current of module 1, CH2: dc-link voltage of module2, CH3: dc-link voltage of module3, CH4: grid current of the three-module 3LNPC-CR); (b) M = 0.8, R changes from 20 Ω to 50 Ω (CH1: dc-link voltage of the three-module 3LNPC-CR); (b) M = 0.8, R1 1changes from 20 Ω to 50 Ω (CH1: dc-link voltage of module 1, CH2: dc-link voltage of module2, CH3: dc-link voltage of module 3, CH4: grid current of module 1, CH2: dc-link voltage of module2, CH3: dc-link voltage of module 3, CH4: grid current of the three-module 3LNPC-CR); and (c) M = 0.9, R1 changes from 20 Ω to 30 Ω (CH1: dc-link voltage of the three-module 3LNPC-CR); andof(c) M = 0.9, R1 changes 20of Ωmodule to 30 Ω3,(CH1: dc-link voltage module 1, CH2: dc-link voltage module 2, CH3: dc-link from voltage CH4: grid current of of module 1, CH2: dc-link voltage of module 2, CH3: dc-link voltage of module 3, CH4: grid current of the three-module 3LNPC-CR). the three-module 3LNPC-CR). 6. Conclusions 6. Conclusions Several control strategies are proposed to solve the balancing problems of single-phase 3LNPC-CR. A PI-based scheme used along with the transient control strategy successfully obtains3LNPCan Several control strategies are proposed to solvecurrent the balancing problems of single-phase expected sinusoidal grid current with unity power factor and regulated output voltages. The output CR. A PI-based scheme used along with the transient current control strategy successfully obtains an voltages successfully to theunity reference value evenand if the loads in each module are different. expected sinusoidal grid converge current with power factor regulated output voltages. The output The inductor-based balancing strategy is addressed to balance the dc-link voltages in a single-phase voltages successfully converge to the reference value even if the loads in each module are different. 3LNPC rectifier module. The auxiliary circuit does not have any effects on the main circuit and is The inductor-based balancing strategy is addressed to balance the dc-link voltages in a single-phase controlled separately. Corresponding experiments have been carried out to verify the above features. 3LNPC rectifier module. The auxiliary circuit does not have any effects on the main circuit and is Therefore the effectiveness of the proposed control strategy is confirmed. controlled separately. Corresponding experiments have been carried out to verify the above features. Acknowledgments: This work wasproposed supported control by the National Natural Science Foundations of China (Grant Therefore the effectiveness of the strategy is confirmed. No. 51477144). Author Contributions: Xu Peng Xiaoqiong strategy and the experiments;ofPengcheng Acknowledgments: This work was and supported byHe theconceived Nationalthe Natural Science Foundations China (Grant Han performed the experiments; Zeliang Shu analyzed the data; Shibin Gao contributed experiment prototype; No. 51477144). and Xiaolan Lin wrote the paper. Author Contributions: Peng anddeclare Xiaoqiong He conceived the strategy and the experiments; Pengcheng Han Conflicts of Interest:Xu The authors no conflict of interest. performed the experiments; Zeliang Shu analyzed the data; Shibin Gao contributed experiment prototype; and References Xiaolan Lin wrote the paper. 1. of Kouro, S.; Malinowski, M.; Gopakumar, K.; Pou, J.; Franquelo, L.G.; Wu, B.; Rodriguez, J.; Perez, M.A.; Conflicts Interest: The authors declare no conflict of interest. Leon, J.I. Recent advances and industrial applications of multilevel converters. IEEE Trans. Ind. Electron. 2010, 57, 2553–2580. [CrossRef] References 2. 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