Download CHAPTER 2 OPERATIONAL AMPLIFIERS

CHAPTER 2 OPERATIONAL AMPLIFIERS
Chapter Outline
2.1 The Ideal Op Amp
2.2 The Inverting Configuration
2.3 The Noninverting Configuration
2.4 Difference Amplifiers
2.5 Integrators and Differentiators
2.6 DC Imperfections
2.7 Effect of Finite Open‐Loop Gain and Bandwidth on Circuit Performance
2.8 Large‐Signal Operation of Op Amp
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2.1 Ideal Op Amp
Introduction
Their applications were initially in the area of analog computation and instrumentation
Op amp is very popular because of its versatility
Op amp circuits work at levels that are quite close to their predicted theoretical performance
The op amp is treated a building block to study its terminal characteristics and its applications
Op‐amp symbol and terminals
Two input terminals: inverting input terminal () and noninverting input terminal (+)
One output terminal
Two dc power supplies V + and V 
Other terminals for frequency compensation and offset nulling
Circuit symbol for op amp
Op amp with dc power supplies
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Ideal characteristics of op amp
Differential‐input single‐ended‐output amplifier
Infinite input impedance i1 = i2 = 0 (regardless of the input voltage)
Zero output impedance
vO= A(v2 – v1) (regardless of the load)
Infinite open‐loop differential gain
Infinite common‐mode rejection
Infinite bandwidth
Differential and common‐mode signals
Two independent input signals: v1 and v2
Differential‐mode input signal (vId): vId = (v2 – v1)
Common‐mode input signal (vIcm): vIcm = (v1 + v2)/2
Alternative expression of v1 and v2:
v1 = vIcm – vId /2
v2 = vIcm + vId /2
Exercise 2.2 (Textbook)
Exercise 2.3 (Textbook)
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2.2 The Inverting Configuration
The inverting close‐loop configuration
External components R1 and R2 form a close loop
Output is fed back to the inverting input terminal
Input signal is applied from the inverting terminal
Inverting‐configuration using ideal op amp
The required conditions to apply virtual short for op‐amp circuit:
 Negative feedback configuration
 Infinite open‐loop gain
Closed‐loop gain: G ≡ vO /vI =  R2 /R1
 Infinite differential gain: v2  v1 = vO /A = 0
 Infinite input impedance: i2 = i1 = 0
 Zero output impedance: vO = v1  i1 R2 =  vI R2 /R1
 Voltage gain is negative
Input and output signals are out of phase
 Closed‐loop gain depends entirely on external passive components (independent of op‐amp gain)
 Close‐loop amplifier trades gain (high open‐loop gain) for accuracy (finite but accurate closed‐loop gain)
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Equivalent circuit model for the inverting configuration
 Input impedance: Ri ≡vI /iI = vI / (vI /R1) = R1
For high input closed‐loop impedance, R1 should be large, but is limited to provide sufficient G
In general, the inverting configuration suffers from a low input impedance
 Output impedance: Ro = 0
 Voltage gain: Avo = R2/R1
Other circuit example for inverting configuration
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Application: the weighted summer
A weighted summer using the inverting configuration
n
Rf
k 1
R1
vO  0  R f  ik  (
v1 
Rf
R2
v2  ... 
Rf
Rn
vn )
A weighted summer for coefficients of both signs
R 
 R  R 
 R  R 
 Rc 
vO  v1  a  c   v2  a  c   v3  c   v4  
 R1  Rb 
 R2  Rb 
 R4 
 R3 
Exercise 2.4 (Textbook)
Exercise 2.6 (Textbook)
Exercise 2.7 (Textbook)
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2.3 Noninverting Configuration
The noninverting close‐loop configuration
External components R1 and R2 form a close loop
Output is fed back to the inverting input terminal
Input signal is applied from the noninverting terminal
Noninverting configuration using ideal op amp
The required conditions to apply virtual short for op‐amp circuit:
 Negative feedback configuration
 Infinite open‐loop gain
Closed‐loop gain: G ≡ vO /vI = 1 + R2 /R1
 Infinite differential gain: v+  v = vO /A = 0
 Infinite input impedance: i2 = i1 = v /R1
 Zero output impedance: vO = v + i1R2 = vI (1 + R2 /R1)
 Closed‐loop gain depends entirely on external passive components (independent of op‐amp gain)
 Close‐loop amplifier trades gain (high open‐loop gain) for accuracy (finite but accurate closed‐loop gain)
Equivalent circuit model for the noninverting configuration
 Input impedance: Ri = 
 Output impedance: Ro = 0
 Voltage gain: Avo = 1 + R2 /R1
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(1+R2/R1)vi
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The voltage follower
Unity‐gain buffer based on noninverting configuration
Equivalent voltage amplifier model:
 Input resistance of the voltage follower Ri = 
 Output resistance of the voltage follower Ro = 0
 Voltage gain of the voltage follower Avo = 1
The closed‐loop gain is unity regardless of source and load
It is typically used as a buffer voltage amplifier to connect a source with a high impedance to a low‐
impedance load
Exercise 2.9 (Textbook)
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Exercise 1: Assume the op amps are ideal, find the voltage gain (vo/vi) of the following circuits.
(1) (2)
(3) (4)
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2.4 Difference Amplifiers
Difference amplifier
Ideal difference amplifier:
 Responds to differential input signal vId
 Rejects the common‐mode input signal vIcm
Practical difference amplifier:
 vO = AdvId + AcmvIcm
Ad is the differential gain
Acm is the common‐mode gain
 Common‐mode rejection ratio (CMRR):
CMRR  20 log
| Ad |
| Acm |
Single op‐amp difference amplifier
R4
v I 2  v
R3  R4
v v 
R
1  R2 / R1
vO  v  iR2  v    1  R2   2 vI 1 
vI 2
R1
1  R3 / R4
 R1 
v 

R2
vIcm  vId / 2  1  R2 / R1 vIcm  vId / 2
R1
1  R3 / R4
 1  R2 / R1 R2 
1  1  R2 / R1 R2 
 
 vIcm  
 vId

R
R
R

R
R
R1 
1
/
2
1
/
3
4
1 
3
4


1  1  R2 / R1 R2 
 
Ad  
2  1  R3 / R4 R1 
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 1  R2 / R1 R2 
 
Acm  
 1  R3 / R4 R1 
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Superposition technique for linear time‐invariant circuit
Set vI2 = 0 → vO1  ( R2 / R1 )vI 1
 R  R4 
vI 2
Set vI1 = 0 → vO 2  1  2 
 R1  R3  R4 
R
1  R2 / R1
vO  vO1  vO 2   2 vI 1 
vI 2
R1
1  R3 / R4
vI1
vO1
 1  R2 / R1 R2 
1  1  R2 / R1 R2 
 
 vIcm  
 vId
2  1  R3 / R4 R1 
 1  R3 / R4 R1 
 1  1  R2 / R1 R2   1  R2 / R1 R2 
CMRR  20 log  
  / 
 
 2  1  R3 / R4 R1   1  R3 / R4 R1 
1  1  R2 / R1 R2 
 
Ad  
2  1  R3 / R4 R1 
 1  R2 / R1 R2 
 
Acm  
 1  R3 / R4 R1 
vI2
vO2
The condition for difference amplifier operation: R2 /R1 = R4 /R3  vO = (R2 /R1)(v2  v1)
For simplicity, the resistances can be chosen as: R3 = R1 and R4 = R2
Differential input resistance Rid:
 Differential input resistance: Rid = 2R1
 Large R1 can be used to increase Rid
R2 becomes impractically large to maintain required gain
Gain can be adjusted by changing R1 and R2 simultaneously
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Instrumentation amplifier
Ad 
vO
R  R 
 4 1  2 
vI 2  vI 1 R3  R1 
Differential‐mode gain can be adjusted by tuning R1
Common‐mode gain is zero
Input impedance is infinite
Output impedance is zero
It’s preferable to obtain all the required gain in the 1st stage, leaving the 2nd stage with a gain of one
Exercise 2.15 (Textbook)
Exercise 2.17 (Textbook)
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2.5 Integrators and Differentiators
Inverting configuration with general impedance
R1 and R2 in inverting configuration can be replaced by Z1(s) and Z2(s)
The closed‐loop transfer function: Vo(s) /Vi(s) = Z2(s) /Z1(s)
The transmission magnitude and phase for a sinusoid input can be evaluated by replacing s with j
Inverting integrator
Time domain analysis:
t
vC (t )  VC 
t
1
1 vI (t )
(
)
i
t
dt

V

dt
1
C
C 0
C 0 R
t
vO (t )  vC (t )  
1
vI (t )dt  VC
RC 0
Frequency domain analysis:
Vo ( j )
1
Z
 2 
Vi ( j )
Z1
jRC
1
Vo

Vi RC
 = 90
Also known as Miller integrator
Integrator frequency (int) is the inverse of the integrator time‐constant (RC)  int = 1/RC
The capacitor acts as an open‐circuit at dc ( = 0)  open‐loop configuration at dc (infinite gain)
Any tiny dc in the input could result in output saturation
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The Miller integrator with parallel feedback resistance
To prevent integrator saturation due to infinite dc gain, parallel feedback resistance is included
G (dB)
1
RF C
w (log scale)
1
RC
Vo ( j )
Z ( j )
1
 2
 
Vi ( j )
Z1 ( j )
R / RF  jRC
Closed‐loop gain = 1/(jRF + R/RF)
Closed‐loop gain at dc = RF/R
Closed‐loop gain at high frequency ( >>1/RFC) ≈ 1/ jRC
Corner frequency (3dB frequency) = 1/RFC
The integrator characteristics is no longer ideal
Large resistance RF should be used for the feedback
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The op‐amp differentiator
Time domain analysis
iC
dvI (t )
dt
vO (t )   RC
dvI (t )
dt
Frequency domain analysis
Vo ( j )
Z
  2   jRC
Vi ( j )
Z1
Vo
 RC
Vi
 = 90
Differentiator operation:
Differentiator time‐constant: RC
Gain (= RC) becomes infinite at very high frequencies
High‐frequency noise is magnified (generally avoided in practice)
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The differentiator with series resistance
To prevent magnifying high‐frequency noise, series resistance RF is included
G (dB)
w (log scale)
Vo ( j )
jRC

Vi ( j )
1  jRF C
1
RC
1
RF C
Closed‐loop gain = jRC / (1 + jRFC)
Closed‐loop gain at infinite frequency = R/RF
Closed‐loop gain at low frequency ( << 1/RFC ) ≈  jRC
Corner frequency (3dB frequency) = 1/RFC
The differentiator characteristics is no longer ideal
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Exercise 2: For a Miller integrator with R = 10 k and C = 10 nF, a shunt resistance RF is used to suppress the dc gain. Find the minimum value of RF if a period signal with a period of 0.1 s is applied at the input.
Example 2.4 (Textbook)
Example 2.5 (Textbook)
Exercise 2.18 (Textbook)
Exercise 2.20 (Textbook)
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2.6 DC Imperfections*
Offset voltage
Input offset voltage (VOS) arises as a result of the unavoidable mismatches
The offset voltage and its polarity vary from one op‐amp to another
The analysis can be simplified by using the circuit model with an offset‐free op amp and a voltage source VOS at input terminal
Typical offset voltage is a few mV
Effect of offset voltage for a closed‐loop amplifier
VO  VOS (1  R2 / R1 )
A dc voltage VOS(1+R2/R1) exists at the output at zero input voltage
Input offset voltage is effectively amplified by the closed‐loop gain as the error voltage at output
Some op amps are provided with two additional terminals for offset nulling
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Input bias and offset current
DC bias currents IB1 and IB2 are required for certain types of op amps
Input bias current is defined by IB = (IB1+IB2)/2
Input offset current is defined as IOS = |IB1IB2|
Typical values for op amps that use bipolar transistors are IB = 100 nA and IOS = 10 nA
Effect of input bias current for a closed‐loop amplifiers
Output dc voltage due to input bias current: VO = IB1R2  IBR2
The value of R2 and the closed‐loop gain are limited.
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Effect of input offset voltage on the the inverting integrator
The output voltage is given by
vO  VOS 
V
1 t VOS
dt  VOS  OS t

C 0 R
RC
The output voltage increases with time until the op amp saturates
Effect of input bias current on the inverting integrator
The output voltage is given by
vO   I B 2 R 
I
1 t
I OS dt   I B 2 R  OS t

0
C
C
The output voltage also increases with time until the op amp saturates
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2.7 Effect of Finite Open‐Loop Gain and Bandwidth on Circuit Performance
Practical op‐amp characteristics
Op amp with finite open‐loop gain: A(j) = A0
Op amp with finite open‐loop gain and bandwidth: A(j) = A0 / (1 + j/b)
Frequency response of op amp:
Open‐loop op‐amp
The frequency response of an open‐loop op amp is approximated by STC form: A(j) = A0 /(1+ j/b)
At low frequencies ( <<b), the open‐loop op amp is approximated by |A(jw)| ≈ A0 At high frequencies ( >>b), the open‐loop op amp is approximated by |A(jw)| ≈ A0/b
Unity‐gain bandwidth (ft = t/2) is defined as the frequency at which |A(jt)| ≈ 1  t = A0b
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Inverting configuration using op‐amp with finite open‐loop gain
Closed‐loop gain:
vI  (vO / A0 ) vI  vO / A0

R1
R1
v
v v v / A 
vO   O  i1 R2   O   I O 0  R2
A0
A0 
R1

v
 R2 / R1
G O 
vI 1  (1  R2 / R1 ) / A0
i1 
 Closed‐loop gain approaches the ideal value of R2 /R1 as A0 approaches to infinite
 To minimize the dependence of G on open‐loop gain, we should have A0 >> 1+ R2/R1
Input impedance: Ri 
vI
vI
vI
R1



i1 (vI  vO / A0 ) / R1 (vI  vI G / A0 ) / R1 1  G / A0
Output impedance: Ro  0
Inverting configuration using op amp with finite gain and bandwidth
 R2 / R1
 R2 / R1

1  (1  R2 / R1 ) / A( j ) 1  (1  R2 / R1 ) /A0 /(1  j / b )
 R2 / R1

1  (1  R2 / R1 ) / A0   j (1  R2 / R1 ) / b A0 
G
if A0 >> 1+R2/R1  G ≈ G0 /(1+j/3dB)
where G0 = R2/R1 and 3dB = A0b /(1+R2/R1) ≈ (A0 /|G0|)b
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Exercise 3: Consider an inverting amplifier where the open‐loop gain and 3‐dB bandwidth of the op amp are 10000 and 1 rad/s, respectively. Find the gain and bandwidth of the close‐
loop gain (exact and approximated values) for the following cases: R2/R1 = 1, 100, 200, and 2000.
Exercise 4: An op amp has an open‐loop gain of 80 dB and a 3‐dB bandwidth of 10 rad/s.
(1) The op amp is used in an inverting amplifier with R2/R1 = 100. Find the close‐loop gain at dc and at  = 1000 rad/s.
(2) Two identical inverting amplifiers with R2/R1 = 100 are cascaded. Find the close‐loop gain at dc and at  = 1000 rad/s.
(3) For the cascaded amplifier in (2), find the frequency at which the gain is 3 dB lower than the dc gain.
Exercise 2.26 (Textbook)
Example 2.6 (Textbook)
Exercise 2.27 (Textbook)
Exercise 2.28 (Textbook)
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2.8 Large‐Signal Operation of Op Amps
Output voltage saturation
Rated output voltage (vO,max) specifies the maximum output voltage swing of op amp
Linear amplifier operation (for the required vO < vO,max): vO = (1+R2/R1)vI
Clipped output waveform (for the required vO > vO,max): vO = vO,max
The maximum input swing allowed for output voltage limited case: vI,max = vO,max/ (1+R2/R1)
Output is typically limited by voltage in cases where RL is large
Output current limits
Maximum output current (iO,max) specifies the output current limitation of op amp
Linear amplifier operation (for the required iO < iO,max): vO = (1+R2/R1)vI and iL = vO /RL
Clipped output waveform (for the required iO > iO,max): iL = iO,max iF
The maximum input swing allowed for output current limited case: vI,max = iO,max[RL||(R1+R2)]/(1+R2/R1)
Output is typically limited by current in cases where RL is small
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Slew rate
dv
SR  O max
Slew rate is the maximum rate of change possible at the output: (V/sec) dt
Slew rate may cause non‐linear distortion for large‐signal operation
Input step function
Small‐signal distortion (finite BW)
Large‐signal distortion (SR)
vO (t )  V (1  e t t )
Full‐power bandwidth
Defined as the highest frequency allowed for a unity‐gain buffer with a sinusoidal output at vO,max
vi (t )  Vo sin t  vo (t )  Vo sin t
vO
dvo (t )
 Vo cos t
dt
dv (t )
| o |max  Vo  SR  distortionless
dt
dv (t )
| o |max  Vo  SR  distortion
dt

SR
fM  M 
2 2vO ,max
vO,max
SR
w
wM
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Example 2.7 (Textbook)
Exercise 2.29 (Textbook)
Exercise 2.30 (Textbook)
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