Download a reduced power 6-tap pre-emphasis for 10gb/s

A REDUCED POWER 6-TAP PRE-EMPHASIS FOR 10GB/S BACKPLANE
COMMUNICATIONS
Dezhong Cheng, Bangli Liang, Dianyong Chen, Tad Kwasniewski
Department of Electronics, Carleton University, 1125 Colonel By Driver, Ottawa, ON K1S 5B6, Canada
ABSTRACT
Pre-emphasis is often employed at the transmitter side to
counteract the inter symbol interface (ISI) in high-speed
data communications. Traditional pre-emphasis drivers,
implemented in CML, use one pair of CMOS transistors as
the output stage. To design a pre-emphasis for different
channels requires a wide range of current for the same tap.
The challenge for traditional circuits is how to choose the
sizes for these transistors. To meet this challenge, this paper
presents a lower 6-tap pre-emphasis with several pairs of
transistors at output stage to solve this issue. The simulation
shows the eye diagram for the same channel improved
vertical 8% and horizontal 5%. The pre-emphasis consumes
only 57.7mW with a total of 6 tabs.
transmitter side, arrive at the receiver side at a different
time, which further distorts the received signals. To
counteract the ISI, a pre-emphasis in the transmitter side [1]
or an equalizer in receiver side [2], or both [3], are
employed. Finite impulse response (FIR) circuits
implemented in CML are the most popular circuits in preemphasis. Normally, a pair of CMOS transistors is used for
one tap of a pre-emphasis. If the current of this tap changes
in a wide range for different channels, how to choose the
size of the transistors is a challenge. This paper presents an
improved circuit to meet this challenge. This paper is
organized as follows. Section 2 explains why the size of the
transistors is a big challenge. Section 3 describes FIR preemphasis with proposed pre-emphasis driver. Section 4
compares the simulation results of both circuits. And finally,
section 5 gives the conclusion.
2. SIZING TRANSISTOR PROBLEM
1. INTRODUCTION
Recently, the need to transport high volumes of data from
chip to chip or from board to board through backplanes
while reduced I/O pin counts makes high-speed
serializer/deserializer (SERDES) communication to replace
conventional low-speed parallel bus structure. A typical
topology of a modular platform backplane consists of two
daughter boards where the transceivers are located, and one
backplane that connects the two daughter boards. The
daughter boards and backplane are attached by the
connectors.
Due to the limited bandwidth of the channel, ISI is a
major factor limiting the maximum distance and data rate of
in high speed SERDES communication. ISI is mainly
caused by frequency dependent factors such as attenuation,
phase propagation velocity (or group delay) of the
backplane, and reflections found in interconnects, such as
the connectors, PCB traces, and vias. Frequency dependent
attenuation is mainly caused by the skin effect and dielectric
loss of the backplane, which suppresses high frequency
content of the not-return-zero (NRZ) data stream and makes
the output signal spread beyond one baud period. Frequency
dependent group delay and reflection also make the signals
at different frequencies travel at different speeds through the
channel. Therefore, the signals with different frequency
content that are transmitted at the same time at the
In high speed circuits design, the CMOS transistors are
biased at maximum fT, which gives us the current density
around 0.28mA/µm [4]. Fig. 1 shows the simulation of the
fT for a 10µmx1µm NMOS transistor in 90nm technology.
In order to design a FIR of pre-emphasis for different
channels, the coefficients of the FIR require changing in a
wide range, which results in the wide range current
changing for the same tap. The pre-emphasis driver consists
of several pairs of NMOS transistors and several digitalanalog converter (DAC) current sources depending on the
taps. Fig. 2 shows the traditional one tap of FIR preemphasis driver with a 5-bit digital controlled current
source. The challenge is how to choose the size of the
transistors for a wide current changing range. For example if
the maximum current for the specific tap is 10mA for a
specific channel, but for another channel the maximum
current is 1mA, if we choose size of the transistor to meet
the maximum fT according to the maximum possible
current, which gives us the width of the transistor as 35.7µm
and fT as 129GHz. When the circuit operates for another
channel, the current is 1mA and the current density is
0.028mA/µm, and the resulting fT is 62.6GHz. If the current
change is wider, the fT drops more. Furthermore the actual
fT of the transistors changes according to the gate-source
voltage (Vgs) and the drain-source voltage (Vds). A
reasonable Vgs and Vds may be just 0.3V to 0.6V because the
of the traditional circuit is larger than that of the proposed
circuit (Fig. 4 b and d).
VDD
R
Out+
R
Out-
transistors are stacked vertically and the maximum power
supply voltage is limited. That results in lowing the fT of the
transistors further and limiting the speed of the circuit.
Therefore, for the circuits to operate at 10Gb/s or beyond,
the transistors should be biased around the maximum fT to
obtain better performance.
WxL = 10um/0.1um
150
1b
fT (GHz)
In+
100
Vb C0
M1,2
1a
In-
2b
M3,4
2a
Vb C1
In+
4b
M5,6
4a
Vb C2
2a
1a
4a
In-
Vb C3
8b
M7,8
8a
In+
16b
M9,10
16a
Vb C4
8a
16a
50
Fig. 3 One Tap of Proposed FIR Pre-emphasis Driver
0
-6
10
Cgs (Input High)
-3
Fig. 1 fT Vs. Current Density
(NMOS WxL 10µmx0.1µm, 90nm technology)
1
Vb C1
2
2
Vb C2
45
4
46
45
44
Vb C3
5
10
15
20
5-bit Coefficients
25
42
30
5
a) Cgs (Saturation)
Out+
10
15
20
5-bit Coefficients
25
30
b) Cgs (CutOff)
Cgd (Input High)
Cgd (Input Low)
120
80
100
70
In-
8
Vb C4
8
16
16
Fig. 2 One Tap of Traditional FIR Pre-emphasis Driver with 5bit digital controlled current source
3. PROPOSED FIR PRE-EMPHASIS
The proposed one tap of pre-emphasis driver shown in the
Fig. 3 solves this challenge. In this circuit, the current
source is controlled by a 5-bit digital signal. So current of
each branch is fixed when the control bit is high, or the
current is zero when the control bit is low. So, the
transistors M1 to M10 can be sized to make the current
density around the maximum fT using the current when the
control bit is high.
One benefit of using the proposed circuits is reducing
the input capacitance (Cgs and Cgd) of the pair of transistors.
Fig. 4 shows the Cgs and Cgd (M1 in Fig 2 or M1,4,5,8,9 in
Fig. 3) changing when the 5-bit coefficients change from 1
to 31. Reducing the input capacitance means the transistors
of pre-emphasis driver can turn on and off more quickly.
When the input is high, Cgs and Cgd of the traditional circuit
is larger than those of the proposed circuit (Fig.4 a and c).
When input is low, the Cgs of both circuits is close, and Cgd
Capacitance (fF)
Tranditional Circuit
Proposed Circuit
Capacitance (fF)
M2
4
Tranditional Circuit
Proposed Circuit
47
50
R
Out-
Vb C0
1
55
40
R
M1
48
Tranditional Circuit
Proposed Circuit
43
VDD
In+
Cgs (Input Low)
60
10
Capacitance (fF)
-4
Capacitance (fF)
-5
10
10
Current Density IDS/W (mA/um)
80
60
60
50
Tranditional Circuit
Proposed Circuit
40
5
10
15
20
5-bit Coefficients
25
30
40
5
10
15
20
5-bit Coefficients
25
30
c) Cgd (Saturation)
d) Cgd (CutOff)
Fig. 4 Cgs and Cgd Vs. Coefficients
Another benefit of using the proposed circuits is the
performance current source improved. Fig. 5 shows the
output of the current source of both circuits at different
coefficients (9 and 15) using the 0101… data pattern. From
the Fig. 5, we can see that there is not much difference in
the average of the current source for the two circuits at the
same coefficient, but the traditional circuit has a large
variance (dash line). The reason for this is the transistors in
the proposed circuit turn on and off faster than the
traditional circuit due to the smaller input capacitance Cgs
and Cgd. If the power supply of the circuit is an ideal voltage
source, the current variance would not benefit to the output
(transmitted signals) of the circuit. But in the real world, the
power supply has impedance, and also the trace on the PCB
and the IC package have impedance, the proposed circuit
will have better performance than the traditional circuit. For
example, the bond wire of the IC package has 1nh/mm. If
the bond wire is 2 mm, which is normal for TQFP, the bond
wire has 2nh. The voltage drop of an inductor is given by:
In-
di
dt
∆V = L
E-1
Fig. 6 shows the voltage drop cross the bond wire
(2mm) using the current shown in Fig. 5. The proposed
circuit has only a 0.07V ripple compare to a 0.42V voltage
ripple in the traditional circuit at coefficients 9 without
decoupling capacitors. Of course, in the design, we have
decoupling capacitors, and therefore the ripple will be
reduced.
Output of Current Source (Coeff=9)
Output of Current Source (Coeff=15)
5
4
Data In
8
Clock
6
6.2
6.4
6.6
time ns
6.8
5
7
6
6.2
6.4
6.6
time ns
6.8
7
MATLAB
Optimized
Coefficients
a) Coeff=9
b) Coeff=15
Fig. 5 Output of Current Source at Different Coefficients
0.2
0
0.2
0
-0.2
6.4
6.6
time ns
6.8
-0.2
7
6
6.2
6.4
6.6
time ns
6.8
7
a) Coeff=9
b) Coeff=15
Fig. 6 Voltage Drop at Different Coefficients
Average Relative Error
4. SIMULATION RESULTS
Variance/Mean
5
0.8
Tranditional Circuit
Proposed Circuit
Variance/Mean
4
3
2
1
Tranditional Circuit
Proposed Circuit
0.6
0.4
0.2
0
-1
5
10
15
20
5-bit Coefficients
25
30
0
5
10
15
20
5-bit Coefficients
25
30
a) Relative Error
b) Variance/Mean
Fig. 7 Error and Variance of Output of Current Source
Fig. 8 shows the test bench used to compare the two
circuits. The sizes of the transistor M1, M2 in Fig. 2 are the
sum of sizes of the transistors M1, M4, M5, M8, M9 and
M2, M3, M6, M7, M10 respectively. The simulation results
are shown in Fig. 4 through Fig. 7.
VDD
50
PRBS11
Buf
Channel
UTD
10 GHz
CLK
Absolute
Value of
Coefficients
In order to save power, all DFFs and XORs are
optimized for power consumption according to their loads.
For example, the loads for the DFF are one DFF and one
XOR. So we do not need to design a high fan out, such as
fan out 4. A large fan out means a heavy load and the
circuits need more power. For the same reason, the XOR is
designed only to drive one buffer.
0.4
Voltage (V)
Voltage (V)
0.4
6.2
Sign of
Coefficients
Data Output
Fig. 9 Architecture of Pre-emphasis
0.6
6
Pre_emphasis
Driver
Voltage Cross 2nH (Coeff=15)
Voltage Cross 2nH (Coeff=9)
0.6
-0.4
Pre-Driver
7
6
3
Relative Error (%)
Retiming
Circuit
Value
Current (mA)
Current (mA)
6
9
Sign
7
2
Fig. 9 shows the architecture of the pre-emphasis. It
consists of the retiming circuit, the pre-driver with
coefficient sign control, and the pre-emphasis driver with
coefficient control. The retiming circuit consists of the
DFFs. The sign of coefficients is controlled through the
XOR gate in the pre-diver. The pre-driver also consists of
buffers to drive large CMOS transistors in the pre-emphasis
driver circuit. The absolute value of the coefficients controls
the weight of each tap by controlling the tail current of the
pre-emphasis driver.
Buf
Fig. 8 Test Bench of the Pre-emphasis Driver
50
In order to compare the performance of the proposed preemphasis driver, we designed two 6-tap FIR pre-emphases,
one with a traditional pre-emphasis driver and another with
the proposed pre-emphasis driver in 90nm. Fig. 10 shows
the test bench of these two circuits. To compare the circuits’
performance, two simulations are run both for the traditional
circuit and the proposed circuit. In one simulation uses an
ideal power supply connected directly to the circuits. In
another simulation adds the package between the circuits
and power supply. The package used in the simulation is the
lump parameters model. The model of the package is shown
in the Fig.11. This model does not consider the crosstalk
between the adjacent bond wire, although the crosstalk is
another issue when the data rate is 10Gb/s and beyond. The
channel model is the channel B20, which can be
downloaded from [5]. Fig. 12 shows the eye diagram of the
two circuits with bond wire using the same input data
stream (PRBS11). The simulation results of the two circuits
are listed in the Table 1.
PRBS11
Buf
DataIn
VDD
PreEmphasis
10 GHz
CLK
Buf
Clk
Out+
C00-C05
C10-C15
C20-C25
C30-C35
C40-C45
C50-C55
Coeff
Register
50
50
Channel
Out-
through the JTAG interface. The pre-emphasis with the
proposed circuit improves the eye diagram both vertical and
horizontal (Vertical 5% and Horizontal 8%) without
increasing any cost for 10Gbp/s operation over the channel
B20 backplane. The power dissipation is only 57.5mW at a
1.2V power supply.
Table 2 Power dissipation comparison
Fig. 10 test bench of the pre-emphasis
L2
L1
IC_PAD
C1
C2
C3
SUB
Fig. 11 Lump Parameters Model for IC Package
B20 Rx
0.2
0.2
0.1
0.1
Amplitude
Amplitude
B20 Rx
0
-0.1
-0.2
-100
-0.2
-100
0
Time
50
100
VDD
(V)
4
2
4
3
4
90
.18
.13
1.2/1.0
1.8
1.5
90
70
40.5
180
183.2
95
1.2
Data
Rate
Gb/s
10
6
10
5/10
10
[3]
[6]
[7]
[8]
[9]
This
work
6
90
57.5
1.2
10
6. REFERENCE
0
-0.1
-50
Power
(mW)
L3
PCB
C4
Technology
Taps
[1] C.H Lin, et al. “5 Gb/s Serial Link Transmitter with Pre-emphasis” in
Proc. Conf. on Design Automation , pp 795-800, Jan. 21-24, 2003
-50
0
Time
50
100
a) Tradition Circuit
b) Proposed Circuit
Fig. 12 Eye diagram of the signal at near end
[2] J.F. Bulzacchelli, et al “Power-Efficient Decision-Feedback Equalizers
for Multi-Gb/s CMOS Links” in Proc. Conf. on Radio Frequency
Integrated Circuits, pp 507-510, Jun. 3-5, 2007
Table 1 Comparison of Simulation Result
Traditional
Proposed
Circuit
Circuit
Without Vertical (mV)
105.2
105.1
Package
Horizon (UI)
0.6404
0.6403
With
Vertical (mV)
97.3
105.7
Package
Horizon (UI)
0.6172
0.6453
[3] J.F. Bulzacchelli, et al “A 10-Gb/s 5-Tap DFE/4-TapFFE Transceiver in
90-nm CMOS Technology”, IEEE J. Solid-State Circuits, Vol. 41, pp
2885-2900, 2006
The total current for the 6-tap FIR pre-emphasis is
47.9mA and consumes 57.5mW. The comparison of power
dissipation is listed in the Table 2. From Table 2, we can see
that the power dissipation is lower compared to other
designs. Although the lowest power dissipation is the design
in [6], this work has 4 more taps than that of the design in
[6]
[5] W. Peters, IEEE P802.3ap Task Force Channel Model Material.
http://grouper.ieee.org/groups/802/3/ap/public/channel_model/index.html
5. CONCLUSION
A 6-tap programmable coefficient FIR pre-emphasis has
been implemented in 90nm technology. The tap
coefficients, including the sign are completely
programmable by changing the value of the registers
[4] D.O. Dickson, et, al “The Invariance of Characteristic Current Densities
in Nanoscale MOSFETs and Its Impact on Algorithmic Design
Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed
Building Blocks” IEEE J. Solid-State Circuits, Vol. 41, pp 1830-1845,
2006
[6] C.M. Chu, C.H. Chuang, et al. “A 6Gb/s Serial link transmitter with
pre-emphasis” in Proc. Conf. On VLSI Design, Automation and Test, pp.12, April 25-27, 2007
[7] F. Weiss, D. Kehrer, et al “Transmitter and Receiver circuits for serial
data transmission over lossy copper channels for10Gbps in .13 um CMOS”
in Proc. Conf. On Radio Frequency Integrated Circuits, June 11-13, 2006
[8] C. H. Lin, S.J. Jou, “4/2 PAM Pre-emphasis Transmitter with combined
driver and mux” in Proc. Asian Conference On Solid-State Circuits
Conference. Pp189-192, Nov. 2005
[9] A. Rylyakov and S. Rylov, “A low power 10 Gb/s serial link transmitter
in 90-nm CMOS,” in Proc. Conf. On Compound Semiconductor Integrated
Circuit Symposium. pp. 189–19, Oct. 30 – Nov.2, 2005