Download COMMENTS from Kjell on the TOP 10 most useful equations in the

MY COMMENTS TO THE LIST OF THE TOP 10 MOST USEFUL EQUATIONS
#10
The definition of sheet resistance, sometimes called sheet resistivity, RS=/d, appears strange
to most students at first because of the strange dimension in ohms per square. What kind of
square is that? It is any square resistor with an aspect ratio L/W=1. Since all resistances in
any certain layer in a CMOS technology has the same thickness d, it is a useful quantity. All
you have to do to get the resistance is to multiply the sheet resistivity and the number of
squares, L/W, along the resistor to get the resistance. The longer and narrower the resistor,
the larger its resistance.
R  RS
#9
The MOSFET is a square-law device. Remember that! At least the long-channel devices are.
In todays short-channel devices there are many second-order short-channel effects (SCE)
that must be also considered. But not in this course. Later when you become professional
designers. However, even this basic formula can provide valuable insight into the behaviour
of CMOS inverters, like calculating an approximate switching voltage by making the nchannel and p-channel saturation currents equal. However, do not forget that VGS is negative
for p-channel devices.
I DS 
#8
L

where RS 
W
d
W
2
k´VGS  VT 
L
The dot operator equations. Hm, what to say? It is a mathematical definition. In essence, it
shows that the dot operator can be used to build trees by combining groups of inputs.
Gi: j  Gi:k  Pi:k Gk 1: j
Pi: j  Pi:k  Pk 1: j
#7
Elmore delay formula. These equations show the dominant time constant of a two-stage RCladder. The good thing is that it can be extended as a good approximation for any number of
RC-stages in the ladder. It can be written in two ways, quite easy to remember, actually. You
either multiply each resistance with its downstream capacitance, or you multiply each capacitance with its up-stream resistances; the voltage source at the wire input being the source.
  R1C1   R1  R2  C2
  R1  C1  C2   R2C2
However, do not forget that for obtaining the wire delay, the tao in this formula must be
multiplied by 0.7. And don´t be confused with the FO1 delay of an ideal inverter with no
output capacitance that is also denoted tao=0.7ReffCG. See #1.
#1
Speaking about tau, I will make a jump to the most important of all equations in the course,
the equation for tau, the inverter process constant. As I just wrote, this is the FO1 delay of an
ideal inverter with negligible parasitic output capacitance! In our 65 nm process this time
constant is 5 ps! Ideally, since we neglect any capacitance contributions to the gate
capacitance that are not scalable with the channel width, all inverters have the same FO1
delay independent of their sizes or driving capabilities X. At least in our ideal world!
More important, any propagation delay that appears in this course is some kind of multiple
of this time constant. Very often is an integer multiple.
#3
All delays are multiples of the process time constant tau using d, the relative delay:
d   p  f ,
where p is the parasitic delay, and f is the fanout delay!
#6
Now, we must learn how to calculate the parasitic delay for any logic gate and collect our
data in a table for later use.
p
Reff gate Coutgate
Reffinv Cininv
To calculate p, we size the MOSFETs so that all pull-up and pull-down paths obtain the
same resistance as the effective resistance of our reference inverter. Then we just count the
number of CD capacitances at the drain output of the logic gate and divide by the 3 unit gate
caps of the reference inverter. Sometimes we also must remember that CD and CG of the
inverter are not equal, i.e. pinv≠1. I have found this way of calculating p much easier than to
try to make all input caps of the gate equal to the 3 unit gate caps of the inverter, and then
trying to find the resistance ratios. Finally, don´t forget that p is a ratio of two RC products.
#5
However, the electrical effort is just a capacitance ratio!
h
#4
CLOADgate
Cingate
When determining the logical effort g of a gate we use the same procedure as for determining the parasitic delay! Both are ratios between two RC products. Say that we want to
determine g and p of an m-input NAND-gate. First, we make a simplified circuit schematic,
like this in its simplest form where the MOSFETs are illustrated by hastily drawn circles:
Once g and p are determined we can rescale the logic gate to any size we want! It is complicated, but can be done. Shown below are the X1 and X2 sizes of a 3-input NAND gate. The
X1 NAND3 gate has the same input capacitance as the X1 reference inverter, i.e. 3 cap units.
The X2 NAND3 gate has twice that input capacitance, i.e. 6 cap units. For the RC products
to remain 5 (since g=5/3), the corresponding resistances are 5/3 and 5/6, respectively.
Here are the tables from the textbook with some logical efforts and parasitic delays listed.
#2.
The dynamic power dissipation P is given by
2
Pdyn   fCVDD
Reducing the supply voltage from the 5 V of the sixties and early seventies to the 1 V of
today means a power reduction of a factor 25! Even going from 1.2 V to 1.0 V is a large
saving. On the other hand, we have come a long way on frequency from the 25 MHz of the
eighties to the 4 GHz of today. That is a factor of 40. Chips are also larger today, therefore
they have more capacitance. No wonder heat dissipation has become a problem. Obviously,
multicores do not help, when more and more functionality is added. So low-power design is
important, as is thermal management, i.e. ways of keeping chips cool both by regulating
frequency f and supply voltage VDD. A chip that dissipates 10 W or more at a supply
voltage of 1 V obviously needs a lot of current flowing into the package and distributed
across the chip. Also 10 W at a frequency of 1 GHz and 1 V supply voltage indicates an
effective capacitance of 10 nF being switched continously. If I am doing my math correctly,
this seems to be one million 10 fF gates operating at 1 GHz.
Runners up?
In her lecture, when she presented the ten most important equations in the course, Lena Peterson asked
for runners up, or ”bubblare” as we say in Swedish if we listen to Svensktoppen on the radio. Did not
think of it then, but now I have one proposal concerning wire repeaters to submit! Please, have a look:
#11
Under what circumstances are we to consider inserting wire repeaters to make wire segments
shorter, an important topic since wire delay increases with the wire length L2. This is the
topic to be considered in the proposed runner-up equation. So, here comes my proposed
equation for the optimal number of segments
mopt 
1
2
RW CW
RC
where RWCW is the RC-product of the wire with resistance RW and capacitance CW, and RC is
the RC-product of the inverter with effective resistance R and input capacitance C. If, for
example, RWCW=36RC, then we know that three wire segments is the optimal number of
segments (and an odd number of segments does not invert the signal at the wire output).
When sizing the repeaters for minimum propagation delay, all four delay contributions from
the Elmore delay model become equal, yielding a total delay of
t pdmin  0.7  4  RW CW  RC
,
where the square root represents the geometric mean of the two RC products. With the
numbers given above, the minimum delay becomes 84 ps. Without the two extra repeaters,
the wire delay would have been 112 ps1.
1
tpd=tpdmin/2+0.7*5 ps*(2+ RWCW/2RC)=112 ps.