Download Planar Interconnection Technology for LSI Fabrication Utilizing Lift

Planar Interconnection Technology for LSI Fabrication Utilizing
Lift-off Process
Kohei Ehara, Takashi Morimoto, Susumu Murarnoto, and Seitaro Matsuo
Nippon Telegraph and Telephone Public Corporation,Atsugi Electrical Communication Laboratory, 1839, Ono,Atsugi-shi,
Kanagawa 243-01, Japan
ABSTRACT
A surface planarization process for multilevel metallization structure is proposed for higher packing density and
higher yields in fabricating LSI's. The technique makes use of the ECR plasma deposition method and a lift-off process.
The deposition method is suited for the lift-off process, because of its directional deposition properties and low temperature deposition. The surface planarization process yields a flat surface. Fine patterns in the upper layer are obtained.
The potential for using this technology for manufacturing the MOS LSI is verified by the good yield and fine A1 patterns for 1 kbyte associative memory fabricated with this process.
For higher packing density in LSI's, a multilevel metallization structure must be improved by miniaturization
and by increasing the n u m b e r of layers. In microfabrication technology, lithographic techniques and dry etching
techniques have contributed to the rapid progress in reduction of the lateral dimensions for the patterns. In
contrast to such rapid advancement, the thickness of the
insulating and conducting films for multilevel interconnection cannot be appreciably reduced, because of wiring
resistance and parasitic capacitance. Thus, the LSI surface step height increases compared with the lateral dimensions of the pattern with increasing LSI packing density. In this case, the surface step causes poor step
coverage of a deposited thin film, short circuiting, or
breakage in conducting lines. In addition, the pattern size
uniformity in the lithographic process becomes worse.
In order to solve these problems, planar technology for
the interconnection layer has been used. For example,
there are several planarization techniques, such as anodic
oxidation (1), lift-off (2-4), glass flow (5), surface leveling
(6), polymer film coating (7), and etch back employing
RIE (8). Anodic oxidation can form completely planar interconnection metallization (1). In this process, the unanodized metal remains in the spaces between the lines, and
a reduction in cross-sectional area for the metal line occurs. Thus, it seems that these factors interfere with
miniaturizing the LSI's pattern, because it is difficult to
further decrease these factors. The lift-off process for surface planarization utilizes A1 evaporation on the
photoresist without heating the substrate (2, 3). Thus, A1
film has a poor step coverage at the sidewall of the
through-hole contact or at the surface step of the underlying film pattern edge. Furthermore, the MOS LSI fabrication process utilizes CVD film deposition or H2 heattreatment at about 400~ substrate temperature. In these
heating processes, hillocks will grow easily for A1 film
evaporated (9). There is another lift-off process, which can
obtain fine-featured smoothly tapered metallization patterns by using a polyimide as the lift-off layer (4). In this
process, the remaining surface steps interfere, increasing
the n u m b e r of metallization's levels. The P-glass flow
process, which makes the surface smooth (5), requires
1000~ to 1200~ heat-treatment and still leaves the surface
step. The surface leveling process makes use of organic
material flow and its etching, using conditions that etch
the photoresist and the underlying P-glass at nearly the
same rate (6). Although this process also can obtain a
smoothed surface without high temperature heat-treatment, the surface step still remains. There is another process, utilizing a polyimide as an interlevel dielectric (7).
Although the film is highly resistant to heat, it seems to
be difficult to obtain a uniform miniaturization because
of film-thickness variations. The etch-back process, employing RIE, can be used to obtain a smoothed surface
(8). In this process also the surface step still remains.
There are other planar technologies which have the potential for the application to planar interconnection. For
example, there is a technology which employs a low temperature photo-CVD oxide (10) in conjunction with a liftoff. Using this technology, the fabrication of a fully recessed field isolation (11) had been attempted.
This paper introduces a new planar technology for
multilevel metallization with a high packing density (12).
In this process, surface planarization is carried out employing the lift-off technique. This lift-off utilizes electron
cyclotron resonance (ECR) plasma deposition, which has
such features as high directionality, high quality, and low
temperature deposition (13). Thus, in this lift-off process,
the processing ease depends mainly on the deposited
film, and not on the stencil. Furthermore, this lift-off utilizes anisotropic dry etching for pattern formation. Therefore, it is suitable for miniaturization and multilevel formation of metallization. In the following sections, a fundamental planar process, ECR plasma deposited film,
lift-off yield, and the application to LSI fabrication are
described.
Key words: multilayer metallization, planar interconnection,
lift-off, ECR plasma deposition.
~ Step D
Manufacturing Process
The fundamental process steps for making planar interconnections are shown in Fig. 1. Details of these steps are
as follows.
Step A . ~ F i r s t A1 layer etching with a resist mask using
a dry etching technique. AI(Si) film 0.6 u m thick as a
first A1 layer is deposited by using a magnetron sputter
evaporation technique. The substrate t em p er atur e is
about 300~ A projection printing technology is used for
the photolithography. The photoresist layer is 1.5 um
thick, and the m i n i m u m pattern size is a 2 ~m lines and
spaces. First A1 interconnection patterns are etched away
in a parallel plate plasma etcher using 0.25 torr CC14 gas.
All these methods are generally used in the metal interconnection formation.
Step B.--Silicon dioxide (SIO2) deposition, using the
ECR plasma deposition method. The SiO2 film thickness
deposited by the ECR plasma deposition method is the
same as in Step A.
Step C.--Sidewall deposited film etching with wet
etchant.
Step D.--SiO2 film lift-off from the resist by resist
removing. More details for steps C and D are indicated in
Table I. A m m o n i u m fluoride/hydrofluoric acid/ethylene
glycol solutions shown in Table I are used to make the
SiO2 and A1 etching rate ratio large (14). The lift-off process itself is completed in process 3 of Step D in Table I.
But, in case the lifted-off material adheres on the wafer
surface again, a high pressure water method is employed,
which can remove the adhesive material without giving
Table I. Detail processconditionsof Step C and Step D
1. Slight etching, ammonium fluoride/HF/
|
ethylene glycol solutions, 5 rain
es~
2. Deionized water rinse, 10 rain
3. Ultrasonic cleaning in acetone, 10 rain x 2 tim
4. High pressure water cleaning, 1200 psi, 90s
5. J-100 cleaning (90~176
trichlorethylene boiling
Step C
J
419
Downloaded on 2016-02-18 to IP 130.203.136.75 address. Redistribution subject to ECS terms of use (see ecsdl.org/site/terms_use) unless CC License in place (see abstract).
420
February 1984
J. Electrochem. Soc.: S O L I D - S T A T E S C I E N C E A N D T E C H N O L O G Y
SlOt
[A|
~ ~
Fig. 1. The lift-off process. A:
parallel plate plasma etching. Bi
ECR plasma deposition. C: slight
etching. D: lift-off. E: interlevel
insulator and second AI layer
formation.
4,
[D]
jECR SiO~
[B}
r / / / / / / / / / / / / , , , # 2 r ~ J hi
[El
~
C
V
D
SiOl
4,
[c}
any scratch on the wafer surface. Since the strength of the
adhesion is too weak to be removed by the high pressure
water method, the removal is completed perfectly. 1200
psi water pressure is used.
Step E.--Filling the remaining groove by interlevel insulator deposition. Second AI layer formation on the substrate. CVD SiO2 0.8 t~m thick is deposited at 400~ substrate temperature. The second A1 interconnection 1.0 tLm
thick is formed by using the above-mentioned method.
Features of this process are as follows. After a pattern
having a steep side wall is formed by using parallel plate
plasma etching, the sunken place formed by the etching
is buried using the ECR plasma deposition. This process
is suitable for miniaturization, because it utilizes anisotropic characteristics both in etching method and deposition method. Next, the processes added to the conventional LSI process are only Steps B, C, and D. With regard
to photolithography, generally used process conditions
are utilized. Thus, this process can be applied easily to
the conventional process by adding Steps B, C, and D.
ECR Plasma Deposited Film Properties
Ttie ECR plasma deposition apparatus allows the performance of high quality thin film deposition at room
temperature without the need for thermal reaction (13). It
does this by enhancing the plasma excitation efficiency
and the b o m b a r d m e n t effect of ions with moderate energies on the deposition reactions through using a microwave ECR plasma generation and a plasma extraction by
a divergent magnetic field method. SiO~ film can be deposited by introducing O~ and Sill4 into the plasma and
specimen chamber, respectively. The deposition rate increases from about 200 to 400 A/rain at the gas flow rates
of O~ 10 cm3/min and SiI-I4 10 cm3/min in the microwave
power from 50 to 300W. Table II shows the fundamental
characteristics of ECR SiO2 deposition used in this study.
Step coverage.--Figure 2 shows step height and tapered
angle dependence on deposited SiO2 thickness. CVD SiO2
is also shown for comparison. The substrate is silicon,
which is etched away to form lines and spaces 1 ~m deep.
For CVD SiO2, the trench becomes filled when the deposited film thickness becomes greater than 2 tLm. However, for ECR SiO2, the trench is not filled yet to the same
deposited thickness. The tapered angle for ECR SiO2 is
constant, even when the ECR SiO2 thickness is 2 /~m,
while that for CVD SiO2 increases after decreasing. For
CVD SiO2, with increasing deposited film thickness, the
trench is filled when the tapered angle starts increasing.
In this way, in the ECR plasma deposition method, the
deposited film surface keeps the substrate shape. Film
thickness deposited on the sidewall is about a third of
that deposited on the fiat surface. The reason that the
o , 9 ECR SiOz
,9 CVD Si02
E
- 9O
0
A
O
v
Fig. 2. Step height and tapered
angle dependence on depositedSiO= thickness.
a 1.0( L
F-1(.9
H
A
,o!,
W
I
Q_ 0.5
W
F-
\
-8
\
60-~
\
\
\
,
i,i
d
'"
\\
0(--,,..>~'"
r~T"-~__0__,5
~
v0
~" " " / ~
1.0
1.5
2.0
30Z
0
DEPOSITED SiOz THICKNESS L (pm)
Downloaded on 2016-02-18 to IP 130.203.136.75 address. Redistribution subject to ECS terms of use (see ecsdl.org/site/terms_use) unless CC License in place (see abstract).
Vol. 131, No. 2
LSI FABRICATION
421
Table II. Fundamental characteristics of ECR plasma deposited film
Reaction gases
Microwave power
Pressure
Temperature
Deposition rate
Etching rate by BHF* (25~
flat surface
sidewall
Refractive index
~ SitL (pure)
t O2
100W
2 • 10-4 tort
40~176
260 A]min
10 cmS/min
10 cm~/min
590 AJminr
> - 5 ~rn/min
1.45-1.47
*(NI~F 40 weight percent):(HF 50 volume percent) = 10:1 (volume
ratio).
tReference data; thermal oxide (wet 1100~ 700 gJmin.
step coverage of the ECR SiO2 becomes a characteristic
shape (as mentioned above) is the high directionality of
the ECR plasma deposition. The directionality is considered to be produced by the following mechanism. After
ions are extracted from the plasma chamber by a magnetic field, they are accelerated towards the substrate by
the electric field in the plasma stream. In this process,
these ions have no collision for the other gas molecules
because of the low gas pressure (mean free path is 20 - 30
cm). In addition, the neutral species having no
directionality scarcely deposit on the specimen (13).
Film etching rate and other properties.--The etching
rate for the ECR SiO2 deposited on the flat surface was
e x a m i n e d using buffered solution containing 10% HF as a
function of the solution temperature (10~ - 35~ In this
temperature range, the etching rates for the ECR SiO~ are
almost the same as those for the thermally grown silicon
dioxide film which was etched simultaneously. The refractive index measured by ellipsometry is almost constant at values from 1.45 to 1.47 in wide range of microwave power. In the infrared absorption spectrum for the
SiO~ film deposited at 100W microwave power, the Si-O
bond peak is clearly observed at 1065 cm -1 wave number,
but no Si-H bond peak is observed. F r o m these results, it
is clear that the SiO2 film deposited on the flat surface
has a dense structure. This is because the substrate is
bombarded by the ions having a energy (-20 eV) suitable
for the deposition reaction. In addition, hydrogen or other
impurities are difficult to contain in the film during its
growth because of the low gas pressure (13).
Figure 3 is an SEM micrograph of a cross-sectional
view, before etching and after etching. During etching
with HF, the film on the sidewall is removed, while the
film on the flat surface is shallowly etched. As a result,
the structure (Step C) shown in Fig. 1 is obtained. Figure
4 shows the change in the cross-sectional view with etching time. The sidewall-deposited film is already removed
after 0.2 rain. Since the etching rate of the sidewall-
Fig. 3. SEM micrograph showing the cross-sectional view change ~n
step coverage by slight etching
deposited film is markedly large in the wet etchant containing HF, the exact value of the etching rate in the
etchant cannot be obtained. However, from the experimental results shown in Fig. 4, the value is roughly estimated to be more than a hundred times that of the flatsurface-deposited film. The differential etch rates for the
ECR SiO~ on the flat surface and the sidewall are explained as follows. Since there is no b o m b a r d m e n t of ions
on the sidewall, the deposition reaction at the sidewall is
not enough; it allows hydrogen and poor molecule bonds
to remain in the film: As a result, a loose structure film is
deposited on the sidewall. In spite of that, a dense structure film is deposited on the flat surface because of the
ion b o m b a r d m e n t (13). Space d, shown in the crosssectional view, increases gradually with increasing etching time. The space d increasing rate is almost the same
as the etching rate for the flat-surface-deposited film.
The tapered angle does not change, even if the etching
time increases. The tapered angle is determined by the ratio of the thickness between the sidewall-deposited film
and the flat-surface-deposited film. F r o m the tapered angle shown in Fig. 4 (-71~ the ratio is about 1:3.
Effect of fiatband voltage and mobile ions.--Figure 5
shows the flatband voltage dependence on the SiO2
thickness. With regard to MOS diode fabrication using
ECR plasma deposition, the sample has three layers,
namely, from the silicon surface, the thermal oxide, the
ECR SiO2, and A1 gate electrode. For comparison, the
thermal oxide flatband voltage is also shown. After oxidation or ECR plasma deposition, no heat-treatment is
made. The A1 electrode is deposited at room temperature
by the heat-resistance method in order to prevent other
effects on the MOS diode. In this result, the fixed charge
density for MOS diode using ECR SiO2 is less than that
using wet SiO2 (15). It is considered that this difference is
due to the fact that the dry SiO2 is formed between the
0.51HF(50
~):H 190 Be oQ
04L"3:'~176
Jso
0.2I
-
ll
;
~
o$
i
Fig. 4. Change in cross section
with etching time.
AfterEtching
,b4o
ETCHING TIME(min)
Downloaded on 2016-02-18 to IP 130.203.136.75 address. Redistribution subject to ECS terms of use (see ecsdl.org/site/terms_use) unless CC License in place (see abstract).
---
0
DRY 0~(500s
+ECR Si02
Wr/~
g
"'~-~
"~
a
U.
F e b r u a r y 1984
J. Electrochem. Soc.: S O L I D - S T A T E S C I E N C E A N D T E C H N O L O G Y
422
WET02
I
0
0.1
I
"''"I"""-
I
0.2
I
I
0.3
OXIDE THICKNESS
I
I
0.4
(pro)
Fig. 5. Flotband voltage shift as a function of oxide thickness
ECR SiO2 and the silicon surface for the MOS diode using
the ECR SiO2. Because both flatband voltages are almost
the same level, no damage is introduced to the fixed
charge density by the ECR plasma deposition method.
Furthermore, the mobile ion density for the ECR SiO2 is
evaluated by using the above-mentioned MOS diode in
the TVS method (16). The mobile ion density is less than
the detectable m i n i m u m value (about 5 x 109 cm-2). Thus,
it is suggested that no mobile ion contamination is introduced by the ECR plasma deposition method. In this
way, with regard to fixed charge density and mobile ions,
the ECR plasma deposition has no problems in MOS LSI
fabrication.
Lift-off Yield and Surface Flatness
In our lift-off technique, lift-off yield and surface
flatness depend on many factors, such as stencil shape,
the slight etching a m o u n t before lift-off, ECR SiO, thickness, etc. Here, among these factors, the A1 layer and ECR
SiO2 thicknesses are both fixed at 0.6 ~m. Figure 6 shows
the dependence of the lift-off yield or the surface flatness
on the slight etching a m o u n t before lift-off. The interlevel
insulator thickness is 0.8 ~m. The yield is evaluated by inspection of the wafer surface using an optical microscope.
A good evaluation corresponds to the wafer having no
lift-off remainder. For the case where the slight etching
a m o u n t is small, lift-off yield for the line patterns (2 ~m
wide) is completed easily, but the lift-off for the square
patterns (9 ~m 2) is not completed. The incompleteness of
the latter is caused by the photoresist edge shape, which
tapered angle is small in the four edges of the square pattern. In this way, the optimum condition for the slight
etching amount depends on the photoresist shape in details. Thus, when the tapered angle of the photoresist is
small, as mentioned above, by increasing the slight etching amount, the good yield of the lift-off is obtained in
good reproducibility, as shown in Fig. 6. However, the
greater the slight etching a m o u n t is, the worse surface
flatness the process offers. With increasing the slight
etching amount, bottom width B and step height D,
which are shown in thecross-sectional view in Fig. 6, increase gradually. Then, both B and D increase rapidly, as
shown in Fig. 6. Thus, taking the lift-off yield and the surface flatness into account, in the present case mentioned
above, the slight etching a m o u n t is appropriate in the
0.05-0.10 ~m range.
Figure 7 shows surface flatness dependence on
interlevel insulator thickness. A cross-sectional view of
the sample structure is shown in the figure. The slight
etching a m o u n t before lift-off is about 0.05 ~m. After the
lift-off process, B defined for the remaining groove
shown in Fig. 6 is nearly zero. Width W decreases gradually with increasing interlevel insulator thickness. Step
height D diminishes rapidly and becomes less than 0.15
~m when interlevel insulator thickness increases. The remaining groove is filled easily, and the planarized surface
is obtained by depositing the interlevel insulator used in
the conventional process. An SEM micrograph of a crosssectional view of this planarized structure is shown in
Fig. 8. The buried first A1 line is 2 ~m wide. The CVD
SiO2 used as the interlevel insulator is 0.8 ~m thick. On this
planarized structure, a second A1 layer is formed.
LSI Fabrication
Test element group fabrication.--Before this technology
was a p p l i e d to LSI fabrication, it was evaluated by applying to a test element group (TEG), which is designed
for evaluating the 2 ~m rule MOS technology (17). This
TEG contains a n u m b e r of patterns for LSI elements,
such as e n h a n c e m e n t MOS FET, depletion MOS FET, p-n
diode, and multilevel metallization. In most of these characteristics, there is no specific characteristic difference
between the element applied by the present technology
and a conventional technology. However, for the twolevel AI interconnection, resistance and deviations in the
second A1 wiring are different from those in conventional
interconnection. Figure 9 shows the experimental values
for the second A1 wiring, under which the first A1 wiring
level is planarized by using the present technology. For
comparison, the experimental values for a conventional
structure are also shown. These sample structures are
drawn in the figure. There are 2006 cross points between
the first A1 line and the second A1 line. Yield for the second A1 line is 97-100%. The experimental values for the
second A1 wiring resistance for the planarized structure
can be combined to form a straight line. This line can be
o
0
"
0.05
0.10
0.15
0.20
AMOUNT OF SLIGHT ETCHING (jJm)
Fig. 6. Step height and bottom width dependence on slight etching
amount,
1
i
0.2
o14
THICKNESS
L
0.6
J
L
0.8
L(pm)
Fig. 7. Surface flatness dependence on interlevel insulator deposited
thickness.
Downloaded on 2016-02-18 to IP 130.203.136.75 address. Redistribution subject to ECS terms of use (see ecsdl.org/site/terms_use) unless CC License in place (see abstract).
Vol. 131, No. 2
LSI FABRICATION
423
Table III. Layout rules, dimensions, numbers, and length for the AI twolevel interconnections
First A1 layer
Minimum width
Minimum space
Thickness
Number of interconaections
Total wiring length
Number of through holes
Through hole size
Fig. 8. SEM micrograph of buried AI line. Cross-sectional view
E
.,C
...,~400
bJ
',.)
Z
~
2 n d AI
t st At
CONVENTIONAL
3oo
STRUCTURE
l
1.
-(''"~
"""
/
w
~ 200
Z
2nd A I - - ' ~ . / / 1
/~
121
Z
~
C
I
I
I0
20
30
2ND AI WIRING LENGTH(mrn)
Fig. 9. Second AI wiring resistance comparison. Second AI line width
is 4 p.m.
extrapolated to the origin. The straight line, which combines the experimental values for the conventional structure, cannot be extrapolated to the origin. These two
straight lines are parallel, and difference AR in the figure
is the resistance caused by the surface steps of the first
A1 layer. Thus, the second A1 line resistance for the
planarized structure is less than that for the conventional
structure. As can be seen in the same figure, resistance
deviations are also caused by the uoderlying layer surface
flatness.
MOS LSI fabrication.--Evaluation procedure.--Logic
LSI's require complicated connections and large areas for
the metal interconnections. Thus, the problem of the interconnections has a great effect on the logic LSI's yield.
The importance of the problem becomes larger as the
LSI's change into VLSI's. In this study, a 1 kbyte associative m e m o r y (18) which has a two-level A1 interconnection is regarded as TEG for the evaluation of the LSI
interconnection. Since the importance of the interconnection fabrication is great in this memory, it is suitable for
evaluation of the present technology. As an evaluation
procedure for the effectiveness of the present technology,
the comparison between the conventional technology and
the present technology was carried out in the LSI fabrication process and function testing. The wafers applied to
the above technologies were fabricated in the same lot except the planarization of the first A1 interconnection. The
m e m o r y contains about 34,000 MOS transistors. Chip size
is 4.1 m m x 4.95 ram. The 2 izm n-channel E/D MOS process is used. Table III shows the interconnection scale,
such as layout rules, dimensions, numbers, and length for
the interconnection in the region where cell areas are
arranged.
Evaluation results. First, observation results about LSIs'
first A1 interconnection fabrication are explained. In the
3.0 #m
2.0 Izm
0.6 tzm
7550
777 mm
41,500
2/~m 2
Second A1 layer
5.0/zm
3.0/zm
1.0 ~m
162
456 mm
15,000
3 ~m ~
present technology, a planarization process is added to
the conventional process after etching the first A1. In this
case, in spite of the various surface steps in the actual LSI
surface, the reason that the present technology is successfully completed is as follows. The factors causing the surface steps, when the first A1 layer is etched away and the
photoresist on it is not removed yet, are local oxidation of
silicon (LOCOS), poly-Si, first through hole, and the first
A1 line. In this structure, the LOCOS surface step is
smooth. The poly-Si surface step becomes smooth, because the glass flow process is carried out for the P S G
film covering the poly-Si. Furthermore, steep steps at the
first through hole for the contact between the first A1
and the diffused layer of Si substrate or between the first
A1 and the poly-Si gate electrodes are filled by the
photoresist coated on the first A1 layer. Thus, there are
steep steps only at the edges of the first A1 interconnection pattern and the photoresist on it. Consequently, the
present technology can be applied to the first A1 pattern
without changing the conventional process, by only
adding a few new processes. In the slight etching before
the lift-off, the wet etchant mentioned in Table I scarcely
attacks the A1 layer and has an appropriate etching rate
for the slight etching of SiO2. Figure 10 shows the LSI
surface after the slight etching mentioned above. Only the
sidewall of the first A1 line and photoresist appear. Surface steps, except for the first A1 line, are the ones caused
by LOCOS and poly-Si gate electrode. It is suggested that
this structure is very suitable for the lift-off.
Next, the observation results regarding LSI's second A1
interconnection fabrication is explained. The Ibresent
technology is different from the conventional technology
in the condition of exposure and etching, but the process
steps of both technologies are the same. In the conventional technology, since there are surface steps on the wafer surface, photolithography requires a slight overexposure time in order to prevent short-circuiting of the A1
lines. Thus, the breakage in the Al lines is apt to occur on
the upper part at the surface step. In addition, in the case
that the interlevel insulator sidewall on the first A1 line is
almost vertical, short circuiting is apt to occur. In the
present technology, breakage or short-circuiting rarely
occurs, because the substrate surface is fiat. In this case,
since the small surface depression (< 0.15 t~m) after the
interlevel insulator deposition (see above) is completely
filled by the second Al film, an appropriate exposure
condition, which is almost the same as one for the fiat
surface, can be applied in order to offer correct lines and
spaces. In addition, it is easy to observe the photoresist
pattern of the Al lines by the optical microscope, because
the underlying layer surface is fiat. Figure I0 shows an
SEM micrograph of this LSI surface after fabricating the
second A1 interconnection. This is the same place as that
shown in Fig. 10. Since, the first A1 line is fully
planarized, the steps caused by the first A1 line are not
shown in the picture. The steps by field isolation and
gate electrode are shown.
In this LSI, in order to connect directly the second A1
interconnection to the poly-Si gate electrodes or Sidiffused layer, a buffered metallization, formed by the
first A1 layer (5 /~m 2) has been used under the second AI
layer (17). By using this buffered metallization, it is easy
to connect an interconnection with another one lying in a
different layer without a specific fabrication process. An
SEM micrograph of the through hole where buffered metallization is used is shown in Fig. 11. The conventional
through hole is shown in Fig. 11. For the first A1 layer's
planarization, no surface step caused by the buffered met-
Downloaded on 2016-02-18 to IP 130.203.136.75 address. Redistribution subject to ECS terms of use (see ecsdl.org/site/terms_use) unless CC License in place (see abstract).
424
J. Electrochem. Soc.: S O L I D - S T A T E S C I E N C E A N D T E C H N O L O G Y
F e b r u a r y 1984
ing layer surface's flatness. The technology is applied to
the first metallization of the 1 kbyte associative memory,
in order to verify its potential for use in MOS LSI fabrication. Since the steep steps are only at the edge of the first
A1 interconnections, the present technology can be applied to a conventional LSI fabrication process without
introducing any serious changes in the process condition.
However, several additional processes, such as ECR
plasma deposition, slight etching, and lift-off, are introduced to the two-level interconnection fabrication.
Finally, it has been shown that this technology offers a
great advantage for LSI fabrication, because it leads to a
good yield and fine A1 interconnections are easily
obtained.
Fig. 10. SEM micrograph of application to LSI fabrication
Acknowledgments
The authors wish to thank Dr. E. Arai, S. Nakayama, H.
Ikawa, and Dr. T. Kitayama for their direction and encouragement. The authors also wish to thank M. Kiuchi
for his helpful assistance. The devices were fabricated by
the staff members of the High Density Integration Section, the Patterning Technology Section, and the
Microfabrication Systems Section at Atsugi Electrical
Communication Laboratory, NTT.
Manuscript submitted Feb. 22, 1983; revised manuscript
received Sept. 27, 1983.
Fig. 11. SEM micrograph of through hole contact between second AI
layer, and the diffused silicon layer using a buffered metollization of
first AI layer.
allization is observed u n d e r the second AI line at the
through hole, while a large surface step is observed in the
conventional through hole. In the usual LSI fabrication
process this structure is not used because it decreases the
LSI yield. In the present technology, since the buffered
metallization is planarized, the good yield is obtained.
The wafers applied to the present technology and the
wafers applied to the conventional technology, which
were fabricated in the same lot, were compared by testing
16 function patterns. In the good chip n u m b e r s passing
the etch test pattern or all test patterns, the wafers applied to the present technology have a better yield than
the conventional one. As a result, it was shown that the
present planar technology offers a great advantage for
LSI fabrication.
Conclusion
Planar interconnection technology, utilizing a lift-off
process, which makes use of the ECR plasma deposition
method, is presented. The deposition method features
high directionality, high quality, and low temperature
deposition. These features are suitable for the lift-off process. By using these features, the lift-off is easily completed after etching the sidewall-deposited film on the A1
line and the resist film. The remaining groove, which is
formed after the lift-off, is completely filled with the
interlevel insulator deposition on the substrate. The surface step after planarization is less than 0.15 t~m. The SiO2
etching a m o u n t for the sidewall-deposited film is appropriate in the 0.05-0.10 tLm range, taking the surface
flatness and the lift-off yield into account.
The present technology has no specific effect on the
characteristics of LSI elements, such as a MOS FET.
However, the resistance and the deviations in the upper
metal interconnections decrease, because of the underly-
Nippon Telegraph and Telephone Public Corporation
assisted in meeting the publication costs of this article.
REFERENCES
1. G. C. Schwartz and V. Platter, This Journal, 122, 1508
(1975).
2. H. Mutoh, Y. Mizokami, H. Matsui, S. Hagiwara, and
M. Ino, ibid., 122, 987 (1975).
3. B. M. Welch, Y. Shen, R. Zucca, R. C. Eden, and S. I.
Long, IEEE Trans. Electron Devices, ed-27, 1116
(1980).
4. Y. Homma, H. Nozawa, and S. Harada, ibid., ed-28,
552 (1981).
5. W. E. Armstrong and D. L. Tolliver, This Journal, 121,
307 (1974).
6. A. C. Adams and C. D. Capio, ibid., 128, 423 (1981).
7. K. Mukai, A. Saiki, K. Yamamaka, S. Harada, and S.
Shoji, IEEE J. Solid-State Circuits, so-13, 462 (1978).
8. H. Hazuki, T. Moriya, and M. Kashiwagi, Paper presented at the 1 9 8 2 Symposium on VLSI
Technology.
9. C. J. Santro and D. L. Tolliver, Proc. IEEE, 59, 1403
(1971).
10. J. W. Peters, IEDM Digest, p. 240 (1981).
11. J. Y. Chen, R. C. Henderson, J. T. Hall, and E. W. Yee,
ibid., p.233 (1982).
12. K. Ehara, T. Morimoto, S. Muramoto, T. Hosoya, and
S. Matsuo, Paper presented at the 1982 Symposium
on VLSI Technology.
13. S. Matsuo and M. Kiuchi, in "VLSI Science and Technology," C. J. Dell'Oca and W. M. Bullis, Editors, p.
79, The Electrochemical Society Softbound Proceedings Series, Pennington, NJ (1982).
14. T. A. Shankoff, C. C. Chang, and S. E. Hasszo, This
Journal, 125, 467 (1978).
15. E. H. Nicollian and J. R. Brews "MOS Physics and
Technology," p. 469 Wiley-Interscience, New York
(1982).
16. N. J. Chou, This Journal, 118, 601 (1971).
17. K. Saito, S. Hamaguchi, and H. Asakawa, Rev. Electr.
Commun. Lab., 30, 649 (1982).
18. T. Nikaido, T. Ogura, S. Hamaguchi, and S.
Muramoto, Paper A-2-2 in the 14th Conference on
Solid State Devices, Tokyo (1982).
Downloaded on 2016-02-18 to IP 130.203.136.75 address. Redistribution subject to ECS terms of use (see ecsdl.org/site/terms_use) unless CC License in place (see abstract).