Download Nonisolated High Step-Up Stacked Converter Based on Boost

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 2, FEBRUARY 2011
577
Nonisolated High Step-Up Stacked Converter Based
on Boost-Integrated Isolated Converter
Ki-Bum Park, Student Member, IEEE, Gun-Woo Moon, Member, IEEE,
and Myung-Joong Youn, Senior Member, IEEE
Abstract—To obtain a high step-up gain with high efficiency
in nonisolated applications, a high step-up technique based on
isolated-type converters is introduced in this paper. By stacking
the secondary side of an isolated converter in addition to its primary side, a high step-up conversion ratio and a distributed voltage
stress can be achieved. Moreover, a careful choice of an isolated
converter can provide zero-voltage switching, continuous input
current, and reduced reverse recovery on diodes. Based on a
conventional voltage-doubler-rectifier boost-integrated half-bridge
converter, the derived converter satisfies all these features, which
make it suitable for high step-up applications. The operational
principle and characteristics of the proposed converter are presented, and verified experimentally with a 135-W, 24-V input,
250-V output prototype converter for a LED driver.
Index Terms—Boost converter, boost-integrated half bridge
(BHB) converter, high step-up converter, isolated converter, zerovoltage switching (ZVS).
I. INTRODUCTION
HE demand of high step-up conversion technique is gradually increased according to the growth of battery-powered
applications and low-voltage renewable sources such as electric vehicles, uninterrupted power supplies, photovoltaic system, and fuel cell system [4]–[13]. For nonisolated applications,
a classical boost converter has been a popular choice because
of a simple structure and a continuous input current. When an
extreme high-voltage gain is required, however, it is hard for
a boost converter to achieve both high-voltage conversion ratio and high efficiency at the same time, due to the parasitic
resistances, which cause a serious degradation in the step-up
ratio and efficiency as the operating duty cycle is increased [1].
Moreover, as an output voltage is increased, a usage of highvoltage device is inevitable, which gives a detrimental effect on
a converter’s performance. That is, a high-voltage diode causes a
severe reverse-recovery problem requiring an additional current
snubber [2], [3] and a high-voltage switch increases a conduction loss. To achieve a high step-up gain and a low-voltage stress
T
Manuscript received April 23, 2010; revised July 13, 2010; accepted August
6, 2010. Date of current version February 9, 2011. This work was supported by
the Brain Korea 21 Project, School of Information Technology, Korea Advanced
Institute of Science and Technology, Daejeon, Korea. This paper was presented
in part at the International Telecommunications Energy Conference, Seoul, Korea, October 18–22, 2009. Recommended for publication by Associate Editor
H. S. H. Chung.
The authors are with the Department of Electrical Engineering, Korea
Advanced Institute of Science and Technology, Daejeon 305-701, Korea
(e-mail: [email protected]; [email protected]; mmyoun@ee.
kaist.ac.kr).
Digital Object Identifier 10.1109/TPEL.2010.2066578
Fig. 1. Conventional high step-up techniques based on classical boost converter. (a) Cascaded structure. (b) Coupled-inductor-employed structure. (c)
Multiplier-cell-employed structure.
on devices, as shown in Fig. 1, various types of step-up converters have been developed based on a classical boost converter,
which utilizes a cascaded structure, a coupled inductor, or a
multiplier cell [4]–[13].
Cascading a boost converter, shown in Fig. 1(a), is one of
the easy approaches to achieve a high step-up gain, however it
requires lots of components and a final output stage still suffers from a high-voltage stress [4]. A boost converter with a
coupled-inductor shown in Fig. 1(b) is a favorable candidate
in low-to-medium power applications for its simple structure
and a low switch-voltage stress. Moreover, a leakage inductance of the coupled-inductor provides a current-snubbing effect. As the auxiliary turns of a coupled inductor are increased
to raise a voltage gain further, however, an input current ripple
becomes larger in return, requiring more input filter. Moreover,
an auxiliary voltage clamp circuit is also required to suppress
the switch-voltage spike caused by the leakage inductance of
a coupled inductor [5]–[10], [28], [36]. A voltage multiplier
cell is also a useful approach to increase a step-up gain in
collaboration with classical converter topologies, as shown in
Fig. 3(c) [11]–[13], [33], [35], [36]. As the output voltage is increased, however, the number of a multiplier stage is increased,
requiring more capacitors and diodes. Besides, a current snubber is required to reduce the excessive di/dt on devices caused
by a capacitor charging operation of the multiplier cell.
With regard to utilizing isolated-type converters for high
step-up applications, current-fed converters, an isolated version
of a boost converter, easily offer a high step-up gain using a
transformer. Moreover, it has a continuous input current and
a voltage stress on rectifier is clamped to the output voltage.
Therefore, it is inherently suitable for high step-up applications [14]–[18], [29], [30]. At the price of utilizing a transformer,
however, a voltage snubber is needed to limit the switch-voltage
0885-8993/$26.00 © 2010 IEEE
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Fig. 2. Nonisolated high step-up structure based on isolated converter. (a)
Basic isolated structure. (b) Stacked structure with source as lower output. (c)
Stacked structure based on boost-integrated structure with primary link capacitor
as lower output.
spike caused by the transformer leakage inductance, resulting
in an additional loss. Besides, an auxiliary circuit is needed
for below 0.5 duty operation. The recently developed currentfed converter for nonisolated applications relieves these limitations with a simple structure, though a hard switching still
remains [16]. Active clamping approaches also resolve these
problems and reduce switching losses, but leads to a complex
structure with increased number of switches [17], [18].
In this paper, to obtain a high step-up capability with high
efficiency, an alternative structure based on isolated-type converters is investigated, since some of isolated converters have
been proved to be suitable for high step-up application such as
current-fed converters mentioned before. To further utilize their
advantages, stacking the secondary side on the top of its primary
side, as shown in Fig. 2, can be considered. This structure would
distribute a voltage stress on devices and contribute to a high
step-up gain as well. Moreover, a careful choice of topology can
inherently provide the zero-voltage switching (ZVS), continuous input current, and alleviated reverse recovery on diode.
II. HIGH STEP-UP CONVERTER BASED ON BOOST-INTEGRATED
ISOLATED CONVERTER
The simplest approach for the stacked structure is just putting
the secondary output upon the input source VS , as shown in
Fig. 2(b) [19]. Some portion of the power is directly transferred
to the output from the source and only the rest of the power is
handled by the converter. Therefore, as the converter manages
less power, more improved efficiency can be achieved. In addition, the voltage stress on the secondary can be reduced, since
it only has to provide the difference between the output voltage
VO and the input voltage VS . When an extremely high step-up
gain is required, however, the effect of voltage stress distribution
becomes ignorable, since most of the voltage stress would be
impressed on the secondary side. Besides, as the input source is
directly connected to the output, the input noise can pass through
the output, i.e., it has very sensitive audio susceptibility.
To further distribute the voltage stress between primary and
secondary sides while relieving the input noise problem, a boost-
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 2, FEBRUARY 2011
integrated isolated converter, where a boost converter is topologically integrated in the primary side [20]–[23], can be converted
to the stacked structure, as shown in Fig. 2(c). Since a general
boost-integrated structure possesses a link capacitor in the primary side, it can be served as a lower output voltage VPo . This
lower output voltage is boosted from the input source, therefore,
less upper output voltage VSo is required and a secondary side
burden can be reduced accordingly. That is, more fair distributed
voltage stresses can be achieved between primary and secondary
sides compared with the structure shown in Fig. 2(b).
Till now, various types of boost-integrated structure have been
developed [20]–[23]. Among them, as a basic topology for the
stacked structure, the voltage-doubler-rectifier boost-integrated
half-bridge (VDRBHB) converter shown in Fig. 3(a) is one
of the fine candidates [22]. Combining the boost-integrated
half-bridge (BHB) converter [20], [21] with the voltage-doubler
rectifier (VDR) in the secondary side [31]–[36], this converter
has ZVS capability, continuous input current, and low voltage
stress on switch and diode, and all these features make it inherently suitable for high step-up applications with high efficiency.
Therefore, it is converted to the stacked structure in this paper.
The proposed nonisolated high step-up converter obtained
from the VDRBHB converter with some modification is presented in Fig. 3(b). In the primary side, a link capacitor Clink
and a half-bridge balancing capacitor CR are repositioned to
the output side to serve as the output capacitors CPo1 and CPo2 .
Then, the secondary VDR is stacked in addition to the primary
BHB module to obtain an additional step-up gain.
In addition, to simplify the circuit, the boost inductor LB and
the transformer can be integrated as shown in Fig. 3(c) since
the shapes of the applied voltages on the boost inductor and the
transformer are the same [23]–[26]. As a result, the magnetizing
inductor of the transformer LM can be served as a boost inductor.
At the price of magnetic integration, however, an input current
ripple becomes larger, since both the boost-inductor current and
the transformer current come from the input terminal.
The fundamental operations and characteristics of circuits
shown in Fig. 3(b) and (c) are the same, except for an input
current. Therefore, the following analysis of the proposed converter is based on the circuit in Fig. 3(b).
III. OPERATION PRINCIPLES
A. Operational Mode Analysis
The basic operation of a proposed converter shown in Fig. 2(b)
is a combined operation between a boost converter and an
asymmetric-controlled half-bridge converter employing VDR.
With a switching action of the main switch QM , a boosted
voltage is generated as the primary output voltage VL , i.e.,
VPo1 + VPo2 . Then, regarding VPo1 and VPo2 as a source, a
power is delivered to the secondary side through the transformer
by a switching action of QM and QA . Here, a complementary
switching enables ZVS and the transformer leakage inductance
Llkg functions as a current-driving impedance in the half-bridge
converter.
The key waveforms and topological states of a proposed converter are presented in Figs. 4 and 5, respectively. A magnetizing
PARK et al.: NONISOLATED HIGH STEP-UP STACKED CONVERTER BASED ON BOOST-INTEGRATED ISOLATED CONVERTER
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Fig. 3. Nonisolated high step-up converter based on VDRBHB converter. (a) Conventional VDRBHB converter. (b) Stacked structure. (c) Stacked structure with
integrated magnetics.
current of the transformer has zero offset in the circuit of
Fig. 3(b), therefore, it is neglected to simplify the analysis. One
switching period is subdivided into six modes and the detailed
operation is presented as follows.
Mode 1 [t0 –t1 ]: QM conducts. The input voltage VS is applied to the boost indictor LB , thus IL b is increased linearly with
a boosting operation. At the same time, the primary lower output voltage VPo1 is applied to the transformer primary side, i.e.,
Vab . Therefore, the powering path is formed to the secondary
side through the secondary lower side diode Ds1 . The difference
between VPo1 and the reflected secondary output voltage nVSo1
is applied to Llkg . The Llkg acts as a current-driving impedance
and the transformer primary current Ilkg is increased linearly.
Both IL b and Ilkg flow through QM .
Mode 2 [t1 –t2 ]: QM is turned off at t1 . Since Ds1 is still
conducting, Vpri is fixed by nVSo1 , and Llkg is resonated with
the switch output capacitances CM and CA . Therefore, CM is
charged by Ilkg as well as IL b while CA is discharged. Ilkg and
VQ M can be expressed as follows:
Ilkg (t) = (Ilkg (t1 ) + IL b (t1 )) cos (ω0 (t − t1 )) − IL b (t1 )
ω0 = 1
Llkg (CM + CA )
VQ M (t) = (IL b (t1 ) + Ilkg (t1 ))
(1)
Llkg
sin (ω0 (t − t1 )) .
CM + CA
(2)
Fig. 4.
Key waveforms of proposed converter.
Mode 3 [t2 –t3 ]: At t2 , VQ M is clamped to VPo1 + VPo2 and
VQ A reaches zero. Both IL b and Ilkg flow through the antiparallel diode of QA , i.e., dA . To achieve ZVS, QA should be turned
on while dA conducts. Since Vpri is still fixed to nVSo1 , the
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 2, FEBRUARY 2011
Fig. 5. Topological states for mode analysis. (a) Mode 1 [t0 –t1 ]. (b) Mode 2 [t1 –t2 ]. (c) Mode 3 [t2 –t3 ]. (d) Mode 4 [t3 –t4 ]. (e) Mode 5 [t4 –t5 ]. (f) Mode 6
[t5 –t6 ].
entire voltage VPo2 + nVSo1 is impressed on Llkg . Therefore,
Ilkg is decreased linearly, which leads IDs1 to be decreased
linearly.
Mode 4 [t3 –t4 ]: At t3 , IDs1 reaches zero. QA is conducting
and the primary upper output voltage VPo2 is applied to Vab .
The powering path is formed to the secondary side through the
secondary upper side diode Ds2 . The difference between VPo2
and the reflected secondary output voltage nVSo2 is applied to
Llkg , therefore, Ilkg is decreased linearly. VS − VPo1 − VPo2
is applied to LB and IL b is decreased linearly and flows to
the output side through QA in reverse direction. The difference
between Ilkg and IL b flows through QA .
Mode 5 [t4 –t5 ]: QA is turned off at t4 . Since Ds2 is still
conducting, Vpri is fixed to nVSo2 , and Llkg is resonated with
the switch output capacitances CM and CA . Therefore, CA is
charged by the difference between Ilkg and IL b . Ilkg and VQ A
can be expressed as follows:
Ilkg (t) = − (|Ilkg (t4 )| − IL b (t4 )) cos (ω0 (t − t4 )) − IL b (t4 )
(3)
VQ A (t) = (|Ilkg (t4 )| − IL b (t4 )+)
× sin (ω0 (t − t4 )) .
Llkg
(CM + CA )
(4)
Mode 6 [t5 –t6 ]: At t5 , VQ A is clamped to VPo1 + VPo2 and
VQ M reaches zero. The difference between IL b and Ilkg flows
through the antiparallel diode of QM , i.e., dM . To achieve ZVS,
QM should be turned on while dM conducts. Since Vpri is still
fixed to nVSo2 , the entire voltage VPo1 + nVSo2 is impressed
on Llkg . Therefore, Ilkg is increased and IDs2 is decreased
linearly.
B. Input–Output Voltage Conversion Ratio
The proposed converter consists of a boost converter and a
half-bridge converter with VDR, and each converter operates
individually except for the common shared parts, i.e., QM and
QA . Thus, in view of a boost converter, its voltage conversion
ratio VL /VS is 1/(1−D).
For the sake of analysis on the half-bridge converter with
VDR, Fig. 6 shows the simplified current waveforms neglecting the switching transitions and assuming that IL b is constant.
Since the each average current of IDs1 and IDs2 is the same
as Io , this relation can be expressed as (5). Then, using the
voltage-second balance across the transformer and (5), the voltage conversion ratio of the half-bridge stage, VSo /VL , can be
expressed as (6).
Both VL /VS and VSo /VL are presented in Fig. 7(a) with
a function of the damping factor Q. The shape of VSo /VL is
symmetric and Q provides a damping effect to the gain curve.
Therefore, as Q is increased, the voltage gain is reduced and the
dead zone, where the gain is zero, is increased. The total output
voltage conversion ratio VO /VS can be expressed as (7) and is
shown in Fig. 7(b). Normally this gain curve follows (7) except
for the case when VSo /VL is zero. In this case, both Ds1 and
Ds2 conduct simultaneously, i.e., the secondary side does not
affect the total gain, and VO /VS follow the boost conversion
ratio VL /VS . Provided that Q is small enough, VO /VS can be
PARK et al.: NONISOLATED HIGH STEP-UP STACKED CONVERTER BASED ON BOOST-INTEGRATED ISOLATED CONVERTER
Fig. 6.
Simplified current waveforms according to n. (a) n > 1 (ZVS condition of Q M ). (b) n < 1 (Hard switching of Q M ).
Fig. 7.
Input–output voltage conversion ratio (n = 1). (a) V L /V S and V S o /V L . (b) V O /V S .
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approximated as (1 + n)/(1−D). When D becomes zero, i.e.,
the converter does not operate, all series connected diodes dA ,
Ds1 , and Ds2 conduct, and VO follows VS such as in a classical
boost converter
Io =
VL + VSo
(VPo1 − VSo1 /n) D2 TS
=
RO
2nLlkg
(VPo2 − VSo2 /n) (1 − D)2 TS
2nLlkg
1 − nQ (1/D2 ) + 1/(1 − D)2
=n
1 + n2 Q ((1/D2 ) + 1/(1 − D)2 )
=
VSo
VL
VO
1 VSo
=
VS
1 − D VL
1+
VL
VSo
(5)
Q=
2Llkg
R O TS
(6)
≈
1+n
(Q ≈ 0).
1−D
(7)
C. Voltage and Current Stress on Devices
With the assumption that Q = 0, the primary output capacitor voltages VPo1 and VPo2 can be approximated to VS and
DV S /(1−D), respectively. Fig. 8 shows the output capacitor
voltage stress normalized by VS . In the secondary, VSo1 and
VSo2 can accordingly be obtained as nVS and nDV S /(1−D),
respectively. That is, the capacitor voltages of upper module,
VSo1 and VSo2 , are “n” time higher than those of lower module.
Fig. 8.
Voltage stress on lower output capacitors.
The voltage stresses on primary switches and secondary diodes
are clamped to VL and VSo , respectively.
From (8) and (9), the switch peak current stress normalized
by IO according to a variation of n can be illustrated as shown
in Fig. 9. Here, “n = 0” represents a classical boost converter,
where the secondary side is ignored and QA only acts as a diode.
As n is increased, both current stresses of switches are increased.
The current stress of QM consists of IL b and nIDs1 , where IL b
is increased and IDs1 is decreased according to an increase in the
duty cycle. The current stress of QA is the difference between
IL b and nIDs2 , therefore, it can be a negative value if n is less
than 1. Fig. 10 shows the switch current stress according to a
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Fig. 9.
Fig. 10.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 2, FEBRUARY 2011
Switch peak current stress normalized by Io according to variation of n. (a) Peak current stress of Q M . (b) Peak current stress of Q A .
Switch peak current stress normalized by Io according to variation of M. (a) Peak current stress of Q M . (b) Peak current stress of Q A .
are expressed as in (10) and (11), and which also represent the
reflected secondary diode currents IDs1 and IDs2 to the primary
side. When D = 0.5, Ilkgp and Ilkgn are equal, and as the duty
cycle is increased, the overall current stresses are decreased
2n
2 (M (1 − D) − 1)
IO =
IO
D
D
2n
1
IO = 2 M −
=
IO .
1−D
1−D
Ilkgp = nID s1p =
(10)
Ilkgn = nIDs2p
(11)
D. ZVS Condition
Fig. 11. Transformer primary current stress normalized by Io according to
variation of M.
variation of the input–output voltage conversion ratio M. As M
is increased, the current stress is increased. In the same M, an
increase in the duty cycle, which implies a decrease in n, reduces
a current stress on switches
1+n
2n
2M (1 − D) − 2
+
IQ M p =
IO = M +
IO
1−D
D
D
IQ A p =
n−1
IO =
1−D
M (1 − D) − 2
1−D
(8)
IO .
(9)
Fig. 11 presents peak the current stress on the transformer
according to a function of M. Ilkgp and Ilkgn denote positive peak
value and negative peak value of the transformer currents, which
As explained in mode 2 of Section II, at first, ZVS of QA is
achieved by the energy stored in Llkg . Unless this energy for
ZVS is sufficient, the boost inductor current IL b , which can be
considered as a current source, would discharge the rest of the
charge in CA . Therefore, ZVS of QA can always be achieved if
the dead time is sufficient. The minimum dead time for ensuring
ZVS can be expressed as (12).
In a similar way, ZVS of QM is achieved by the energy stored
in Llkg with the peak switch current of QA shown in Fig. 9(b).
The ZVS condition can be expressed as (13). Since IQ A IQ A
(t4 ) can be negative as shown in Fig. 6(b), which causes a
hard-switching if n is less than 1, n should be selected at least
higher than 1 to perform ZVS. Fig. 12 shows the simplified
current waveform considering the current ripples of IL b and the
transformer magnetizing current IL m . In this case, IQ A (t4 ) can
be expressed as (14) and it is higher than that shown in Fig. 6(a)
owing to the current ripple of IL b and IL m . Therefore, IQ A (t4 )
PARK et al.: NONISOLATED HIGH STEP-UP STACKED CONVERTER BASED ON BOOST-INTEGRATED ISOLATED CONVERTER
Fig. 12.
IL b .
Simplified current waveform considering current ripples of IL m and
Fig. 13.
LED driver with a large number of LEDs in one string.
is increased as Lb and the transformer magnetizing inductance
Lm is reduced. That is, a larger ripple of IL b and IL m is of
benefit to ZVS of QA
Td ≥
VS (CM + CA )
VL (CM + CA )
≈
IL b (t1 )
(1 + n)Io
(CM + CA ) VL2 ≤ Llkg IQ A (t4 )2
(12)
(13)
n−1
ΔIL b + ΔIL m
IO +
1−D
2
n−1
1
VS DTS
1
=
IO +
+
.
(14)
1−D
2
Lb
Lm
IQ A (t4 ) = Ilkg (t4 ) − IL b (t4 ) =
IV. EXPERIMENT
A. Design Guideline
To verify the proposed converter, a prototype for an LED drive
application [27], where a large number of LEDs are connected
in series and in a string, as shown in Fig. 13, is implemented. The
high step-up converter boosts an input voltage to a high output
voltage, and following current regulators control each current
of LED string. To illustrate the design procedure, the high stepup converter has following specification; input voltage VS =
24 V, output voltage VO = 150–250 V, rated output current
Io = 0.54 A, and switching frequency FS = 85 kHz. The output
voltage and the output current are varied according to the number
of LEDs in one string and the number of strings, respectively.
The following design is focused on 250-V – 0.54-A output and
Fig. 14.
RMS current of main switch Q M .
Fig. 15.
Transformer turn ratio n according to variation of M.
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the required input–output voltage gain M is 10.4 (=250/[24]),
i.e., about 10.
In the converter design, a selection of the main switch QM ,
which is rather burdened by the sum of the large input current
IL b and the transformer current Ilkg , is primarily considered
in view of the cost and the efficiency. As presented in (15)
and Fig. 14, for the same M, an rms value of switch current is
slowly decreased as a duty cycle is increased. That is, a switch
conduction loss would be rarely affected by the operating duty
cycle. On the other hand, a switch-voltage stress, VS /(1 − D),
is decreased as the duty cycle is decreased, which lead to a use of
lower voltage switch having a smaller on-resistance. However,
a smaller duty cycle results in a larger turn ratio n from (7),
which increases a handling power of the secondary side. As
shown in Fig. 11, consequently, a smaller duty cycle increases
a peak current stress on the transformer and would increase the
transformer conduction loss accordingly. Therefore, a duty cycle
should be selected to accommodate a low-voltage stress as much
as possible while not to increase the transformer conduction loss
too much. To utilize a 100-V switch with a sufficient margin,
the nominal duty cycle Dnom is selected as about 0.5.
2
n+D
n2
+
IQ M rm s ≈ IO
1−D
3
(M − DM − 1)2
. (15)
= IO (M − 1)2 +
3
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 2, FEBRUARY 2011
TABLE I
EXPERIMENTAL PARAMETERS
Considering Dnom to be 0.5, from (7) and Fig. 15, the required transformer turn ratio n is determined as 4.2 accordingly. Assuming RO = 462, FS = 85 kHz, and Llkg = 3 uH,
the damping factor Q in (6) is so small, merely around 0.001,
that its damping effect on the output voltage would be negligible. With the selected n and Dnom , from (6) and (7), VL and VSo
are designed to be about 50 V and 200 V, respectively. Thereby,
the usage of a 100-V switch is allowed for the primary side and
300-V diodes for the secondary VDR.
The design of the boost inductor and the transformer is the
same as those of conventional ones. Considering a current ripple
to be 25% of the input current 5.7 A, LB is designed as 120 uH.
From the fabricated transformer, the transformer magnetizing
inductance Lm is obtained as 230 uH.
In LED driver applications, because of its constant current
load characteristic, the converter is usually operated in a fullload condition. With previously obtained parameter from (14),
IQ A (t4 ) in a full-load condition would be 4.3 A. Provided
IRF540 is used for switch, of which COSS is about 100 pF
at a 50-V drain-sours voltage, the required Llkg for ZVS of QM
should be larger than 2.6 uH from (13).
B. Experimental Results
To verify the proposed stacked converter, a prototype is implemented. The specification and design parameters obtained
from the design guideline are presented in Table I.
Figs. 16 and 17 show the experimental waveforms at a fullload condition with VO = 250 V and VO = 150 V, respectively.
They well coincide with the theoretical analysis except for some
voltage spikes across switches caused by parasitic inductance.
In case of VO = 250 V, the operating duty cycle is slightly larger
than 0.5. The voltage stresses on both switches are around 50 V,
which allows utilizing 100-V switches, and the voltage stress on
the secondary diode is well clamped to the upper output voltage
200 V allowing the use of 300-V diodes. As can be seen in the
waveforms of IQ A and VQ A , the ZVS of QA is well achieved.
Although, the turn-off current of IQ A is small, about 4 A, the
ZVS of QM is also achieved with 2.8 uH of Llkg which is
designed in the Section IV-A. The ZVS of QM is verified by the
small negative current flowing through QM .
In case of VO = 150 V, because of a reduced step-up gain,
the operating duty cycle is reduced to about 0.35 and the voltage stresses on most devices are decreased compared to those
of VO = 250 V case. The voltage stress on switch is under
50 V and the voltage stress on secondary diode is also well
clamped to about 110 V. However, the reduced duty cycle
causes an imbalance of Ilkg in return, which leads to an increase in the current stress of IQ M . The ZVS of both QM and
QA are also achieved as verified by the negative current flowing
ahead.
In the experiment of a conventional boost converter, where
a low-performance high-voltage switch is used inevitably, the
output voltage could not be obtained over 180 V. That is, the
switch becomes thermally unstable as the output voltage is
increased with the same boost inductor, a switch FQP17N40
(Rds = 0.21 Ω, VDSS = 400 V), and a diode STTH2003.
For the comparison with the other high step-up converter, a
prototype of the circuit presented in [7] is implemented as shown
in Fig. 18(a) with the following design parameters; a switching
frequency = 85 kHz, a boost inductance LB = 33 uH (core:
EER3435), a coupling turn ratio n = 7, a leakage inductance
Llkg = 25 uH, a switch Q: IRF540 (Rds = 49 mΩ, VDSS =
100 V), a clamp diode DC : 16CTQ100 (VF = 0.58 V, VRRM =
100 V), an output diode DO : ISL9K1560 G3 (VF = 1.8 V,
VRRM = 600 V), a snubber capacitor Csn = 22 nF, a snubber
resistor Rsn = 20 kΩ. Fig. 18(b) and (c) show the experimental
waveforms at a full-load condition with VS = 250 V and VS =
150 V, respectively. The input current Iin , which comprises the
switch current IQ and the clamp diode current ID C as well,
is discontinuous by the coupling effect of LB . The switchvoltage stress is about 50 V, allowing the usage of a 100-V
switch. However, the voltage stress on the output diode, VD O ,
is over 400 V in spite of utilizing an resistor-capacitor-diode
PARK et al.: NONISOLATED HIGH STEP-UP STACKED CONVERTER BASED ON BOOST-INTEGRATED ISOLATED CONVERTER
Fig. 16.
Experimental waveforms at V O = 250 V.
Fig. 17.
Experimental waveforms at V O = 150 V.
585
586
Fig. 18.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 2, FEBRUARY 2011
Experiment of high step-up circuit in [7]. (a) Circuit diagram. (b) Experimental waveforms at V O = 250 V. (c) Experimental waveforms at V O = 150 V.
converter is higher over 1% at the full-load condition owing
to the full ZVS operation and the usage of low-voltage highperformance devices. In addition, the proposed converter does
not require an additional input filter because of its inherent
continuous input current by the boost inductor. If the circuit
in [7] adopts an additional input filter to smooth the input current,
the efficiency would be slightly decreased further in return.
V. CONCLUSION
Fig. 19.
Measured efficiency.
(RCD)-snubber. The use of a 600-V diode is inevitable and it
causes a reverse recovery, which can be observed from ID O , and
the reflected current to the primary side of the coupled-inductor
is rather high as can be seen in Iin .
Fig. 19 presents the comparative efficiency curves for the
proposed converter and the circuit in [7] with respect to VO =
250 V and VO = 150 V. The overall efficiency of the proposed
converter with VO = 250 V is over 93%. Since the design for
the proposed converter is focused on the VO = 250 V case,
the efficiency of VO = 150 V gets lower due to the reduced
duty cycle which causes an asymmetric in Ilkg and increases a
conduction loss. In case of the circuit in [7], the efficiency with
VO = 250 V is below 92% at the full-load condition due to a
large conduction loss, a snubber loss, and a reverse-recoveryrelated loss. Regarding the case of VO = 150 V, however, it
shows a rather higher efficiency compared with the proposed
converter for a reduced conduction loss. It is noted that, at the
design point of VO = 250 V, the efficiency of the proposed
An alternative structure to obtain a high step-up gain for nonisolated applications is introduced in this paper. Based on the
conventional VDRBHB converter, the secondary side is stacked
in addition to the primary side to further increase the step-up
gain and distribute the voltage stress to devices. Moreover, the
derived stacked converter shows a continuous input current and
a ZVS capability by inherent characteristics of VDRBHB converter. It is worth noting that the introduced stacked structure
can be extended to other isolated-type converters and, particularly, a boost-integrated structure is expected to shows a good
performance for high step-up applications.
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Ki-Bum Park (S’07) was born in Korea, in 1981. He
received the B. S., M. S., and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of
Science and Technology (KAIST), Daejeon, Korea,
in 2003, 2005, and 2010, respectively.
He is currently a Postdoctoral researcher at
KAIST, Daejeon. His current research interests include dc–dc converter and power-factor correction
ac–dc converter for server power systems and display power systems, and display driver circuit.
Dr. Park received the Best Paper Award from the
International Telecommunications Energy Conference in 2009.
Gun-Woo Moon (S’92–M’01) received the M. S.
and Ph.D. degrees in electrical engineering from the
Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1992 and 1996,
respectively.
He is currently a Professor at the Department
of Electrical Engineering, KAIST, Daejeon. His research interests include modeling, design and control of power converters, soft-switching power converters, resonant inverters, distributed power systems,
power-factor correction, electric drive systems, driver
circuits of plasma display panels, and flexible ac transmission systems.
Dr. Moon is a member of the Korean Institute of Power Electronics, Korean Institute of Electrical Engineers (KIEE), Korea Institute of Telematics and
Electronics (KITE), Korea Institute of Illumination Electronics and Industrial
Equipment, and Society for Information Display (SID).
Myung-Joong Youn (S’74–M’78–SM’98) was born
in Seoul, Korea, in 1946. He received the B. S. degree from Seoul National University, Seoul, Korea
in 1970, and the M. S. and Ph.D. degrees in electrical engineering from the University of Missouri,
Columbia, MO, in 1974 and 1978, respectively.
In 1978, he joined the Air-Craft Equipment Division, General Electric Company, Erie, PA, where he
was an individual contributor on Aerospace Electrical System Engineering. Since 1983, he has been a
Professor at the Korea Advanced Institute of Science
and Technology, Daejeon, Korea. His research activities are in the field of power
electronics and control, which include the drive systems, rotating electrical machine design, and high-performance switching regulators.
Dr. Youn is a member of the Institution of Electrical Engineers, U. K.,
Korean Institute of Power Electronics, Korean Institute of Electrical Engineers,
and Korea Institute of Telematics and Electronics.