Download Power Amplifier in SiGe technology for 60GHz Systems Electronics

Power Amplifier in SiGe technology for 60GHz Systems
Tiago Barata Gabriel
Thesis to obtain the Master of Science Degree in
Electronics Engineering
Supervisor: Prof. João Manuel Torres Caldinhas Simões Vaz
Examination Committee
Chairperson: Prof. Jorge Manuel Torres Pereira
Supervisor: Prof. João Manuel Torres Caldinhas Simões Vaz
Members of the committee: Prof. Pedro Rafael Bonifácio Vítor
Outubro 2014
Abstract
The last few years have witnessed a tremendous growth of wireless communications due to
demand and technology advances. This led to an increasing demand of high transmission speeds and
larger bandwidths, creating a great interest worldwide in the 60 GHz band. This band has almost 9 GHz
of unlicensed bandwidth, allowing high-speed data rates. In these frequencies exist a huge oxygen
attenuation which significantly attenuates radio signals over distances of a few hundred meters, causing
them suitable for wireless short distance communications. Another advantage of the 60 GHz band is the
short wavelength, approximately 5 mm in free space, allowing the integration of passive components,
such as transmission lines and antennas.
The recent developments of CMOS and SiGe technologies have enabled these to be used in the
design of microwave integrated systems. These technologies have some limitations, which make the
development of a high frequency power amplifier one of the main challenges on the transceiver design.
The aim of this project is to develop a power amplifier in SiGe BiCMOS 0.25 µm technology for
60 GHz systems, with the best tradeoff between the amplifier output power, linearity and efficiency.
Another objective is to increase the output power by using power combining techniques, without
compromising power amplifier efficiency.
Keywords: Power Amplifier, Silicon-germanium, Hetero-junction Bipolar Transistor, Class-A,
Output power, Power added efficiency, Power gain, Power Combiner, Electromagnetic simulations.
iii
Resumo
Nos últimos anos tem-se testemunhado um enorme crescimento das comunicações sem fios,
motivado pela procura e pelos avanços da tecnologia. O que levado a um aumento da procura por
maiores velocidades de transmissão e larguras de banda, criando um grande interesse na banda dos
60 GHz. Esta banda tem aproximadamente uma largura de 9 GHz, e é não licenciada, permitindo
grandes velocidades de transmissão de dados. Nesta banda existe ainda uma grande atenuação
devido ao oxigénio o que faz com que seja adequada a transmissões de curta distância, uma vez que
os sinais de rádio não se conseguem propagar mais que uma centena de metros. Os 60 GHz tem ainda
a vantagem de ter um comprimento de onda relativamente pequeno, 5mm em espaço livre, permitindo
assim a integração de elementos passivos, como linhas de transmissão, e de antenas.
O desenvolvimento das tecnologias de CMOS e SiGe permitiram que estas começassem a ser
usadas no projecto de sistemas integrados de microondas. No entanto, estas tecnologias têm ainda
algumas limitações o que faz com que o desenvolvimento de um amplificador de potência a altas
frequências nestas tecnologias seja um dos principais desafios no projecto de um emissor-receptor.
O objectivo principal deste trabalho consiste em desenvolver um amplificador de potência em
tecnologia SiGe BiCMOS 0.25 µm para sistemas a 60 GHz, onde se consiga obter a melhor relação
possível entre a potência de saída do amplificador, a linearidade e a eficiência. Outro dos objectivos é
aumentar potência de saída usando técnicas de combinação de potência sem comprometer a eficiência
do amplificador de potência.
Palavras-chave: Amplificador de Potência, Silício-germânio, Transístor Bipolar de Heterojunção,
Classe-A, Potência de saída, PAE, Ganho de potência, Combinador de Potência, Simulações
electromagnéticas.
iv
Acronyms
4G
Fourth Generation
CMOS
Complementary Metal-Oxide-Semiconductor
ECMA
European Computer Manufacturers Association
EM
Electromagnetic
fmax
Maximum Oscillating Frequency
FoM
Figure of Merit
fT
Transit Frequency
Gp
Power Gain
HBT
Hetero-junction Bipolar Transistor
ITRS
International Technology Roadmap for Semiconductors
NLOS
Non-Line of Sight
P1dB
1dB Compression Point
PA
Power Amplifier
PAE
Power-Added-Efficiency
PC
Power Combiner
Psat
Saturated Power
SiGe
Silicon-Germanium
WiGig
Wireless Gigabit Alliance
WLAN
Wireless Local Area Network
WPAN
Wireless Personal Area Network
v
Acknowledgements
I am using this opportunity to express my gratitude to everyone who supported me throughout the
course of this thesis.
Firstly, I would like to thank my supervisor, Professor João Manuel Caldinhas Vaz, for all the
support, guidance and patience throughout this work. He’s constant teachings, invaluably constructive
criticism and friendly advice truly helped me and made it possible to write this thesis, in the requested
period of time.
Secondly, an honest and heartfelt thank you to my family, for all the support, affection and
provided moments. To my parents, Paula and João, for all the effort and sacrifices they have made and
which got me here. A special thanks to my father, whom drove me to college every day. Also, to my
brother, for the support and pleasant moments.
Thirdly, a warm thanks to my girlfriend Rute for her aspiring guidance, all the patience and help
she gave me, whether it was reviewing this work or just inspiring me. Above all, for the companionship,
love and care she gives me.
At last, but not least, to my friends and colleagues, that stood by me throughout these years and
without whom this experience wouldn’t have been so intense and inspiring.
vi
Contents
Abstract.................................................................................................................................................... iii
Resumo ................................................................................................................................................... iv
Acronyms ..................................................................................................................................................v
Acknowledgements ................................................................................................................................. vi
Contents ................................................................................................................................................. vii
List of Figures .......................................................................................................................................... ix
List of Tables .......................................................................................................................................... xii
Introduction ...................................................................................................................................... 1
1.1.
Purpose and Motivation ........................................................................................................... 1
1.2.
Goals and challenges .............................................................................................................. 2
1.3.
State of the Art ......................................................................................................................... 2
1.3.1. SiGe BiCMOS Technology .................................................................................................... 2
1.3.2. 60-GHz Standards ................................................................................................................. 3
1.3.3. Power Amplifier ..................................................................................................................... 5
1.4.
Specifications........................................................................................................................... 7
1.5.
Document Organization ........................................................................................................... 8
Technology Study ............................................................................................................................ 9
2.1.
Technology Overview .............................................................................................................. 9
2.2.
Active Devices ....................................................................................................................... 10
2.3.
Passive Elements .................................................................................................................. 13
2.3.1.
Capacitors ..................................................................................................................... 13
2.3.2. Inductors .............................................................................................................................. 14
2.3.3. Transmission Lines .............................................................................................................. 15
2.4. Electromagnetic Simulations ...................................................................................................... 18
2.4.1.
Profile Improvement ..................................................................................................... 19
2.4.2. EM Simulations of Passive Components ............................................................................ 21
2.5.
Summary ............................................................................................................................... 25
Power Amplifier ............................................................................................................................. 27
3.1.
Class-A Operation Mode ....................................................................................................... 28
3.2.
HBT in Class-A Study ............................................................................................................ 28
3.3.
Common-emitter Vs Cascode ............................................................................................... 31
3.4.
Simulation Results ................................................................................................................. 35
3.5.
Summary ............................................................................................................................... 51
Power Amplifier with Power Combining ........................................................................................ 53
4.1.
Wilkinson Power Combiner ................................................................................................... 53
4.2.
Simulation Results ................................................................................................................. 54
4.3.
Power Combiner Layout ........................................................................................................ 56
4.4.
Power Amplifier and Power Combiner .................................................................................. 58
vii
4.5.
Summary ............................................................................................................................... 62
Conclusions and Future Work ....................................................................................................... 63
5.1.
Conclusions ........................................................................................................................... 63
5.2.
Future Work ........................................................................................................................... 64
Bibliography ................................................................................................................................... 65
viii
List of Figures
Figure 1.1: fmax and the associated ft data for selected SiGe vendors (Source [13]).
3
Figure 2.1: Carbon influences in maximum oscillating frequency (source [23]).
9
Figure 2.2: Transistor schematic.
10
Figure 2.3: Layout of the npn200_1 (left) and npn201_1 (right).
11
Figure 2.4: Layout of the npn200_8 (above) and npn201_8 (below).
11
Figure 2.5: DC characteristic IC(VCE) of npn201_8.
11
Figure 2.6: DC characteristic IC(VCE) of npn201_8.
12
Figure 2.7: Stability factor and additional stability factor of np201_8 for maximum transit frequency. 12
Figure 2.8: Capacitor’s schematic and layout.
13
Figure 2.9: Capacitor’s different capacitances.
13
Figure 2.10: Capacitor’s quality factors.
14
Figure 2.11: Inductor schematic (left) and layout (right).
14
Figure 2.12: 0.94 nH L2 inductor resonant frequency.
15
Figure 2.13: 0.94 nH L2 inductor quality factor.
15
Figure 2.14: Technology microstrip lines schematic.
16
Figure 2.15: Technology microstrip lines layout.
16
Figure 2.16: 50 Ω transmission line matching.
16
Figure 2.17: 50 Ω transmission line losses.
17
Figure 2.18: 50 Ω transmission line effective electrical length.
17
Figure 2.19: 502 transmission line matching.
17
Figure 2.20: 502 transmission line effective electrical length.
18
Figure 2.21: 502 transmission line losses.
18
Figure 2.22: 1 pF capacitor EM and electrical model results.
21
Figure 2.23: Inductor EM and electrical model results.
22
Figure 2.24: EM and electrical model matching results for 50 Ω transmission line.
22
Figure 2.25: EM and electrical model losses results for 50 Ω transmission line.
23
Figure 2.26: EM and electrical model phase results for 50 Ω transmission line.
23
Figure 2.27: EM and electrical model phase results for 502 Ω transmission line.
23
Figure 2.28: EM and electrical model matching results for 502 Ω transmission line.
24
Figure 2.29: EM and electrical model losses results for 502 Ω transmission line.
24
Figure 3.1: Simplified diagram of a single stage power amplifier.
27
Figure 3.2: Class-A bias point for a bipolar transistor.
28
Figure 3.3: Class-A transistor study schematic.
29
Figure 3.4: PA in common-emitter mode with ideal components.
32
Figure 3.5: Stability factor and additionally stability factor of PA in common-emitter mode.
32
Figure 3.6: Power results of PA in common-emitter mode.
32
Figure 3.7: PA in common-emitter mode efficiency.
33
Figure 3.8: PA in cascode mode with ideal components.
33
Figure 3.9: Stability factor and additionally stability factor of PA in cascode mode.
34
ix
Figure 3.10: Cascode S11 and S22 parameters.
34
Figure 3.11: Cascode power results.
34
Figure 3.12: Cascode PAE.
35
Figure 3.13: Transistor Q1 collector-emitter voltage.
35
Figure 3.14: Class-A power amplifier in common-emitter mode with technology components.
36
Figure 3.15: S11 and S22 parameters results.
36
Figure 3.16: Power amplifier with the solution to solve the instability problem.
37
Figure 3.17: S11 and S22 parameters of the Figure 3.16 circuit.
37
Figure 3.18: PA power results with technology components.
37
Figure 3.19: PA efficiency with technology components.
38
Figure 3.20: Bias network layout.
38
Figure 3.21: Bias network S-parameters.
38
Figure 3.22: DC block with two 50 Ω transmission lines layout.
39
Figure 3.23: DC block S-parameters.
39
Figure 3.24: PA with EM model components.
39
Figure 3.25: S11 and S22 parameters of the PA with EM model components.
40
Figure 3.26: Power results of the PA with EM model components.
40
Figure 3.27: PAE of the PA with EM model components.
40
Figure 3.28: PA with an input matching network.
41
Figure 3.29: PA S11 and S22 reflection coefficients.
41
Figure 3.30: Power results of the PA with an input matching network.
41
Figure 3.31: PAE of the PA with an input matching network.
42
Figure 3.32: Power amplifier’s layout.
42
Figure 3.33:S11 and S22 parameters of the PA with EM networks simulated.
43
Figure 3.34: Power results of the PA with EM networks simulated.
43
Figure 3.35: PAE of the PA with EM networks simulated.
43
Figure 3.36: Transistors block layout.
44
Figure 3.37: S11 and S22 parameters of the PA with transistors layout extraction.
44
Figure 3.38: Power results of the PA with transistors layout extraction.
44
Figure 3.39 PAE of the PA with transistors layout extraction.
44
Figure 3.40: VCE for a VCC of 1.1 V.
45
Figure 3.41: VCE for a VCC of 1.2 V.
45
Figure 3.42: Power results for a VCC of 1.2 V.
45
Figure 3.43: PAE for a VCC of 1.2 V.
46
Figure 3.44: 2 stages power amplifier.
46
Figure 3.45: 2 stages PA S11 and S22 parameters.
47
Figure 3.46: S11 and S22 parameters of 2 stages PA with stability solution.
47
Figure 3.47: S11 and S22 parameters of the PA with EM components.
47
Figure 3.48: S11 and S22 parameters of the PA with the ITN adjusted.
48
Figure 3.49: Power results of PA with matching networks.
48
x
Figure 3.50: PAE of PA with matching networks.
48
Figure 3.51: 2 stages power amplifier’s layout.
49
Figure 3.52: S11 and S22 of 2 stages PA.
49
Figure 3.53: 2 stages PA power results.
49
Figure 3.54: 2 stages PA efficiency.
50
Figure 3.55: VCE1 and VCE2 when VCC=1.2 V.
50
Figure 3.56: 2 stages PA power results when VCC=1.2V.
50
Figure 3.57: 2 stages PA PAE when VCC=1.2V.
51
Figure 4.1: 2:1 Wilkinson Power Combiner.
54
Figure 4.2: Obtained S-Parameters for the 2:1 Wilkinson Power Combiner.
55
Figure 4.3: Power combiner with 5 degrees lines between the inputs and the resistor.
55
Figure 4.4: Obtained S-Parameters for the power combiner of Figure 4.3.
56
Figure 4.5: Rectangular power combiner layout.
56
Figure 4.6: Squared power combiner layout.
56
Figure 4.7: Rectangular power combiner results.
57
Figure 4.8: Squared power combiner results.
57
Figure 4.9: Power combiner’s output bias network.
58
Figure 4.10: Rectangular combiner’s results.
58
Figure 4.11: Squared combiner’s results.
58
Figure 4.12: Power amplifier with power divider and combiner layout.
59
Figure 4.13: Power results of the PA with a power divider and power combiner.
60
Figure 4.14: PAE of the PA with a power divider and power combiner.
60
Figure 4.15: 2 stages power combiner with power divider and power combiner.
61
Figure 4.16: Power results of the 2 stages PA with power combining.
61
Figure 4.17: PAE of the 2 stages PA with power combining.
61
xi
List of Tables
Table 1.1: 60 GHz standards and its applications (source [2]). .............................................................. 4
Table 1.2: State of the Art of 60 GHz Power Amplifiers in SiGe Technology. ........................................ 5
Table 1.3: Power amplifier’s specifications. ............................................................................................ 7
Table 2.1: HBTs main parameters (source [24]). .................................................................................. 10
Table 2.2: Maximum collector current for all the HBTs. ........................................................................ 10
Table 2.3: Transmission lines summary. ............................................................................................... 18
Table 2.4: Technology metal conductivity. ............................................................................................ 19
Table 2.5: Technology vias properties. ................................................................................................. 20
Table 2.6: Resistors properties. ............................................................................................................ 21
Table 2.7: Technology resistors conductivity. ....................................................................................... 21
Table 2.8: Electrical model and electromagnetic results for the required transmission lines. .............. 24
Table 3.1: Obtained values for the load that maximizes the tradeoff between PAE and P out. .............. 30
Table 3.2: Obtained values for the load that maximizes the tradeoff between PAE and P out................ 31
Table 3.3: Obtained values for the load that maximizes the tradeoff between PAE and P out. .............. 31
Table 3.4: Common emitter and cascode power results. ...................................................................... 35
Table 3.5: Input matching network dimensions. .................................................................................... 41
Table 3.6: Impedance transformation network dimensions. .................................................................. 48
Table 3.7: Power amplifier main parameters and FoM. ........................................................................ 51
Table 4.1: Transistors input matching network...................................................................................... 59
Table 5.1: Specifications and obtained results. ..................................................................................... 63
xii
Introduction
1.1. Purpose and Motivation
The wireless communication sector had an enormous growth in the last few years due to the
increasing demand of wireless devices [1]. Nowadays, applications such as high-speed point-to-point
data links or personal area wireless networking are requiring transmission data rates which cannot be
performed by existing third-generation cellular system or wireless local area network (WLAN) 802.11a
[1], as well as the fourth generation (4G) which already has data rates between the 10 and 50 Mbit/s [2].
This led to a carrier frequency and channel bandwidth increase [3], as a way to improve data transfer
speed.
The 60 GHz band begins to attract growing interest worldwide because of the almost 9 GHz of
unlicensed bandwidth, which allows extremely high data rates to be transmitted [3], [4]. Additionally, this
frequency band has a huge oxygen absorption, which significantly attenuates radio signals with
approximately 16/17 dB/km [2], as well as fog and rain. For that reason, the 60 GHz band is attractive
for short-range high data rate wireless communications and for indoor radar applications [5]. Another
advantage of the 60 GHz frequency band is the relative short wavelength, approximately 5mm in free
space, which allows unprecedented levels of integration of analog and microwave components such as
transmission lines [2], and even integrated antennas into a single chip [6].
In such high frequencies the transceivers’ design is more difficult than for lower frequencies since
a small parasitic element can change the operating frequency by several GHz [3]. Therefore a careful
calculation of the parasitic elements and a full modeling of all the passive parts must be performed
before any design [3].
Recent years have seen major advances in ultra-scaled silicon technologies, such as digital
complementary metal-oxide-semiconductor (CMOS) and silicon-germanium (SiGe) Hetero-junction
Bipolar Transistors (HBTs), where transistors have been made smaller, and as a result, fast enough for
mm-wave operations [7]. SiGe HBTs have achieved transition and maximum oscillating frequencies as
high as fmax/fT=350/300 GHz [8], which allows these technologies to compete in terms of high frequency
performance to other technologies like Gallium Arsenide and Indium Phosphide [9]. On the other hand,
the transistors size reduction results in a lower breakdown voltage [9] which limits performance [10] and
makes the high power amplifiers a challenging block in a transceiver design [8].
The Power Amplifier (PA) is one of the most powerfull hungry device of a wireless system [2]. The
power amplifier performance can be defined in terms of saturated power (P sat), power gain (Gp), output
1dB compression point (P1dB) and Power-Added-Efficiency (PAE) [1]. Therefore, it can be designed in
order to maximize one of these parameters or to achieve a good tradeoff between them. However, in
high frequencies parasitic losses become important and degrade the power amplifier performance [1].
In order to obtain better performance values, Power Combiners (PCs) are frequently used. Although,
this solution introduces losses, the total output power is the sum of multiple PA cells [11]. The power
combiner should be used whenever its insertion losses are compensated by the output power increase
[11].
1
This work focus is on the design of a power amplifier with SiGe BiCMOS 0.25 µm technology for
60 GHz applications where the main goal is designing the PA with the best tradeoff between the output
power, linearity and PAE. Another goal is to verify if a power combiner can be implemented in this
technology, namely if the power combiner enables a higher output power without compromising the
efficiency of the amplifier.
1.2. Goals and challenges
The main goal of this project is to design a power amplifier for 60 GHz wireless personal area
networks (WPAN) in 0.25 µm SiGe technology. In order to accomplish this, some key objectives were
defined:
 Study the active components, in this case the transistors of the technology through DC
analysis.
 Study the passive components, such as transmission lines and capacitors of the technology,
in order to identify its behavior. Electromagnetic (EM) simulations will be performed to prove the
components’ electrical model.
 Study the transistors in a common-emitter and a cascode topology, both working in class-A
mode in order to verify the better transistor choice. Then, a PA will be developed taking into
account the results obtained in the first stage. Finally, it will be compared with the state-of-art
PAs by the PA figure of merit (FoM).
 Design a possible power combiner in order to see what losses it inserts in the output signal
and how many PAs can be combined.
The main challenge will be to design a power amplifier that has a significant output power with a
good efficiency.
1.3. State of the Art
The power amplifier area is very wide so this chapter will be focused on the PA in SiGe technology
for 60 GHz systems.
Firstly, in this section, a brief overview about the SiGe BiCMOS technology is presented. After
that, the existing standards for 60 GHz systems and its applications are presented. At last, the studied
articles with the best results will be presented.
1.3.1. SiGe BiCMOS Technology
Only in the last 15 years was possible to grow lattice-matched SiGe alloy in silicon. The
introduction of SiGe in the base region of silicon-based bipolar transistors offered improved performance
at higher operating frequencies [12]. In addition to this, the increasing efficiency of SiGe HBTs is putting
aside others III-V semiconductors like Gallium-Arsenide (GaAs) and Indium Phosphide (InP) [8].
2
The development of SiGe HBT technology has improved aggressively, which allowed an advance of the
maximum transition frequency, f T, and maximum oscillation frequency, f max, from 100 GHz to 300 GHz
and beyond in research laboratories [13], as can be seen in Figure 1.1.
Figure 1.1: fmax and the associated ft data for selected SiGe vendors (Source [13]).
On one hand, SiGe BiCMOS technology features important advantages such as:
 Inherently high forward current gain;
 Homogeneous high integration of bipolar transistors (HBT) and CMOS;
 Power saving due to higher fT allowing a lower bias current for a given gain at a given
frequency;
 Low noise figure and high linearity. [12]
On the other hand, the continuous growth of transit and maximum oscillation frequency by device
down scaling results in an inevitable reduction of the breakdown voltage [9] and the PAE [8]. The
breakdown voltage reduction poses a challenge when high dynamic range, high power or low phasenoise is a key requirement for circuits’ development [13].
1.3.2. 60-GHz Standards
The 60 GHz band is a band full of opportunities for higher data rates and for that reason there are
efforts made by several industry consortia and international standard organization to standardize the
60 GHz WPAN and to commercialize it [2], [14]. Current technical standards activities include
WirelessHD, ECMA 387, IEEE 802.15.3c, IEEE 802.11ad and the WiGig standard. All these standards
target short-range 60 GHz networks [2].
The WirelessHD is an industry alliance which aims to provide an unified standard for multi-gigabit
wireless connectivity for consumer electronics, personal computing and mobile devices [15]. This
Consortium supports the WirelessHD standard which according to [16] is intended to create wireless
video area networks (WVANs) to stream uncompressed audio and 1080p video, deliver compressed
3
audio/video data, provide advanced audio/video device control, and allow for non-line of sight (NLOS)
operation with a high degree of privacy.
European Computer Manufacturers Association (ECMA) International is an industry association
founded in 1961 and dedicated to the standardization of Information and Communication Technology
and Consumer Electronics [17]. This Association is also developing the ECMA 387 standard which is
intended to support bulk data transfer such as downloading data from a kiosk and high-definition
multimedia streaming [14].
There are two IEEE groups studying and making standards for the 60 GHz band, with different
objectives. The IEEE 802.15.3c mm-wave standard is an amendment to the IEEE 802.15.3 standard
and shares many similarities with the WirelessHD standard [2]. This group is targeting WPANs, while
the IEEE 802.11 Very High Throughput (VHT) Study Group was studying solutions for future WLAN
standard. From this group was created the Task Group ad (TGad) in order to define enhancements to
the IEEE 802.11 standard for 60GHz band [14]. Another goal of this group is to maintain WLAN
experience such a larger coverage and a backward compatibility to 802.11 [14].
Wireless Gigabit Alliance (WiGig) has worked closely with the IEEE 802.11ad technical group,
and the WiGig standard closely mirrors the IEEE 802.11ad standard [2]. In fact, WiGig Alliance
developed the WiGig MAC and PHY Specification which contributed to the IEEE 802.11ad
standardization process [18]. Already in 2013, the WiGig Alliance was unified with the Wi-Fi Alliance
allowing the consolidation of all technology and certification development within Wi-Fi Alliance to deliver
closely-harmonized connectivity and application-layer solutions [18]. The WiGig technology is based on
IEEE 802.11ad standard and enables a wide range of advanced uses, including wireless docking and
connection to displays, as well as virtually instantaneous wireless backup’s synchronization, and file
transfers between computer and handheld devices [18].
Nowadays, a large number of 60 GHz standards exist, which represents a major problem for
device interoperability and, possibly, leading to consumer confusion and device ubiquity [2]. A brief
summary of the standards and its applications is presented in Table 1.1.
Table 1.1: 60 GHz standards and its applications (source [2]).
Maximum Data Rate
(Gbps)
Name
WirelessHD
ECMA-387
Forum Type
Industry
Consortium
International
Standard
Applications
OFDM
Single Carier
(SC)
4
-
Uncompressed HD video
4,032
6,35
Bulk data transfer and HD
streaming
5,7
5,2
Portable point-to-point file
transfer and streaming
802.15.3c (TG3c)
International
Standard
802.11ad (Tgad)
International
Standard
>1
Rapid upload/download,
wireless display, distribution
of HDTV
WiGig
Industry
Consortium
7
File transfers, wireless
display and docking , and
streaming high definition
4
1.3.3. Power Amplifier
The power amplifier is one of the key blocks of a communication system. It produces the required
output power for transmitting information off-chip with high linearity, which minimizes adjacent channel
perturbation [19]. In the particular case of battery operation, minimum DC power at a given output power
is required [19].
In order to compare the performance of different power amplifiers, a figure of merit (FoM) is used.
The FoM used in this work was introduced by the International Technology Roadmap for
Semiconductors (ITRS), and includes the output power, Pout, the power gain, Gp, and the power-addedefficiency, PAE, at its 1 dB compression point, as well as the carrier frequency, f. Once the state-of-the
art PAs are all for the same frequency (60 GHz), it was decided not to use this parameter in this project.
Considering this, the following formula is obtained
FoMPA  Pout dBm  Gp dB  10log PAE  .
(1.1)
Recently, many articles concerning power amplifiers for 60 GHz systems in SiGe technologies
have been published. These articles have differences in terms of topologies and technologies which
result in different values for output power at 1 dB compression point, saturated output power, power
gain and PAE. A short summary of the selected articles that represent the actual state of the art of power
amplifier in SiGe technology is presented in Table 1.2. The selection was made taking into account the
main parameters of a power amplifier.
Table 1.2: State of the Art of 60 GHz Power Amplifiers in SiGe Technology.
Article
Topology
Process
[µm]
P1dB
[dBm]
Psat
[dBm]
GP
[dB]
PAE
[%]
FoM
[dBm]
Supply
[V]
Pdc
[mw]
[9]
Cascode 2-stg
SiGe 0.25
14.5
15.5
18.8
19.7
46.2
3.3
132
[20]
Cascode
SiGe 0.25
*
14.6
10.7
22
*
3.0
123
[1]
Sing. 2-stg
SiGe 0.18
7.2
8.6
13.5
11.9
31.5
1.9
37.8
[1]
Sing. 3-stg
SiGe 0.18
5.5
7.6
22.5
7.6
36.8
1.9
46.8
[8]
Push-pull diff. 1stg
SiGe 0.13
13.1
20
18
12.7
42.1
4
248
[21]
Class-E
SiGe 0.13
10.5
11.7
4.2
20.9
27.9
1.2
27.6
[22]
diff. 3-stg
SiGe 0.13
19.9
20.5
20.5
19.4
53.3
1.8
353
* Data not available.
The articles [9] and [20] were selected due to the high obtained PAE and to the fact that their
technology is similar to the one in this work. In [9], the main goal was to maximize PAE and output power
under the 1 dB compression point, while the Psat was a second priority. The PA, in this work, consists of
two cascaded stages operating in class AB mode in order to provide high gain, reverse isolation and
efficiency. Matching and filtering networks were implemented with on-chip microstrip transmission lines.
To achieve the required performance, new design techniques were applied. The bias current and the
transistor size (4 in parallel) of the power stage were optimized with parasitic elements so the optimum
5
load for high PAE and output power is close to 50 Ω. Thus, no additional output matching network was
needed and output power and PAE were increased at the same time. A PA should have a linear function
and must not operate in saturation, meaning that to obtain linearity P1 dB and Psat point were moved, as
close as possible. This was done by selecting the bias point and circuitry of the driver stage so at a
certain power level the gain starts to increase slightly before going into compression. The result was
that the difference between the output power levels at 1 dB gain compression and saturation is simply
1 dB. This work has an input matching circuit to provide low return loss and higher linear gain.
In [20] is presented a design methodology and characterization of a 60 GHz class-A power
amplifier. This work presents a study of four topologies of class-A, the common-emitter, the commoncollector, the common-base and the cascode. The study showed that the common-collector is not well
suited for narrow-band power amplifiers, because it tends to be unstable. The common-emitter topology
suffers from the collector-emitter low breakdown voltage due to its high impedance base contact. The
common-base topology shows the highest PAE, because its low impedance base contact leads to a
higher voltage limit based on the collector-base breakdown voltage. Another advantage was the higher
gain that the common-base has in comparison with the common-emitter, as the Miller effect is eliminated
in the first one. Common-base topology has a disadvantage, which is the low input voltage. This leads
to higher losses in the input matching network and a narrow-band characteristic, which cannot be
matched for the complete ISM band. The cascode topology demonstrated the second highest PAE and
the highest gain, making it the selected topology.
Work [1] presents two designs of multi-stage power amplifier for 60 GHz MMIC. The designs
corresponded to a two and a three-stage PA single-ended topology. This has transistors in commonemitter configuration, which enable a higher power driving capability. The input stage in the three-stage
design was a cascade structure, allowing this design to have a better input/output isolation. To push the
output transistors to their full capacity, the optimal load impedance was set to be smaller than the value
obtained from conjugated matching.
Article [8] is interesting because it uses a single stage push-pull amplifier topology, which is
seldom used in such high frequencies. In order to have high power gain, high output voltage and a 3 dB
power pick-up at the antenna port, a two-stage cascode topology in differential mode is used. This mode
of operation enhances the achievable efficiency of the output impedance transformation through a lower
impedance transformation ratio. Also, it allows the power from two amplifiers to be easily combined at
the antenna port. To maximize the breakdown voltage of the output device, the two cascode stages are
in close proximity to each other to provide an ac-ground at the base of the common-base output devices.
This allowed the output voltage to swing ± 2.5 V around the 4 V DC supply voltage without causing the
device to enter in the breakdown region. To ensure a stable operation of the amplifier, a low impedance
was placed at the base. A power detection circuit is used to attenuate the temperature influence in the
output power, as well as the process’ variation that might exist when the cascode stages are biased at
a current density close to their peak fmax.
A 60 GHz class-E power amplifier is presented in [21]. This work’s aim was to develop and,
experimentally, evaluate the design techniques for the implementation of switching mode SiGe PA at
mm-wave frequencies. The class-E PA design consists of an active device that acts as a switch, an
6
output network and an input network. The load network was designed to transform the load impedance
into the appropriate collector impedance for class-E operation. The source network was designed to
provide real low impedance as seen from the base of the active device, which does not necessarily
result in an optimum power match. The main feature of the input network is to improve the switching
behavior of the device.
Work [22] has the best tradeoff between the output power, the power gain and the PAE that was
studied. It uses a 3-stage transformer-coupled, differential, multipath PA topology with integrated input,
inter-stage coupling and 4-way output power combining. This work’s design consists of a single input
stage followed by two-stage amplifiers operating in a parallel-path configuration, and a 4-way power
combiner that couples the differential outputs from each path to a 50  load. The input stage drives the
fully-differential on-chip splitter to match the power in each amplifier. The fully-differential power splitter
couples the first stage to each of the amplifier gain paths. To extend the collector-emitter breakdown
voltage beyond its limit, a differential common-base pairs in each stage were used. In order to improve
stability and reduce base inductance, an adjacent current-return loop using ground paths beneath the
base interconnects was done. The 4:1 power combiner sums the power from each output in the final
stages in an efficient and compact manner.
1.4. Specifications
The standards for 60 GHz applications are recent, and there aren’t fixed specifications to these
systems, yet. Consequently, in order to have challenging specifications for this work it was decided that,
at least, the power amplifier design should equal the output power and the PAE of the state of the art
PAs for the identical technology, 0.25 µm. Therefore, the specifications for this project are given in Table
1.3.
Table 1.3: Power amplifier’s specifications.
F [GHz]
P-1dB [dBm]
PAE [%]
Technology
60
≥ 14.5
≥ 20
IHP SiGe 0.25 µm
7
1.5. Document Organization
This thesis organization is as follows
 Chapter 1: Introduction
The theme of this project is introduced and the work that will be done is described. Additionally,
the state of the art analysis of power amplifiers in SiGe technology for 60 GHz systems and the
discussion of some articles are presented, as well as the specifications of the PA. This document
is composed by four chapters and each one describes the work done along the thesis.
 Chapter 2: Technology Study
A brief technology overview is presented, followed by the technology components study, where
the active devices will be studied at first place, and then, the passive components through its
electrical model. After, electromagnetic simulations will be performed, and to that the technology
profile has to be improved in order to simulate all the components that will be used. Finally, the
electrical model and the EM simulations components results will be compared.
 Chapter 3: Power Amplifier
An introduction of power amplifiers is presented, followed by a study of the transistors working
as class-A. Then, the common emitter and cascode topologies will be studied and compared in
order to choose the topology that will be used. Finally, two power amplifiers will be designed
and compared between them.
 Chapter 4: Power Amplifier with Power Combining
A power combiner brief presentation will be given. Then, its results with technology components
will be presented, as well as, a study to increase the distance between the input ports. After,
two shapes of combiners will be studied in order to see the shape that enables best results. In
the end, the power amplifier with power combining results will be presented.
 Chapter 5: Conclusions and Future Work
As the title suggests, this thesis conclusions will be presented, as well as, the future work.
8
Technology Study
In a mm-wave Power Amplifier design is advisable to study the technology and its components in
the first place. This study should be done in order to fully understand the technology, making easier the
selection of the best topology for the PA design. Additionally, the power amplifier design does not rely
only in the schematic drawing, but also in the layout design. The designer expertise is essential,
especially when a millimeter-wave power amplifier is considered. Additionally, part of the design
constraints are imposed by technology limitations and rules.
Along this chapter, the active devices and the passive components used in the PA design will be
studied using Virtuoso software, developed by Cadence Design System. Due to high working frequency
there is a need to study the passive components through electromagnetic simulations. This will be done
by using Momentum, which is part of Advanced Design System (ADS) software, developed by Agilent
Technologies.
2.1. Technology Overview
As was already mentioned, this work was based on 0.25 µm SiGe technology. This technology
consists in a high performance BiCMOS process, and it is based on SiGe:C npn-HBT’s with up to
190 GHz transient frequencies and up to 220 GHz oscillation frequencies. The used technology offers
3 thin metal layers and two top metal layers with 2 and 3 µm thick, respectively. All of this combined with
a high dielectric thickness, enable high performance RF passive component.
The use of carbon in silicon-germanium reduces boron out diffusion, resulting in a higher boron
doping. A higher boron doping leads to lower intrinsic base resistance and to other advantages such as
higher speed, lower noise, a more stable technology and a higher yield [23]. Carbon influences the
maximum oscillating frequency, which increases by 70%, as can be seen in Figure 2.1.
Figure 2.1: Carbon influences in maximum oscillating frequency (source [23]).
The technology offers a bipolar and a mosfet section, diodes, varicaps, passive elements such
as resistors, capacitors, inductors and transmission lines.
9
2.2. Active Devices
Usually, a power amplifier has a single type of active device, the transistors, which are the only
active components that will be studied.
The technology offers a Bipolar section, which is composed of two kinds of npn HBTs, the npn200
and the npn201. These devices are characterized by its transit frequency, fT, maximum oscillating
frequency, fmax, collector-emitter and collector-base breakdown voltages, BVCEO and BVCBO,
respectively, and these are presented in Table 2.1. Each kind has eight transistors with different sizes
that correspond to a larger number of emitters, and in consequence, to a maximum increase of collector
current, as can be seen Table 2.2. The size of the transistors is the only parameter that can be changed,
all the other are predefined and cannot be changed.
Table 2.1: HBTs main parameters (source [24]).
Device
fT/fmax/BVCEo[GHz/GHz/V]
HBT npn200 fT/fmax=190/190 GHz, BVCEO=1.9V, BVCBO=4.5V
HBT npn201 fT/fmax=180/220 GHz, BVCEO=1.9V, BVCBO=5V
Maximum
Collector
Current [mA]
Table 2.2: Maximum collector current for all the HBTs.
n
1
2
3
4
5
6
7
8
npn200_n
2
4
6
8
10
12
14
16
npn201_n
1.8
3.6
5.4
7.2
9
10.8
13.6
15.4
The transistor schematic is presented in Figure 2.2 and the layout of the smaller and bigger
transistors of each kind is presented in Figure 2.3 and Figure 2.4, respectively.
Figure 2.2: Transistor schematic.
10
Figure 2.3: Layout of the npn200_1 (left) and npn201_1 (right).
Figure 2.4: Layout of the npn200_8 (above) and npn201_8 (below).
In spite of the data, given by the manufacturer, about the transistors, Table 2.1 and Table 2.2, it
is, still, important to study them in order to obtain all the needed data. The reason behind the study
performed for npn201_8 transistor will be explained later on, in this work. Through a DC simulation it is
possible to observe the DC characteristics of the transistor. In Figure 2.5 is presented the collector
current, IC, in function of the collector-emitter voltage, VCE, and in Figure 2.6 is presented the collector
current in function of the base-emitter voltage, VBE. As can be seen in Figure 2.5, the collector-emitter
breakdown voltage, BVCEO, is approximately 1.9 V. When this limit is exceeded, the collector current, Ic,
rises, and the device breaks down, considering that the collector-emitter voltage is bigger than this value
for a certain period. In addition, Figure 2.6 shows that the transistor needs approximately 0.8 volts to
start conducting and after 1V the transistor nonlinear behavior can be seen.
15
Ib=0 uA
Ib=15 uA
Ib=30 uA
Ib=45 uA
Ib=60 uA
Ib=75 uA
Ib=90 uA
Ic [mA]
10
5
0
-5
0
0.5
1
Vce [V]
1.5
Figure 2.5: DC characteristic IC(VCE) of npn201_8.
11
2
120
100
Ic [mA]
80
Vce=0.5 V
Vce=1 V
Vce=1.5 V
Vce=2 V
60
40
20
0
0
2
1.5
1
Vbe [V]
0.5
Figure 2.6: DC characteristic IC(VCE) of npn201_8.
Stability is an important parameter in a PA, so it’s relevant taking this into account when studying
the transistor. A two-port device is unconditionally stable at a given frequency if the real parts of input
and output impedances are greater than zero for all the passive load and source impedances [25]. If the
two-port is not unconditionally stable, it is potentially unstable. This means there are some possible load
and source terminations that can produce input and output impedances, resulting in a negative real part
[25].
From [25] a necessary and sufficient condition for unconditional stability is
2
K
2
1  S11  S22  
2
1
(2.1)
  0
(2.2).
2 S12S21
and
2
B1  1  S11  S22
2
2
The transistor stability was simulated for the maximum transit frequency operation, which is reached
when the transistor is biased with VCE=1.5 V and IC=14.4 mA. The stability factor, K, and the additional
stability factor, B1, of the transistor is shown in Figure 2.7, where it can be seen that from 30 GHz the
transistor is unconditionally stable.
2
1.5
1
0.5
0
0
K
B1
10
20
30
40
Frequency [GHz]
50
60
70
Figure 2.7: Stability factor and additional stability factor of np201_8 for maximum transit frequency.
12
2.3. Passive Elements
To enable high performance integrated circuits designs, the manufacturing process offers several
passive structures, such as resistors, capacitors, inductors and transmission lines. Usually, these
passive components are used in a power amplifier’s design so, these need to be studied, in order to
know the ones that can be used and the ones that cannot.
2.3.1. Capacitors
The available capacitor in the technology is a metal-insulator-metal (MIM) capacitor between
metal 2 and a Tin metal which is used only for this component. This metal is linked to metal 3 to provide
a connection to other components. The capacitor has a scalable rectangular shape, and its capacitance
varies between 1.553 fF and 5.625 pF. Its schematic and layout are shown in Figure 2.8. Here, it is
possible to verify the capacitor’s scalable rectangular shape.
Figure 2.8: Capacitor’s schematic and layout.
In high frequencies it is important to know how the capacitor effective value changes with
frequency. In Figure 2.9 this concept was used for the technology capacitor and it is possible to see that
capacitance almost doesn’t change with frequency. Commonly, a DC block is a capacitor that should
present a reactance between 5 and 1 Ω. Therefore, at high frequencies it should be considered 1 Ω. A
1 Ω reactance capacitor is a 2.65 pF capacitor, meaning that the technology capacitors can be used as
DC block.
Capacitance [pF]
5
4
C=1 pF
C=2 pF
C=3 pF
C=4 pF
C=5 pF
3
2
1
0
0
10
20
30
40
Frequency [GHz]
50
60
Figure 2.9: Capacitor’s different capacitances.
13
70
Other important feature of the capacitor is the quality factor, once it represents its efficiency. So,
the higher the quality factor, the closer it approaches the behavior of an ideal, lossless capacitor. The
quality factor was calculated for the same capacitors as the ones above and the results are shown in
Figure 2.10. It’s possible to see that the smaller capacitor has better quality factor and the bigger one is
the worst between the capacitors studied.
4
10
Quality Factor
3
10
C=1 pF
C=2 pF
C=3 pF
C=4 pF
C=5 pF
2
10
1
10
0
10
0
10
20
30
40
Frequency [GHz]
50
60
70
Figure 2.10: Capacitor’s quality factors.
2.3.2. Inductors
The technology has predefined fixed-size inductors of two types, the ones that have two terminals,
named L2, and others that have a center tap, named L3. There are twelve L2 inductors and thirteen L3.
The schematic and the layout of the L2 inductor are presented in Figure 2.11.
Figure 2.11: Inductor schematic (left) and layout (right).
Usually, in mm-wave frequencies, inductors aren’t used once very small inductances are
necessary. Thus, it will be studied the smallest L2 inductor, with an inductance value of 0.94 nH, which
schematic and layout are represented in Figure 2.11. In order to see if the inductor could be used in
60 GHz, it was studied its resonant frequency which is presented in Figure 2.12. Through Figure 2.12 it
is clear that the inductor has a resonant frequency near 29 GHz, which makes impossible the use of
technology inductors in this project.
14
15
Inductance [nH]
10
5
0
-5
-10
-15
0
10
20
30
40
Frequency [GHz]
50
60
70
Figure 2.12: 0.94 nH L2 inductor resonant frequency.
An ideal inductor doesn’t have resistance or energy losses. However, real inductors have winding
resistance from metal wire that forms the coils. This means, the quality factor of an inductor is the ratio
between its inductive reactance and its resistance at a given frequency. As for the capacitor, the quality
factor is an efficiency measure. This simulation is presented in Figure 2.13, where it can be seen that
for 60 GHz the inductor is not an inductor anymore, once its quality factor is less than zero. Also, in
Figure 2.13 it is possible to see that the best frequencies for the inductor to work are between 10 and
15 GHz.
Quality Factor
50
0
-50
-100
-150
0
10
20
30
40
Frequency [GHz]
50
60
70
Figure 2.13: 0.94 nH L2 inductor quality factor.
2.3.3. Transmission Lines
There are two types of transmission lines in the design kit, differential and single-ended. The first
ones are coplanar lines and the second ones are microstrip lines. These lines have five different
configurations, where the line is in TopMetal1 or TopMetal2 and its grounded plane is in Metal1, Metal2
or Metal3. Only the single-ended will be studied, since there are more discontinuities available.
Therefore, the microstrip lines are the ones that will be used. Both types of transmission lines don’t have
any length limits, but they have limited widths, from 1.8 µm to 20 µm.
The single-ended transmission line type has a normal line, a stub, and four different
discontinuities, a T, a Y, a 45 and a 90 degrees corner. The schematic symbols of these lines are
presented in Figure 2.14 by the same order as was written previously, and their layouts are presented
15
in Figure 2.15. Through Figure 2.15 it is possible to see the ground planes, in blue, and the microstrip
line, in orange.
Figure 2.14: Technology microstrip lines schematic.
Figure 2.15: Technology microstrip lines layout.
The transmission line study’s goal is to observe how the line impedance and losses vary with
width and length variation. This will help to obtain three different lines which will be used in the power
amplifier. The desired lines are a 50 Ω line, and two /4 lines with an impedance of 50 Ω and 502 Ω,
being the last used in the power combiner.
Firstly, it was determined the width that corresponds to a 50 Ω line and the length that reduces
the line losses. For this reason, it was performed an S-Parameter simulation, with the foundry electrical
models, at 60 GHz with a length and width sweeps. The S11 parameter gives the input matching, which
means that the width with lower S11 is the one that corresponds to the pretended impedance. Through
Figure 2.16 it is possible to observe the width that corresponds to 50 Ω is 15 µm. Lower losses are
obtained with a length of 100 µm, as can be seen in Figure 2.17.
-10
W=10 um
W=11 um
W=12 um
W=13 um
W=14 um
W=15 um
W=16 um
S11 [dB]
-20
-30
-40
-50
100
200
300
400
Length [um]
500
600
Figure 2.16: 50 Ω transmission line matching.
16
700
0
S21 [dB]
-0.1
W=10 um
W=11 um
W=12 um
W=13 um
W=14 um
W=15 um
W=16 um
-0.2
-0.3
-0.4
-0.5
100
200
300
400
Length [um]
500
600
700
Figure 2.17: 50 Ω transmission line losses.
The phase of S21 parameter gives the effective electrical length, which allows to determine the
length that a transmission line needs to be a quarter wavelength line. So, through Figure 2.18 it is
possible to see that the effective electrical length almost doesn’t change with width, and the length that
corresponds to a /4 line is between 600 and 700 µm, more precisely 658 µm.
0
S21 Phase [º]
-20
W=10 um
W=11 um
W=12 um
W=13 um
W=14 um
W=15 um
W=16 um
-40
-60
-80
-100
100
200
300
400
Length [um]
500
600
700
Figure 2.18: 50 Ω transmission line effective electrical length.
At last, the previous simulation was repeated in order to obtain a /4 line with an impedance of
502 Ω. The first step was to determine the width that corresponds to an impedance of 502 Ω and
through Figure 2.19 it is possible to see that its value is 6 µm. Then, it was measured the needed length
that corresponds to a /4 line, using S21 parameter’s phase, Figure 2.20, which took values between 600
and 700 µm, more accurately 654 µm. The losses of a line with 6 µm width in function of the length are
presented in Figure 2.21, and it is possible to see that losses increase with length.
-10
S11 [dB]
-20
W=2 um
W=3 um
W=4 um
W=5 um
W=6 um
W=7 um
-30
-40
-50
100
200
300
400
Length [um]
500
600
Figure 2.19: 502 transmission line matching.
17
700
0
S21 [dB]
-0.2
W=2 um
W=3 um
W=4 um
W=5 um
W=6 um
W=7 um
-0.4
-0.6
-0.8
100
300
200
400
Length [um]
700
600
500
Figure 2.20: 502 transmission line effective electrical length.
0
S21 Phase [º]
-20
W=2 um
W=3 um
W=4 um
W=5 um
W=6 um
W=7 um
-40
-60
-80
-100
100
200
300
400
Length [um]
500
600
700
Figure 2.21: 502 transmission line losses.
In conclusion, the technology microstrip lines resemble the classical ones, since a transmission
line with higher impedance requires a small width. The transmission lines’ losses increase with its length,
since larger length results in larger resistance and consequently higher losses. A brief summary of the
study carried out to transmission lines is presented in Table 2.3.
Table 2.3: Transmission lines summary.
Transmission line impedance [Ω] Width [µm] Length [µm] S11 [dB] S21 [mdB]
50
15
100
-45.2
-38.7
50
15
658
-32.9
-257.5
50√2
6
654
-33.12
-306.1
2.4. Electromagnetic Simulations
At high frequencies, the circuitry has different behaviors than at low frequencies, making it
necessary to study the circuit components at these frequencies. Usually, this study is done through
electromagnetic simulations that prove the components electrical model at high frequencies.
EM simulations will be done with a 2.5D simulator available in Momentum ADS. In order to
perform EM simulations of the technology passive components, it is necessary to improve the
18
technology profile since the available one doesn’t allow to simulate all passive components used in the
PA.
This section will not have any images of the technology profile due to non-discloser agreements.
However, it will be presented a study that allows the simulation of the components used in the amplifier.
Passive components EM simulations will be also presented and then compared with the electrical model
results.
2.4.1. Profile Improvement
The technology profile provided by the manufacture is quite simple once it only allows simulating
metals. Therefore, transmission lines and inductors are the only components that can be simulated.
However, other components are used, like capacitors and resistors which have to be simulated as well.
Thus, it is necessary to manage a way to perform EM simulations on these components which will be
explained from now on.
As mentioned in 2.1. the technology has six metals, three thin metal layers, two top metal layers
with 2 and 3 µm thick, respectively, and the MIM capacitor top plate. In order to simulate the skin effect
in these metals, the EM simulator needs their conductivities, since it cannot simulate the skin effect with
the materials resistance per square. This said, the metal conductivity is calculated through

1
Rt
(2.3),
where R is the metal resistance per square and t is the metal thickness. Knowing these parameters,
which are presented in Table 2.4, it is possible to calculate the conductivity through (2.3), presented in
Table 2.4 as well.
Table 2.4: Technology metal conductivity.
M1
M2
CMIM Top Plate
M3
TM1
TM2
R/sq [mΩ/sq]
84 (a)
55 (a)
16x103 (c)
55 (a)
16 (b)
10 (b)
t [µm]
0.58
0.73
0.15
0.73
2
3
σ [S/m]
2.05x107
2.49x107
4.17x105
2.49x107
3.13x107
3.33x107
Notes: (a) W=4.2 µm, L=575 µm, N=10; (b) W=17.5 µm, L=575 µm, N=10; (c) value obtain from [26].
Vias are the connection between two metals in different layers. Thus, it is necessary to calculate
the vias conductivities in order to perform EM simulations. The via conductivity is determined by

h
R w2
(2.4),
where h is the via height, R the via resistance and w2 the via base area (w represents the via width).
These parameters are presented in Table 2.5, as well as the vias conductivity,
19
Table 2.5: Technology vias properties.
Cont
Via1
Via2
ViaMIM
TopVia1
TopVia2
R [Ω/via]
20
5
5
3.97
5
2
h [µm]
1.67
0.9
0.9
0.714
0.9
3
w [µm]
0.36
0.42
0.42
0.42
0.42
0.9
σ [S/m]
6.44x105
1.02x106
1.02x106
1.02x106
1.02x106
1.85x106
The technology has only one type of capacitor CMIM, which is scalable between 1.553 fF and
5.625 pF. This capacitor is made of Metal2 (bottom plate), a dielectric and a Tin metal designated MIM
(top plate). The MIM metal has a thickness of 0.15 µm and a resistance of 16 Ω/sq. From (2.4) the
obtained conductivity is 41.7x107 S/m, which is presented in Table 2.4. The dielectric has a thickness of
58 nm and a dielectric constant of
εr=6.55. In a 2.5D simulator is not possible to insert a layer with a
specific dielectric constant only in one place. Due to that fact, it is required to introduce a new layer in
the profile, with a dielectric constant of εr=6.55. In order to avoid this, the introduced layer has the same
dielectric constant than other layers which is
εr=4.1. The need to maintain the capacity per area leads
to a change in dielectric thickness. Knowing that capacity is given by
A
t
C   0 r
(2.5),
where ε0 is the vacuum permittivity, εr is the relative permittivity, A the area of capacitor plates and t the
capacitor dielectric thickness. Knowing the capacity per area is 1 pF/µm2 and through (2.5),
C  0 r

 1 pF/m2
A
t
(2.6)
From (2.6) and for different thickness,
 r'
t'

 r''
(2.7),
t ''
which leads to obtain a distance between plates of 36 nm and a dielectric constant of 4.1, which means
that ViaMIM height should be 0.714 µm. Once ViaMIM and Via2 are in the same layer, they have the
same conductivity. The ViaMIM properties are presented in Table 2.5.
Four type of resistors are available in the technology, and are designated as Rsil, Rpnd, Rppd and
Rhigh. These are made of polysilicon and because of that resistors can’t be added to the profile, unless
they are considered as metals. Therefore, it is necessary to calculate their resistivity per square. From
process specifications it is known that the resistivity was determined by several parallel resistors,
through
RN  RS
L
W
N
N
 W
(2.8),
where RN is the resistivity, RS is the resistivity per square, L and W are the resistor dimensions, N is the
number of parallel resistors and ΔW is the resistor width variation. Thus, the resistivity per square of
each resistor can be calculated, and they are presented in Table 2.6.
20
Table 2.6: Resistors properties.
Resistors
Rsil
Rpnd
Rppd
Rhigh
RN [Ω]
6.9
210
305
1.6x103
W [µm]
2.8
2.8
2.8
2.8
L [µm]
230
230
230
230
N
10
10
10
10
ΔW [nm]
30
-40
0
-55
RS [Ω/sq]
0.093
2.19
3.71
15.65
Knowing the resistor thickness it is possible to calculate the conductivity of each one. Assuming
that all have the same thickness which is 0.2 µm, through (2.3) are obtained the conductivities presented
in Table 2.7.
Table 2.7: Technology resistors conductivity.
Rsil
Rpnd
Rppd
Rhigh
t [µm]
0.2
0.2
0.2
0.2
RS [Ω/sq]
0.093
2.19
3.71
15.65
σ [S/m]
5.38x10
2.28x10
1.35x10
3.19x10
All the calculated values shown previously are used in the profile, making it now possible to
perform EM simulations of the passive components.
2.4.2. EM Simulations of Passive Components
Starting with a 1 pF capacitor, it was simulated between 1 GHz to 70 GHz with a 1 GHz step. The
EM results as well as the electrical model results are shown in Figure 2.22. Through Figure 2.22, it is
possible to see that the electrical model shows an almost ideal capacitor and the same doesn’t happen
with the EM results. The EM simulation shows a resonant frequency between 27 and 28 GHz.
3
EM result
Electrical model result
Capacitance [pF]
2
1
0
-1
-2
-3
0
10
20
30
40
Frequency [GHz]
50
60
70
Figure 2.22: 1 pF capacitor EM and electrical model results.
Afterwards, it was simulated, with the same frequency sweep than the capacitor, a L2 inductor
with an inductance of 0.92 nH. The inductor EM and electrical model results are presented in Figure
21
2.23 and through it, it is possible to see that the EM simulation has a resonant frequency smaller that
the electrical model. Also, the electrical model has a higher resonance frequency then the EM, due to
lower capacitances.
15
EM result
Electrical model result
Inductance [nH]
10
5
0
-5
-10
-15
0
10
20
30
40
Frequency [GHz]
50
60
70
Figure 2.23: Inductor EM and electrical model results.
As far as it concerns to transmission lines, they were simulated with different widths, 6 and 15 µm.
Each line was simulated several times with different lengths in order to compare them with the results
of the electrical model. Starting with the 50 Ω transmission line, the matching EM and electrical model
results are presented in Figure 2.24, where it can be seen that there aren’t almost any differences. Next,
the line losses, which are presented in Figure 2.25, were analyzed and it can be seen that the difference
between each line increases with its length. At last, it is presented the effective electrical length in Figure
2.26, and both results have almost no differences between them.
Figure 2.24: EM and electrical model matching results for 50 Ω transmission line.
22
Figure 2.25: EM and electrical model losses results for 50 Ω transmission line.
Figure 2.26: EM and electrical model phase results for 50 Ω transmission line.
Concerning 502 Ω transmission line, the EM results for effective electrical length and the
electrical model results are presented in Figure 2.27. Through Figure 2.27, it is possible to see that the
needed length to obtain a /4 line is less than in the electrical model. The matching and losses of the
EM and the electrical model simulations are presented in Figure 2.28 and Figure 2.29, respectively, and
through them it can’t be seen a big difference in both results.
Figure 2.27: EM and electrical model phase results for 502 Ω transmission line.
23
Figure 2.28: EM and electrical model matching results for 502 Ω transmission line.
Figure 2.29: EM and electrical model losses results for 502 Ω transmission line.
Concluding the transmission line study, the electrical model results aren’t too different from the
electromagnetic ones. This can be confirmed through Table 2.8, where it is presented the electrical
model and the EM results for the studied lines. Analyzing Table 2.8, the largest difference between the
EM and the electrical model results is the length of the /4 transmission lines.
Table 2.8: Electrical model and electromagnetic results for the required transmission lines.
Electrical model results
EM results
Transmission line
impedance [Ω]
Width [µm]
Length [µm]
S11 [dB]
S21 [mdB]
Length [µm]
S11 [db]
S21 [mdB]
50
15
100
-45.2
-38.7
100
-44.83
-50
50
15
658
-32.9
-257.5
644
-32.44
-330
502
6
654
-33.12
-306.1
640
-31.50
-370
This study enabled to know which components can be used at 60 GHz. As an example, the 1 pF
capacitor could be used by its electrical model, however, the same couldn’t be done as can be seen by
its electromagnetic simulation results. Concerning the other components, significant differences weren’t
24
found. From here, the lines electrical model could be used, but, instead, the EM results were used, once
the design kit hasn’t available the discontinuities electrical models.
2.5. Summary
Through this chapter an overview of the technology was presented, as well as a technology study
regarding the components that will be used in the power amplifier design.
The study began with active devices, which in this case were transistors, and where the main
concern was its DC characteristics and stability.
Then, a study of the capacitor and the inductor was preformed, in order to know the resonant
frequency and the quality factor of both components. After, the transmission lines were studied to obtain
the width that corresponds to an impedance of 50 Ω and 502 Ω, and the length that corresponds to a
/4 transmission line, thus, obtaining three transmission lines. Since the working frequency is 60 GHz,
it is necessary to do an electromagnetic simulation, due to the parasitic effects. For that reason, the
technology profile had to be improved once it only allowed to simulate metals. At last, the passive
components were studied electromagnetically and then compared with the electrical model.
25
26
Power Amplifier
A power amplifier can be designed to deliver the maximum power to a load, to have maximum
efficiency or to be linear. It can also be designed to achieve the best tradeoff between two or more of all
of these parameters. However, the PA design must take into account the target application in order to
fulfill the application specifications.
The power amplifier architecture can be divided into two parts, the amplification block and the
impedance transformation block. The first one consists, basically, in the active device in a certain
working class. The second one is used to transform both input and output impedance of the active
device, which is done through passive networks, as illustrated in Figure 3.1.
Low power side
Amplification
Passive
input
network
High power side
Passive
output
network
Active
Device
Figure 3.1: Simplified diagram of a single stage power amplifier.
The power amplifiers are separated in different working classes, each with a tradeoff between its
efficiency and linearity. Two types of working classes can be addressed, the conventional ones
composed by classes A, B, AB and C and the switched ones composed by classes D, E and F. In the
conventional ones, the active device works as a current source, and in the switched ones, the active
device works as a switch.
In theory, a class-A amplifier has a linear behavior, ergo, the best linearity, since the active device
is always conducting. The other conventional classes have better efficiency than class-A, since the
active device does not work through all the conducting period. This results in a lower mean value of the
current and the consumed power, while having worst linearity than class-A. The switched classes have
really good efficiency, nearly 100%.
PAs for 60 GHz must be designed with adequate linearity for the specific modulation scheme that
is used, while delivering adequate output power and efficiency for long battery life [2]. Considering this
and what was said previously, the development of a class-A power amplifier will be studied in this work.
Therefore, in this chapter the class-A operating mode will be presented, followed by the study of the
transistors in a class-A operation in order to select the best transistor or set of transistors that enable
the specification’s fulfillment. Then, common-emitter and cascode topologies will be studied and
compared, in order to choose the topology with best tradeoff between output power and power added
efficiency. Consequently, two power amplifiers will be designed and their obtained values will be
presented, so they can be compared between each order and with the state of art amplifiers.
27
3.1. Class-A Operation Mode
A class-A power amplifier is a linear amplifier, since it works in the linear region. Therefore, the
bias needs to be chosen in order to the amplifier work within this region. This is done by setting the bias
voltage exactly in the middle between the saturation voltage, VK, and the breakdown voltage. Further
the collector current should have a maximum excursion of IC max, as shown in Figure 3.2, where a
maximum efficiency of 50% can be achieved. The signal’s level must not exceed these two limits in
order to avoid the output power saturation.
Class-A has some advantages and disadvantages. In theory, its current output signal doesn’t
suffer distortion, and this has a high gain as an advantage. A major drawback of this structure is that for
zero input power signals, the amplifiers still dissipate DC power. In other words
PDiss  PDC
(3.1).
The wasted power in a standby period causes two problems. First, in the battery-operated equipment,
it has a severe impact on the battery lifetime and should therefore be avoided. Second, any wasted
power in the circuit is dissipated in the active devices, increasing their operating temperatures and, thus,
the chance of failure.
Ic
Ic max
Ic max
2
VDC
VK
2*VDC-VK Vce
Figure 3.2: Class-A bias point for a bipolar transistor.
3.2. HBT in Class-A Study
Knowing the target technology and the concept of the class-A power amplifier makes it easier to
study its composing blocks, starting with the amplification block. Basically, this block consists in the
active device, so the HBTs will be studied with ideal components, in this section.
A class-A amplifier can be designed in four different topologies such as common-base, commoncollector, common-emitter and cascode. From [20] it is known that the common-base presents a very
low input impedance which will lead to high losses in the input matching network. Through [20] it is also
possible to see that the common-collector is not a good choice, because it tends to be unstable. So,
there are left two topologies, common-emitter and cascode that will be studied later. Like other
28
topologies, common-emitter has a problem too - the low collector-emitter breakdown voltage. Even with
this limitation, it can achieve good values for PAE and output power.
The transistors, in this technology, were studied in the selected topology. Ideal components were
used in order to see the best tradeoff between PAE and output power that can be reached by HBTs.
This study was done with the schematic presented in Figure 3.3. There is a particularity about this
schematic, which is the use of a LC network. The LC network is a low-pass filter and is used to tune the
output of the transistor. This network resonant frequency is given by
0 

1
1
 f0  0 
2 2 LC
LC
(3.2),
where f0 is the working frequency which is 60 GHz.
Using (3.2) the inductor and capacitor values for 60 GHz can be calculated. Thus, it was set a
value for the inductor and, after, the capacitor’s value was determined. To have the best possible tune
and to reject the third harmonic, these values were adjusted through a simulation and the obtained
values were L=15 pH and C=0.469 pF.
The transistor bias point was chosen in order to make the circuit work in class-A. The collectoremitter breakdown voltage is 1.9 V and the selected VCC value was 1 V. The current IB was selected in
order to obtain half of the collector current maximum and those values are presented in Table 2.2.
Figure 3.3: Class-A transistor study schematic.
After setting tune and bias issues, a harmonic balance simulation was performed to determine
the load that maximizes the tradeoff between PAE and output power. This study was done for smaller
and bigger transistors of each kind, the npn200_1 and 8, and the npn201_1 and 8.
In Table 3.1 are presented the output power, the PAE and the power gain at 1 dB compression
point for the load that maximizes the required tradeoff. Through this, it is clear that npn201 transistors
show better tradeoff than npn200. Although npn200 transistors have higher output power, its efficiency
is not as good as npn201. The difference between this two types of transistors, considering their output
powers, is not significant when choosing one or another. Even though power gain is not a main
parameter in the transistor’s choice, it was also considered, and, as can be seen in Table 3.1, npn201
has higher power gain than npn200.
29
Table 3.1: Obtained values for the load that maximizes the tradeoff between PAE and P out.
RL [Ω]
Pout [dBm]
PAE [%]
Gp [dB]
npn200_1
648
-5.72
20.70
5.09
npn200_8
80
3.25
20.69
5.16
npn201_1
663
-5.9
23.67
6.08
npn201_8
89
2.89
22.37
5.85
HBT
After selecting the npn201 transistors, a new study for all types of npn201 transistors was
performed. This new study is similar to the preceding one, except that, now, the transistor input
impedance will also be determined. The impedance can be divided into resistance, its real part, and
reactance, its imaginary part. In other words
Z  R  jX
(3.3),
where
R  Re(Z )
,
X=Im(Z)
(3.4).
It is important to know the amplification block input impedance in order to design the input
matching network.
For this study, the used schematic is the same as the previous one as well as the harmonic
balance simulation. The goal is to obtain the optimal load, R L, namely, the one that maximizes the
tradeoff between PAE and Pout. The obtained values of RL, Pout, PAE, Gp and Zin at 1 dB compression
point are shown in Table 3.2. Considering Table 3.2, it is clear that the output power increases along
with the size of the transistor, while the efficiency decreases with the size of the transistor. So, the
transistor with higher output power is the biggest one and with higher efficiency is the smallest one. It is
possible to see a larger variation in Pout than in PAE. Therefore, the transistor with best tradeoff between
Pout and PAE is the npn201_8. Despite the fact that this HBT has the best tradeoff, there is an associated
problem, its input impedance.
Subsequently, it was studied a set of npn201_8 in parallel in order to see how much output power
can be obtained without having a large decrease in efficiency. The results are presented in Table 3.3
and, as expected, the output power increases with the number of HBTs in parallel, unlike efficiency, that
decreases.
If the only criterion was the output power, the set of six npn201_8 in parallel would be selected,
but this is not the case. It is important to look to other parameters like power gain, efficiency, input
impedance and optimum load resistance, as well. Looking at these parameters and knowing that at the
power amplifier end it will be a power combiner with an input impedance of 50 Ω, the best choice is,
perhaps, the set of two npn201_8 in parallel. Once this set has an optimum load of 52 Ω, it is not
necessary to have an output matching network. Another advantage of this set, when comparing it with
other sets of transistors, is the higher input impedance.
30
Table 3.2: Obtained values for the load that maximizes the tradeoff between PAE and P out.
Zin [Ω]
HBT
RL [Ω]
Pout [dBm]
PAE [%]
Gp [dB]
R [Ω]
X [Ω]
npn201_1
663
-5.9
23.67
6.08
144.26
-69.11
npn201_2
340
-2.98
23.20
5.91
74.19
-34.38
npn201_3
270
-2.67
22.86
5.67
50.03
-19.28
npn201_4
198
0.01
22.61
5.71
37.86
-14.46
npn201_5
149
0.94
22.52
5.79
30.61
-12.12
npn201_6
128
1.72
22.46
5.76
25.74
-9.64
npn201_7
120
2.42
22.39
5.66
22.24
-7.34
npn201_8
89
2.89
22.37
5.85
19.72
-7.64
Table 3.3: Obtained values for the load that maximizes the tradeoff between PAE and P out.
Zin [Ω]
HBTs in
parallel
RL [Ω]
2
52
5.95
22.25
3
33
7.66
4
25
5
6
Pout [dBm]
PAE [%]
Gp [dB]
R [Ω]
X [Ω]
5.68
9.83
-3.31
22.03
5.76
6.53
-2.33
8.93
21.92
5.73
4.88
-1.73
20
9.83
21.76
2.75
3.89
-1.37
16
10.59
21.68
5.79
3.24
-1.20
3.3. Common-emitter Vs Cascode
According to the previous section, it is now known that the power stage will have two transistors
npn201_8 in parallel. Due to that fact, it will be studied the common emitter and the cascode topologies
with two transistors in parallel and ideal components. This study will allow to select the topology that
has the best tradeoff between output power and efficiency. Instead of using ADS, it will be used the
Cadence software due to an upgrade of the design kit.
Firstly, the PA in common-emitter mode will be studied and the used schematic is represented in
Figure 3.4, where capacitors and inductors are 1 µF and 1 µH, respectively. The LC network is not used,
as can be seen in Figure 3.4, since it could not be replicated in the final layout. The VCC is 1 V and the
VBB is set with a value that enables the transistor to have a collector current of 14.4 mA. Figure 3.4
doesn’t show two transistors in parallel, because there is an option that allows to put several instances
in parallel, which is indicated by letter ‘m’ visible in Figure 3.4. The power amplifier PFR is shown in
Figure 3.4.
31
Figure 3.4: PA in common-emitter mode with ideal components.
The transistor is not unconditionally stable in wideband, so, it is important to see if there is any
change relatively to the stability factor and the additionally stability factor, which are presented in Figure
3.5. Through Figure 3.5, it can be seen that the PA is not unconditionally stable in wideband, as
expected, since neither is the transistor. The output power, the input power and the power gain of the
power amplifier in common-emitter mode are presented in Figure 3.6. In Figure 3.6 it can be seen the
values of these parameters at 1 dB compression point. The PAE is shown in Figure 3.7, as well as the
1 dB compression point, which is marked by a black cross. Also, it can be seen that this mode has an
efficiency of 23.82%.
2
1.5
1
0.5
K
B1
0
0
10
20
30
40
Frequency [GHz]
50
60
70
Figure 3.5: Stability factor and additionally stability factor of PA in common-emitter mode.
10
0
-10
Output Power [dBm]
Input Power [dBm]
Power Gain [dB]
8.16 dBm
2.48 dBm
5.68 dB
-20
-30
-40
-30
-25
-20
-15
-10
Psav [dBm]
-5
0
5
Figure 3.6: Power results of PA in common-emitter mode.
32
10
25
PAE [%]
20
15
23.82%
10
5
0
-30
-25
-20
-15
-10
Psav [dBm]
-5
0
5
10
Figure 3.7: PA in common-emitter mode efficiency.
Since the study of common-emitter is finished, it will be studied the cascode topology. The
schematic of the PA in cascode mode is presented in Figure 3.8, where the capacitors and the inductors
have the same size as the ones used in the common-emitter. The cascode topology enables an increase
in VCC once it has two transistors in series, meaning that, if setting 2 V in VCC, each transistor had 1 V
in VCE. However, the upper transistor needs to have a VCE higher than the lower one, in order to have
more output power. This is done by checking if the upper transistor’s VCE doesn’t exceed its limit, when
adjusting the VBB1 source. At last, the VBB2 source is set to inflict a collector current of approximately
14.4 mA to transistor Q1.
Figure 3.8: PA in cascode mode with ideal components.
Firstly, it can be seen the stability factor in Figure 3.9, where it is possible to see that the PA is
unstable at low frequencies, since K factor is lower than -1. In order to visualize if the instability is at the
input or at the output or even at both, S11 and S22 reflection coefficients, represented in Figure 3.10,
were analyzed. Figure 3.10 shows that the instability is at the output since the S 22 parameter is higher
than 1 from DC to 40 GHz.
33
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
K
B1
-1.2
0
10
20
30
40
Frequency [GHz]
50
60
70
Figure 3.9: Stability factor and additionally stability factor of PA in cascode mode.
0.5
S-Parameters [dB]
0
-0.5
-1
-1.5
-2
-2.5
S11
S22
-3
0
10
20
30
40
Frequency [GHz]
50
60
70
Figure 3.10: Cascode S11 and S22 parameters.
Although the amplifier is unstable, it is important to see the power results in order to compare with
the PA in common-emitter. The output and input power and the power gain are presented in Figure 3.11,
and the power added efficiency in Figure 3.12. In Figure 3.11 and Figure 3.12 the 1 dB compression
point is highlighted. Now, knowing the available power source at 1 dB compression point, it is possible
to verify if the transistor Q1 VCE exceeds the 2 V. The collector-emitter voltage of transistor Q1 is
presented in Figure 3.13 and it is visible that the VCE isn’t higher than 2 V, enabling to maintain the
chosen PFR.
20
10
0
-10
Output Power [dBm]
Input Power [dBm]
Power Gain [dB]
6.62 dBm
-4.58 dBm
11.19 dB
-20
-30
-40
-30
-25
-20
-15
-10
Psav [dBm]
-5
Figure 3.11: Cascode power results.
34
0
5
20
PAE [%]
15
10
12.34%
5
0
-30
-25
-20
-15
-10
Psav [dBm]
-5
0
5
Figure 3.12: Cascode PAE.
Voltage [V]
2.5
2
1.5
1
0.5
0
2
4
6
8
10
Time [ps]
12
14
16
18
Figure 3.13: Transistor Q1 collector-emitter voltage.
Concluding this study, the power results at 1 dB compression point are presented in Table 3.4.
Through Table 3.4 is possible to see that the common-emitter has a higher output power, PAE, and a
lower power gain than the cascode. In this work, it is required to achieve the best possible relation
between output power and efficiency. This can be seen in Table 3.4, which led to choosing the commonemitter instead of cascode.
Table 3.4: Common-emitter and cascode power results.
POUT [dBm]
PIN [dBm]
GP [dB]
PAE [%]
Common-emitter
8.16
2.48
5.68
23.82
Cascode
6.62
-4.58
11.19
12.34
3.4. Simulation Results
From the previous section it is, now, known that the common-emitter is the chosen topology.
Therefore, the common-emitter will be studied with the technology components instead of the ideal ones,
as done previously. The amplifier schematic is shown in Figure 3.14 where it is used a /4 transmission
line to bias the transistor base and collector and a 150 fF capacitor as a DC block. A T discontinuity
should be used after the transmission line, but that wasn’t possible once the design kit hasn’t available
the discontinuities electrical models.
35
Figure 3.14: Class-A power amplifier in common-emitter mode with technology components.
To work in class-A mode, the amplifier should have a VCE of 1 V, so the VCC is set to 1.1 V in order
to compensate the existing losses in the passive components. The VBB is set with a value that allows
the transistors’ block to work in class-A, which means that it should have a collector current of 14.4 mV.
Form section 2.2. it is known that the transistor is not unconditionally stable in all frequency band,
so it is important to see if there is any kind of instability in wideband. This is done through S-parameters,
which are presented in Figure 3.15, where it can be seen an instability near 15 GHz. This instability has
to be solved now, in order to move forward in the PA design. The S11 instability is due to the output load,
in contrast with the S22 instability which is caused by the negative resistance that is presented by the
input side. Therefore, it started to try solving the output instability by adding a resistor after the VBB
source and a capacitor to ground. This way, instead of “seeing” the perfect AC ground of the voltage
source, the AC signal “sees” a resistor and other way to ground. This solution is presented in Figure
3.16 where it is visible that the used resistor is a 30.2 Ω Rsil and the capacitor is equal to the ones used
as DC blocks.
S-Parameters [dB]
5
S11
S22
0
-5
-10
0
10
20
30
40
Frequency [GHz]
50
Figure 3.15: S11 and S22 parameters results.
36
60
70
Figure 3.16: Power amplifier with the solution to solve the instability problem.
The solution presented in Figure 3.16 solved the output and the input instability, as can be seen
through S11 and S22, presented in Figure 3.17. The output power, input power and power gain, are
presented in Figure 3.18 and power added efficiency in Figure 3.19. Comparing this and the PA with
ideal components results, one can notice a decrease in power gain, due to the components’ losses.
Concerning efficiency, not only it decreases, due to the components’ losses, but also increases in VCC,
from 1 V to 1.1 V.
S-Parameters [dB]
2.5
S11
S22
0
-2.5
-5
-7.5
-10
0
10
20
30
40
Frequency [GHz]
50
60
70
Figure 3.17: S11 and S22 parameters of the Figure 3.16 circuit.
10
0
-10
Output Power [dBm]
Input Power [dBm]
Power Gain [dB]
8.14 dBm
3.32 dBm
4.82 dB
-20
-30
-40
-30
-25
-20
-15
-10
Psav [dBm]
-5
0
5
Figure 3.18: PA power results with technology components.
37
10
25
20.72%
PAE [%]
20
15
10
5
0
-30
-25
-20
-15
-10
Psav [dBm]
-5
0
5
10
Figure 3.19: PA efficiency with technology components.
After solving the instability problem and seeing that there are few differences between the PA
with ideal components and with technology components, the best reality approach that can be obtained
is replacing the components’ electrical models by their electromagnetic simulation results. The bias
network, which is composed with a T discontinuity, a transmission line and a capacitor to ground, is
represented in Figure 3.20. Considering that ports 2 and 3 are matched when presenting a value lower
than -15 dB, it can be established that they are matched to 50 Ω at 60 GHz, Figure 3.21. However, these
ports are fully matched around 55 GHz. The same network can be used for base and collector biasing.
The bias network was adjusted in order to present a parallel open circuit at 60 GHz to the AC signal,
when crossing from port 2 to 3. The capacitor’s function is to provide a short circuit at the transmission
line point it connects, so any added component at port 1 won’t disturbs the AC signal.
Figure 3.20: Bias network layout.
S-Parameters [dB]
0
-5
S22
S32
S33
-16.92 dB
-1.37 dB
-17.06 dB
-10
-15
-20
-25
0
10
20
30
40
Frequency [GHz]
50
60
70
Figure 3.21: Bias network S-parameters.
The capacitor, that works as a DC block, was simulated between two 50 Ω transmission lines,
Figure 3.22, in order to account for the added losses. The DC block S-parameters, Figure 3.23, show
38
significant insertion losses, 0.42 dB, and an input matching value that allows to consider it matched to
50 Ω.
Figure 3.22: DC block with two 50 Ω transmission lines layout.
S-Parameters [dB]
0
-5
S11
S21
-16.64 dB
-0.42 dB
-10
-15
-20
-25
0
10
20
30
40
Frequency [GHz]
50
60
70
Figure 3.23: DC block S-parameters.
The extraction of bias network and DC block electromagnetic results, led to use them instead of
the electrical models. This can be seen in Figure 3.24, where it is represented the PFR circuit, as well.
Consequently, the power amplifier stability was checked, as done before, and it is represented in Figure
3.25, where it is possible to see that there is not any kind of instability. Finally, the power outcome was
shown in Figure 3.26 and Figure 3.27, where it can be seen a decrease in all parameters, when
comparing them with Figure 3.18 and Figure 3.19. The output power decrease can be explained by the
fact that the bias network and DC block present an impedance of 37.94-j1.18 Ω to the transistor, instead
of 50 Ω. The bias network has insertion losses of 1.28 dB, which contributes for the power gain reduction.
This leads to a power added efficiency decrease.
Figure 3.24: PA with EM model components.
39
0
S11
S22
S-Parameters [dB]
-2
-4
-6
-8
-10
-12
-14
0
10
20
30
40
Frequency [GHz]
50
60
70
Figure 3.25: S11 and S22 parameters of the PA with EM model components.
10
0
-10
Output Power [dBm]
Input Power [dBm]
Power Gain [dB]
7.54 dBm
4.94 dBm
2.60 dB
-20
-30
-40
-30
-25
-20
-15
-10
Psav [dBm]
-5
0
5
10
Figure 3.26: Power results of the PA with EM model components.
12
10.25%
PAE [%]
10
8
6
4
2
0
-30
-25
-20
-15
-10
Psav [dBm]
-5
0
5
10
Figure 3.27: PAE of the PA with EM model components.
The input power should be approximately equal to the available power source, which doesn’t
happen when analyzing Figure 3.26, because the input is not matched. Therefore, an input matching
network will be used in order to match the power amplifier input, which has an impedance of
9.83+j*3.31 Ω, to 50 Ω.
The obtained network is composed of technology components, more precisely, an open stub and
a transmission line, as can be seen in Figure 3.28. The network dimensions are presented in Table 3.5,
where widths are equal in order to avoid any layout discontinuities. Subsequently, it can be seen,
40
through Figure 3.29, that the power amplifier input is matched. The input matching network enables
more power gain, Figure 3.30, once there is less power loss at the input. This leads to a slightly increase
in PAE, as seen in Figure 3.31.
Figure 3.28: PA with an input matching network.
Table 3.5: Input matching network dimensions.
Stub
Line
Width [um]
15
15
Length [um]
374
142
S-Parameters [dB]
0
S11
S22
-5
-10
-15
-20
-25
0
10
20
30
40
Frequency [GHz]
50
60
70
Figure 3.29: PA S11 and S22 reflection coefficients.
10
0
-10
Output Power [dBm]
Input Power [dBm]
Power Gain [dB]
7.56 dBm
4.33 dBm
3.23 dB
-20
-30
-40
-30
-25
-20
-15
-10
Psav [dBm]
-5
0
5
Figure 3.30: Power results of the PA with an input matching network.
41
10
15
PAE [%]
10
5
0
-5
-30
11.82%
-25
-20
-15
-10
Psav [dBm]
-5
0
5
10
Figure 3.31: PAE of the PA with an input matching network.
As it was said previously, the power amplifier does not need an output matching network, once
its optimal load is near 50 Ω. Knowing this and considering the study performed up to here, it is, now,
possible to make the power amplifier layout, which is presented in Figure 3.32. In order to have a better
reality approximation of the power amplifier results, it was performed an electromagnetic simulation over
all the passive structure. The S-parameters’ results are presented in Figure 3.33, where it is visible that
input is matched. The power results are presented in Figure 3.34 and when comparing them with Figure
3.30, it is possible to see that power gain decreases due to, probably, the T discontinuity dissipation
losses of the input matching network, since it was not accounted in Figure 3.28 . This leads to a decrease
in the power added efficiency, as can be seen in Figure 3.35.
Figure 3.32: Power amplifier’s layout.
42
S-Parameters [dB]
-5
-10
-15
-20
57
S11
S22
58
59
60
61
62
Frequency [GHz]
63
64
65
66
Figure 3.33:S11 and S22 parameters of the PA with EM networks simulated.
10
0
-10
-20
Output Power [dBm]
Input Power [dBm]
Power Gain [dB]
7.60 dBm
5.07 dBm
2.53 dB
-30
-40
-30
-25
-20
-15
-10
Psav [dBm]
-5
0
5
10
Figure 3.34: Power results of the PA with EM networks simulated.
15
10.21%
PAE [%]
10
5
0
-5
-30
-25
-20
-15
-10
Psav [dBm]
-5
0
5
10
Figure 3.35: PAE of the PA with EM networks simulated.
Since it is not possible to perform an EM simulation over the transistors block, which layout is
represented in Figure 3.36, it was extracted its layout parasitic capacitances. This was done in order to
obtain the best reality approach, through the available data and tools. The parasitic capacitances
influence the obtained results, so it is better to observe the S11 and S22 reflection coefficients, Figure
3.37. Through Figure 3.37 it is visible that there is a slightly difference, since S11 decreases, it is more
negative, and S22 increases. The power results are presented in Figure 3.38 and Figure 3.39 and it can
be seen that the parasitic capacitances have a significant influence in the final results. So they should
have been considered from the beginning.
43
Figure 3.36: Transistors block layout.
S-Parameters [dB]
-5
-10
-15
-20
-25
57
S11
S22
58
59
60
61
62
Frequency [GHz]
63
64
65
66
Figure 3.37: S11 and S22 parameters of the PA with transistors layout extraction.
10
0
-10
Output Power [dBm]
Input Power [dBm]
Power Gain [dB]
6.97 dBm
5.09 dBm
1.88 dB
-20
-30
-40
-30
-25
-20
-15
-10
Psav [dBm]
-5
0
5
10
Figure 3.38: Power results of the PA with transistors layout extraction.
10
PAE [%]
5
0
-5
-10
-30
6.55%
-25
-20
-15
-10
Psav [dBm]
-5
0
Figure 3.39 PAE of the PA with transistors layout extraction.
44
5
10
The transistors block parasitic capacitances result in an output power reduction. Thus, it is
important to increase this power, and to do that, the collector-emitter voltage, Figure 3.40, was
increased. Therefore, the VCC was increased in 1.2 V and it was checked if the collector-emitter voltage
didn’t pass its’ limit, Figure 3.41, which doesn’t happen. At the same time, the VBB source was set in
order to the transistor block maintain the collector current. Consequently, the output power increases
more than 0.5 dB, as can be seen in Figure 3.42. The power gain increases slightly, leading to an
increasing efficiency, Figure 3.43.
Voltage [V]
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0
2
4
6
8
10
Time [ps]
12
14
16
18
14
16
18
Figure 3.40: VCE for a VCC of 1.1 V.
Voltage [V]
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0
2
4
6
8
10
Time [ps]
12
Figure 3.41: VCE for a VCC of 1.2 V.
10
0
-10
Output Power [dBm]
Input Power [dBm]
Power Gain [dB]
7.67 dBm
5.69 dBm
1.98 dB
-20
-30
-40
-30
-25
-20
-15
-10
Psav [dBm]
-5
0
Figure 3.42: Power results for a VCC of 1.2 V.
45
5
10
8
PAE [%]
6
4
2
0
-2
-4
-30
6.92%
-25
-20
-15
-10
Psav [dBm]
-5
0
5
10
Figure 3.43: PAE for a VCC of 1.2 V.
The power amplifier obtained results demonstrate small power gain. Although power gain is not
a concerning issue, it was studied a way to improve it and at the same time to maintain the output power.
This was done adding two stages in cascade in the amplifier, where the second stage is the previous
power amplifier. It was considered to put a smaller transistor in the first stage, but it would start to
compress the signal before the second one, due to the second stage low input impedance. A small
transistor would need a larger load at the output, making it difficult to match to the second stage input
impedance. This would result in an impedance transformation network with high losses. Therefore, the
two stages were set to be equal, in order to the impedance transformation network have few losses.
Firstly, the two stages were placed together with the input matching network used in the one stage
amplifier. This network was used as an impedance matching network, so the first stage “sees” an
impedance of 50 Ω. This amplifier, with technology components can be seen in Figure 3.44, and the S11
and S22 reflection coefficients in Figure 3.45. Through it, one can conclude the amplifier is unstable at
lower frequencies, so this problem has to be solved in the first place. This was done like the solution
presented in Figure 3.16, but, in this case, it was necessary a slightly big resistor, 40 Ω, in the second
stage. In Figure 3.46, both instabilities are solved, but S11 parameter shows a certain tendency to be
unstable. This wasn’t changed since the EM components simulations results have more losses than its
electrical model, causing a decrease in gain and improving, slightly, the stability. Still, in Figure 3.46, the
input is not matched at 60 GHz, and the networks will be adjusted later, when using the components
EM simulations results.
Figure 3.44: 2 stages power amplifier.
46
20
S11
S22
S-Parameters [dB]
10
0
-10
-20
-30
-40
-50
0
10
20
30
40
Frequency [GHz]
50
60
70
Figure 3.45: 2 stages PA S11 and S22 parameters.
0
S-Parameters [dB]
S11
S22
-10
-20
-30
-40
0
10
20
30
40
Frequency [GHz]
50
60
70
Figure 3.46: S11 and S22 parameters of 2 stages PA with stability solution.
Secondly, the technology components were replaced by the EM components simulation results,
as previously. This change doesn’t affect too much the amplifier’s stability, actually, it improves it slightly,
as can be seen in Figure 3.47. Through this same figure, it is, still, possible to see that the input is now
matched at 60 GHz. The impedance matching network was adjusted, Table 3.6, in order to have the
best power results without losing the input matching, as can be seen in Figure 3.48. The power results
are shown in Figure 3.49, where it is possible to see that the power gain significantly increases and, the
output power decreases almost 0.5 dB, when comparing it with Figure 3.30. The amplifier efficiency is
represented in Figure 3.50 and it decreases more than 1.5% when comparing it with Figure 3.31.
0
S-Parameters [dB]
S11
S22
-5
-10
-15
-20
0
10
20
30
40
Frequency [GHz]
50
60
Figure 3.47: S11 and S22 parameters of the PA with EM components.
47
70
Table 3.6: Impedance transformation network dimensions.
Stub
Line
Width [um]
15
15
Length [um]
452
86
S-Parameters [dB]
0
S11
S22
-5
-10
-15
-20
0
10
20
30
40
Frequency [GHz]
50
60
70
Figure 3.48: S11 and S22 parameters of the PA with the ITN adjusted.
10
0
-10
Output Power [dBm]
Input Power [dBm]
Power Gain [dB]
7.03 dBm
-1.64 dBm
8.66 dB
-20
-30
-40
-30
-25
-20
-15
-10
Psav [dBm]
-5
0
5
10
Figure 3.49: Power results of PA with matching networks.
15
PAE [%]
10
5
0
-5
-30
10.12%
-25
-20
-15
-10
Psav [dBm]
-5
0
5
10
Figure 3.50: PAE of PA with matching networks.
Finally, it is represented in Figure 3.51 the power amplifier’s layout. Unlike the previous one,
where all passive structure was electromagnetically simulated together, the same will not happen once
the simulation is too large for the server. Thus, each network was simulated separately, in DC, and
between 57 GHz and 66 GHz, more precisely the 60 GHz band. The transistors’ block, which is the
48
same as the Figure 3.36, extraction was used. The obtained S-parameters are shown in Figure 3.52,
where it can be seen that the input is matched. The obtained power results are represented in Figure
3.53, and comparing them with the results of the 1 stage PA, Figure 3.38, it can be seen that the 2
stages PA has more power gain than the 1 stage PA, but it has less output power. The 2 stages PA has
more efficiency, Figure 3.54, since the difference between power gains is larger than the difference
between output powers.
Figure 3.51: 2 stages power amplifier’s layout.
S-Parameters [dB]
-6
-8
-10
-12
-14
S11
S22
-16
-18
57
58
59
60
61
62
Frequency [GHz]
63
64
65
66
Figure 3.52: S11 and S22 of 2 stages PA.
10
0
-10
Output Power [dBm]
Input Power [dBm]
Power Gain [dB]
6.62 dBm
0.66 dBm
5.96 dB
-20
-30
-40
-30
-25
-20
-15
-10
Psav [dBm]
-5
Figure 3.53: 2 stages PA power results.
49
0
5
10
10
PAE [%]
7.74%
5
0
-5
-30
-25
-20
-15
-10
Psav [dBm]
-5
0
5
10
Figure 3.54: 2 stages PA efficiency.
2
Vce1
Vce2
1.8
Voltage [V]
1.6
1.4
1.2
1
0.8
0.6
0.4
0
2
4
6
8
10
Time [ps]
12
14
16
18
Figure 3.55: VCE1 and VCE2 when VCC=1.2 V.
Then, it was increased the VCC to 1.2 V, as done to the previous power amplifier. It is, then,
necessary to check if the collector-emitter voltage of each transistors’ block don’t exceed its limits and
through Figure 3.55 it is possible to confirm that they don’t. Therefore, it was possible to obtain better
results, Figure 3.56 and Figure 3.57, than when VCC was equal to 1.1 V. When comparing it with the 1
stage amplifier, Figure 3.42 and Figure 3.43, the only difference is that, this time, the output power is
smaller.
10
0
-10
Output Power [dBm]
Input Power [dBm]
Power Gain [dB]
7.27 dBm
1.11 dBm
6.16 dB
-20
-30
-40
-30
-25
-20
-15
-10
Psav [dBm]
-5
0
Figure 3.56: 2 stages PA power results when VCC=1.2V.
50
5
10
10
8.06%
PAE [%]
8
6
4
2
0
-2
-30
-25
-20
-15
-10
Psav [dBm]
-5
0
5
10
Figure 3.57: 2 stages PA PAE when VCC=1.2V.
In this section, two power amplifiers were simulated, one with 1 stage and other with 2 stages.
The first amplifier has small gain, so it was decided to do the second amplifier in order to have more
power gain. The 1 stage PA has more output power, but less power gain than the 2 stages PA. The
difference between power gains is larger than the difference between output powers, this results in a
higher efficiency to the 2 stages PA.
In order to fairly compare both amplifiers, the power amplifiers figure of merit through (1.1) was
calculated. In Table 3.7 are presented the main parameters of each PA and its FoM. Through Table 3.7
it is visible that the 2 stages power amplifier has a better FoM, so it can be considered the better between
the two.
Table 3.7: Power amplifier main parameters and FoM.
Topologia
P1dB [dBm]
GP [dB]
PAE [%]
FoM [dB]
Supply [V]
Com. Emitter 1-stg
7.67
1.98
6.92
18.1
1.2
Com. Emitter 2-stg
7.27
6.16
8.06
22.45
1.2
3.5. Summary
Firstly, in this chapter, it was done a brief presentation of a power amplifier and its classes with
particular focus in class-A, followed by the class-A definition, its characteristics and its working mode.
Secondly, it was studied the technology transistors in class-A operation mode. This study’s goal was to
obtain the load that maximizes the tradeoff between output power and efficiency, as well as the best
kind of transistors and the best set of them. Thirdly, it was compared the common-emitter and cascode
topology, having in mind the results of the previous study. Finally, the power amplifiers were designed,
initially with technology components and, then, with its electromagnetic results. Finally, both amplifiers
were compared through the figure of merit presented in section 1.3.3.
51
52
Power Amplifier with Power Combining
Power combiners (PCs) are widely used in RF and microwave applications. They enable the input
power to be combined within an environment where the characteristic impedance is maintained. In
theory, combiners don’t have losses if the input signals are with the proper phase. However, in reality
that is not the only reason, once the passive components’ losses, also, have to be accounted.
The power combiners are also designated as power splitters, because the same circuit can be
used to combine or split RF power. The only difference is the port where the RF power is applied and
this has to be done in opposite ports.
The in-phase power combiners and dividers are important components of the RF and microwave
transmitters when it is necessary to deliver a high output power level to an antenna. It is also required
to provide a high degree of isolation between output ports over some frequency range for required inphase signals with equal amplitudes [27].
The low breakdown voltage of Silicon based devices limits their peak output power [11].
Nevertheless, greater output power may be achieved using passive power combining if the insertion
loss of the combiner is lower than the power added by summing multiple PAs outputs [28]. On-chip
power combining becomes feasible in mm-wave power amplifiers because the chip area required for a
passive power combiner shrinks with decreasing wavelength [11]. A PC should also transform the offchip load, typically 50 Ω, to the optimum PA load impedance required for maximum output power [11].
Considering all things said before and the integration of the PC, the Wilkinson Power Combiner
was chosen, since it is made of passive elements. This chapter includes an introduction to the Wilkinson
Power Combiner, followed by its study, where it is simulated a Wilkinson with technology components
and it is presented a solution to increase the distance between the input ports. Then, two shapes of
power combiners will be studied and, according with the results, one shape will be chosen. At last, the
power amplifier with power combining will be studied in order to see if the output power is higher than
without power combining.
4.1. Wilkinson Power Combiner
The Wilkinson Power Combiner was introduced by Ernest J. Wilkinson in 1960 [29]. Its purpose
is to equally combine the power between its input ports at the output port, ideally without losses. Like
any other, this PC can be used in reverse direction – as a power divider. Other properties of this
combiner are that all ports are matched, the two input terminals are isolated from one another, and that
it is reciprocal. This means that the same value can be obtained either the signal is sent from one port
to another and vice-versa.
The Wilkinson PC is essentially a pair of 2:1 parallel impedance transformers which transform
each 50 Ω input up to 100 Ω, as illustrated in Figure 4.1. The role of the isolation resistor is to terminate
any odd-mode signals. This port isolation is widely regarded as an asset in RF and microwave power
combiner design, mainly through its ability to suppress odd mode instability between the combined
53
amplifiers [30].Depending on the bandwidth required, the Wilkinson combiner can have two or more
quarter wave matching sections [30], since it enables a bandwidth increase.
Z02
1
/4
R
3
/4
2
Z02
Figure 4.1: 2:1 Wilkinson Power Combiner.
The values within the two way Wilkinson combiner can be calculated through
R  2  Z0
(3.5),
where R is the value of the terminating resistor connected between the two ports and Z0 is the
characteristic impedance of the overall system.
The characteristic impedance of the quarter of wavelength transformers is given by
Z  Z0 2
(3.6).
So, for a system with a reference impedance of 50 Ω the resistor and the impedance of quarter wave
transformers is 100 Ω and approximately 70.7 Ω, respectively.
Ideally, the output signal in the Wilkinson PC has its power equal to the sum of the inputs power,
which means an increase of 3 dB, as it is shown in the S-parameter matrix
0 0 1
j 
S   0 0 1
2
 1 1 0
(3.7).
Through (3.7) it is possible to verify that ports are matched, since S 11, S22 and S33 equal zero. Ports 1
and 2 are isolated, once S12 and S21 equals zero, as well as the power presented at port 3 is equally
combined between ports 1 and 2. This means that S 13, S23, S31 and S32 equal -3 dB with a 90º phase
shift.
4.2. Simulation Results
After a brief introduction of the Wilkinson Power Combiner, a study will be performed, presenting
the simulations results, as well. At first, it was studied the 2:1 Wilkinson PC, as represented in Figure
4.1. It is composed of two transmission lines of a quarter of wavelength and with a characteristic
impedance of 502 Ω. A line with these characteristics was studied in Chapter 2 and through 2.3.3. it
is possible to see that it needs a 6 µm width and 654 µm length.
The Wilkinson PC was studied with Cadence software, through an S-Parameter simulation, and
using the technology components. The obtained results for the 2:1 combiner are shown in Figure 4.2,
where it is possible to see that port 1 and 3 are fully adapted. Therefore, port 2 is adapted too, once the
54
Wilkinson power combiner is symmetric. Port 1 is isolated from port 2 as it is shown in Figure 4.2 through
S21 parameter. Also, losses from inputs to the output are 0.33 dB.
S-Parameters [dB]
0
S11
S21
S31
S33
-39.07 dB
-34.91 dB
-3.33 dB
-32,79 dB
-10
-20
-30
-40
-50
50
55
60
Frequency [GHz]
65
70
Figure 4.2: Obtained S-Parameters for the 2:1 Wilkinson Power Combiner.
If the power combiner layout is equal to Figure 4.1, both entries would be very close since a 100 Ω
resistor has a very small size. This proximity would result in the amplifiers to be close, as well, causing
coupling between them In order to avoid this problem, line sections were placed between the resistor
and the entries, as shown in Figure 4.3.
From 2.3.3. it is known that a /4 line has a length of 654 µm, which corresponds to a 90 degrees
phase. Knowing this and placing a 5 degrees line, which corresponds to a 36 µm line, between the
resistor and each input port, it will be necessary to increase the transmission lines’ length by 5 degrees.
This is done so the signal components that pass from one port to another, are canceled by the
components that run the entire combiner. Therefore, the first ones have a 10 degrees’ phase while the
second ones are in anti-phase, i.e., a 190 degrees’ phase. The schematic of such combiner is shown in
Figure 4.3, where the lines’ dimensions are represented. The use of the 5 degrees lines leads, almost,
to any difference when comparing with the previous combiner, as it can be seen in Figure 4.4.
Figure 4.3: Power combiner with 5 degrees lines between the inputs and the resistor.
55
S-Parameters [dB]
0
S11
S21
S31
S33
-37.60 dB
-31.64 dB
-3.35 dB
-37.82 dB
-10
-20
-30
-40
-50
50
55
60
Frequency [GHz]
65
70
Figure 4.4: Obtained S-Parameters for the power combiner of Figure 4.3.
4.3. Power Combiner Layout
The power combiner layout must be studied so that the configuration that allows to obtain the
best results can be found. Therefore, two types of configuration were studied, one with a rectangular
shape, Figure 4.5, and another with a squared shape, Figure 4.6. In both configurations, the input and
output ports are 15 µm width in order to have the same width as 50 Ω lines, which will be connected to
them.
Figure 4.5: Rectangular power combiner layout.
Figure 4.6: Squared power combiner layout.
56
Although the bandwidth of interest is close to the 60 GHz band, both combiners were simulated
between 50 GHz and 70 GHz, so, it is possible to compare the obtained results between them and with
the electrical model results. The obtained results for the rectangular and squared combiners are
presented in Figure 4.7 and in Figure 4.8, respectively. When comparing both results, it is visible that
the rectangular combiner has slightly better results, since the input ports are more matched and they
are more isolated than the squared combiner. Both have, almost, the same losses, and the output port
is more adapted in the squared combiner than in the rectangular one. Comparing these results with the
electrical model, the major difference is at the input, probably due to the T discontinuity, since it is only
used in the layout. Since there isn’t, almost, any difference between the losses of these combiners, the
selection isn’t going to be made yet.
S-Parameters [dB]
0
S11
S21
S31
S33
-12.16 dB
-15.00 dB
-3.58 dB
-33.44 dB
-10
-20
-30
-40
50
55
60
Frequency [GHz]
65
70
Figure 4.7: Rectangular power combiner results.
S-Parameters [dB]
0
S11
S21
S31
S33
-10.51 dB
-13.85 dB
-3.59 dB
-37.81 dB
-10
-20
-30
-40
50
55
60
Frequency [GHz]
65
70
Figure 4.8: Squared power combiner results.
The power amplifier will be placed between a power divider and a power combiner, so the base
will be biased from the divider’s input, and the collector from the combiner’s output. This led to the study
of the power combiner with an output network, Figure 4.9, which is equal to the one used in the
amplifiers. Both power combiners were simulated with this network at the output, and they were EM
simulated between 57 GHz and 66 GHz. The obtained results for the rectangular shape are shown in
Figure 4.10, and for the squared one in Figure 4.11. Through these results it can be seen that the
rectangular combiner has a better input matching and input ports isolation. However, the squared
combiner has less losses, so, it will be chosen, in order to obtain the maximum output power.
57
Figure 4.9: Power combiner’s output bias network.
S-Parameters [dB]
0
-5
S11
S21
S31
S33
-13.05 dB
-15.93 dB
-4.82 dB
-23.51 dB
-10
-15
-20
-25
-30
57
58
59
60
61
62
Frequency [GHz]
63
64
65
66
Figure 4.10: Rectangular combiner’s results.
S-Parameters [dB]
0
-5
S11
S21
S31
S33
-10.50 dB
-14.88 dB
-4.49 dB
-23.26 dB
-10
-15
-20
-25
-30
57
58
59
60
61
62
Frequency [GHz]
63
64
65
66
Figure 4.11: Squared combiner’s results.
4.4. Power Amplifier and Power Combiner
Now that the power amplifier as well as the power combiner/divider were studied individually, it is
possible to join the three. Therefore, the power amplifier will have a power divider at its input and a
58
power combiner at its output, Figure 4.12, and both were separately simulated. The input matching
network had to be adjusted, and the transistors input impedance, that was considered, is 9.83-j3.31 Ω,
Table 4.1, once the base biasing will be done through the divider’s input. The power divider structure,
that was electromagnetically simulated, is in Figure 4.12. The EM results showed a divider outputs
impedances of 9.2+j3.01 Ω, which means that the transistors are matched. However, the divider
presented high insertion losses, approximately 4.5 dB.
The goal, here, was at the output to achieve, ideally, twice the output power of the amplifier.
However, this is not possible, due to the passive components’ losses. Instead, a bigger value was
achieved, 8.58 dBm, as can be seen in Figure 4.13. It was obtained, almost, more 1 dBm when
comparing it with Figure 3.34, because once again the transistors electrical model without extracted
parasitics were used. On the other hand, a small power gain was obtained, less than 2 dB, comparing
with Figure 3.34, which, seriously, affects the power added efficiency, as shown in Figure 4.14.
Figure 4.12: Power amplifier with power divider and combiner layout.
Table 4.1: Transistors input matching network.
Stub
Line
Width [um]
15
15
Length [um]
441
172
59
20
10
0
Output Power [dBm]
Input Power [dBm]
Power Gain [dB]
8.58 dBm
7.95 dBm
0.62 dB
-10
-20
-30
-40
-30
-25
-20
-15
-10
-5
Psav [dBm]
0
5
10
15
Figure 4.13: Power results of the PA with a power divider and power combiner.
10
2.07%
PAE [%]
0
-10
-20
-30
-30
-25
-20
-15
-10
-5
Psav [dBm]
0
5
10
15
Figure 4.14: PAE of the PA with a power divider and power combiner.
The previous amplifier presents very small power gain even without the transistors’ parasitic
capacitances.
Next a two stages power amplifier with divider and combiner was designed, since it has more
power gain, and allows to compare with the 2 stages power amplifier. The amplifier was placed between
the power divider and the power combiner of Figure 4.12, like it can be seen in Figure 4.15. Here, it was
used the transistors extraction to fairly compare this results with the amplifier of Figure 3.51. The VCC
was set to 1.2 V and the VBB1 and VBB2 were set in order the transistors collector current to be 14.4 mA.
Thus, it was obtained a slightly higher output power, 0.25 dBm, than in Figure 3.56, as can be seen in
Figure 4.16. As the previous amplifier with power combining, the power gain decreased, which led to an
efficiency decrease, Figure 4.17.
60
Figure 4.15: 2 stages power combiner with power divider and power combiner.
20
10
0
-10
Output Power [dBm]
Input Power [dBm]
Power Gain [dB]
7.52 dBm
3.82 dBm
3.69 dB
-20
-30
-40
-30
-25
-20
-15
-10
-5
Psav [dBm]
0
5
10
15
Figure 4.16: Power results of the 2 stages PA with power combining.
5
3.69%
PAE [%]
0
-5
-10
-15
-30
-25
-20
-15
-10
-5
Psav [dBm]
0
5
10
15
Figure 4.17: PAE of the 2 stages PA with power combining.
When comparing both amplifiers with power combining, it can be concluded that the first one has
more output power, more than 1 dBm, but it has less 3 dB in power gain and 1.6% in efficiency. Both
61
amplifiers could have better results, but to do that, several EM simulations have to be performed in order
to adjust the combiner/divider and the impedance matching networks that were used. These EM
simulations are extensive and take a lot of time, affecting the amount of results that can be obtained in
a short period of time.
4.5. Summary
In this Chapter, it is presented a brief introduction of the power combiner, its function, some of its
properties and a reason to be used in microwave applications. Firstly, it was presented the Wilkinson
power combiner with particular focus on its characteristics. This was followed by simulations of Wilkinson
power combiner with technology components, where it was studied the possibility of increasing the
distance of the input ports. Secondly, two combiners with different shapes were used in order to see
which shape allows to have less losses. Then, the same was done with a bias network at the output.
Finally, the power amplifier was placed together with a power divider at its input and, a power combiner
at its output. This was done for both amplifiers that were simulated in 3.4.
62
Conclusions and Future Work
5.1. Conclusions
This master dissertation’s main goal was to design a power amplifier with SiGe BiCMOS 0.25 µm
technology for 60 GHz applications and, also, to evaluate the possibility of implementing a power
combiner in this technology.
To achieve these goals, a technology study was performed. Firstly, the transistors were studied,
and their DC characteristics were observed. From this study it can be seen that transistors need a baseemitter voltage higher than 0.8 V to start conducting. Furthermore, it was verified that transistors are not
unconditionally stable in wideband. Secondly, the passive components were studied through their
electrical model, enabling two important outcomes. The first is that capacitors are, almost, ideal and, the
second is that inductors cannot be used, since they have a resonant frequency lower than 60 GHz.
Simultaneously, transmission lines were, also, studied, concluding that they resemble the microstrip
ones. At last, the passive components were studied through electromagnetic simulations, once it
enabled the electric models accuracy and identified parasitic coupling between components. This study
showed that the capacitors are not ideal, as shown by the electrical model. The inductors EM results
are not too different from the electrical model ones and they showed that the smallest inductor should
be used up to 15 GHz. The transmission lines EM results weren’t significantly different from their
electrical model. Concluding this part of the study, the electromagnetic simulations results were used
instead the electrical models, since the design kit hasn’t the discontinuities’ electrical model.
Throughout the passive components’ study, two power amplifiers were designed, both in
common-emitter mode, one with one stage and, the other with two stages. In Table 5.1, it can be seen
that they don’t fulfill the specifications, although those values were chosen based on the state of the art
results for power amplifiers that use equivalent 0.25 µm technology. Moreover, the obtained values are
too small, when compared to the specifications. This difference means that better values could be
obtained if, instead of using the components’ electrical model, the electromagnetic simulations and
transistors extraction results were used from the beginning. Another possible reason is that the
technology limits weren’t always respected by the state of the art amplifiers. This was observed in terms
of breakdown voltage limit.
Table 5.1: Specifications and obtained results.
P-1dB [dBm]
PAE [%]
≥ 14.5
≥ 20
Com.-emit. 1-stg
7.67
6.92
Com.-emit. 2-stg
7.27
8.06
Specifications
The designed amplifiers were compared through a figure of merit, (1.1), and the amplifier with
best FoM is the one with two stages. Comparing the obtained amplifiers FoM with the state of art, it can
be seen that all have higher values. This comparison may be considered unfair, because there are
different technologies, like, for example 0.13 µm.
63
The Wilkinson power combiner can be designed in this technology since it shows insertion losses
of 0.6 dB, causing, approximately, more than 2.4 dB in the output than in each the input. However, the
obtained results of the power amplifiers with a power divider and combiner show different values. This
difference is caused by the bias networks and the input matching networks, which are, probably, not
presenting the right impedance to the power combiner input and output, causing more losses. To prevent
this, it will be necessary to readjust these networks, which has to be done through EM simulations.
These EM simulations take a lot of time, affecting the amount of results that can be obtained in a short
period of time.
5.2. Future Work
As future work, there are two things that can be, immediately, pointed out. The first one is EM
simulating the amplifier’s components from the beginning of the project, especially the T discontinuity,
instead of doing it with their electrical model. The second one is taking the transistor’s extraction at the
beginning of the project so it can be considered in the amplifiers design.
The use of a 0.13 µm technology would be important, since it is more suitable to high frequencies,
as 60 GHz.
64
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