Download A novel optimization design for 3.3 kV injection

Vol. 35, No. 1
Journal of Semiconductors
January 2014
A novel optimization design for 3.3 kV injection-enhanced gate transistor
Tian Xiaoli(田晓丽)1 , Chu Weili(褚为利)1 , Lu Jiang(陆江)1 , Lu Shuojin(卢烁今)1; 2 ,
Yu Qiaoqun(喻巧群)1 , and Zhu Yangjun(朱阳军)1; 2; Ž
1 Institute
2 Jiangsu
of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
R&D Center for Internet of Things, Wuxi 214135, China
Abstract: This paper introduces a homemade injection-enhanced gate transistor (IEGT) with blocking voltage up
to 3.7 kV. An advanced cell structure with dummy trench and a large cell pitch is adopted in the IEGT. The carrier
concentration at the N-emitter side is increased by the larger cell pitch of the IEGT and it enhances the P–i–N effect
within the device. The result shows that the IEGT has a remarkablely low on-state forward voltage drop (VCE.sat/ /
compared to traditional trench IGBT structures. However, too large cell pitch decreases the channel density of the
trench IEGT and increases the voltage drop across the channel, finally it will increase the VCE.sat/ of the IEGT.
Therefore, the cell pitch selection is the key parameter consideration in the design of the IEGT. In this paper, a
cell pitch selection method and the optimal value of 3.3 kV IEGT are presented by simulations and experimental
results.
Key words: IEGT; dummy cell; 3.3kV; cell pitch
DOI: 10.1088/1674-4926/35/1/014005
EEACC: 2560
1. Introduction
It is well known that the IGBT has become the most popular power device in power application areas due to its advantage in integrating the characteristics of bipolar transistors and
power MOSFETs simultaneouslyŒ1; 2 . Until recently, the concept of the trench structure has been considered to be an effective method to obtain a significant performance improvement
in both on-state forward voltage drop (VCE.sat/ / and turn-off
time (Tf /. However, there is a poor short-circuit safe operation
area (SCSOA) for the trench IGBT compared with the planar
IGBTŒ3 . The main reason is the high saturation current density
of the trench IGBT due to its high cell density. Although the
cell density can be reduced by increasing the distance between
different trenches, it leads to a drop of blocking voltage. In order to overcome this trench IGBT defect and further reduce the
VCE.sat/ of the device, the concept of an IEGT is proposedŒ4 .
In the structure of IEGTŒ5 , a series of inactive cells (called
a dummy cell) which are not contacted to the emitter is adopted.
The carrier concentration at the N-emitter side of the N-base is
increased by the addition of the dummy cell and the P–i–N effect is further enhanced. Therefore a lower VCE.sat/ is obtained
with a carrier profile similar to a thyristorŒ6 (P–i–N diode).
However, the channel density is decreased by the dummy cell
and the voltage drop across the channel is increased, and it
leads to a higher VCE.sat/ of the IEGT. For the IEGT, the adjustment of the cell pitch is the key design process to optimize
the lowest VCE.sat/ , while reducing short-circuit current density
without blocking voltage drop.
2. Theoretical analysis
In order to analyze the internal physics behavior of the
IGBT, two main models are used in the analysis of the for-
ward conduction characteristicsŒ7 . The models are the P–i–N
rectifier/MOSFET model and the P–N–P transistor/MOSFET
model. Figures 1(a) and 1(b) are the equivalent circuits of
the two models. The P–i–N rectifier/MOSFET model can be
used to understand the device behavior in forward condition. And the P–N–P transistor/MOSFET model offers a much
more complete description of the IGBT. In the P–i–N rectifier/MOSFET model, the IGBT is considered as a P–i–N rectifier in series with an MOSFETŒ4 .
When a large positive gate bias is applied, the IGBT structure operates in the on-state, which leads to the formation of an
accumulation layer under the gate electrode where it overlaps
the N-drift region. Electrons arriving in the accumulation layer
Fig. 1. Models used to analyze forward conduction characteristics.
(a) P–i–N rectifier/MOSFET model. (b) P–N–P transistor/MOSFET
model.
* Project supported by the National Major Science and Technology Special Project of China (Nos. 2011ZX02504-002, 2011ZX02603-002).
† Corresponding author. Email: [email protected]
Received 15 May 2013, revised manuscript received 26 July 2013
© 2014 Chinese Institute of Electronics
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via the MOSFET channel can be viewed as being injected into
N-drift region, and they promote the injection of holes from the
PC collector. The P–i–N structure is constructed by the accumulation layer, N-drift region and PC collector.
The P–i–N rectifier and MOSFET are shown by the dashed
line in Fig. 2 (the cross section of the IGBT).
Figure 2 is the cross section of the IGBT. WR is the width
of the poly gate and WP is that of the rest cell. Sum of WR and
WP makes cell pitch P . To simplify the calculation of forward
voltage drop of the IGBT, the chip area is supposed to be unity.
The forward conduction current density JF;P i N in the P–i–N
rectifier is referred to as:
JF; P
i N
D
IC
;
WR Z
(1)
where Z is the length perpendicular to the cross section of the
linear diagram in Fig. 2, and IC is the current flows through
IGBT. The voltage drop of the P–i–N rectifier VF; P i N is related to the current density, and can be expressed as:
VF; P
i N
D
Fig. 2. Cross section of the IGBT.
kT
IC
ln
;
q
2qWR ZDa ni F .d=La /
(2)
where Da is the ambipolar diffusion coefficient. La is the ambipolar diffusion length and the distance d is half the width of
the N-drift region as indicated in Fig. 2.
The voltage drop of the MOS VF; MOS is the product of current IC and total channel resistance Rch . The channel resistance
rch of every cell stays the same if the gate and emitter structures
stay the same. IGBT cells are in parallel connection. Therefore
the total channel resistance can be expressed as:
Rch D .WP C WR / rch :
(3)
While the voltage drop of the MOS is referred to as:
VF; MOS D IC .WP C WR /rch :
The forward drop across the IGBT is simply the sum of
voltage drop across the MOSFET and the P–i–N rectifierŒ8 :
VF D
kT
IC
ln
C IC .WP C WR /rch ; (4)
q
2qWR ZDa ni F .d=La /
where
.d=La / tanh.d=La /
e
F .d=La / D q
1 0:25 tanh4 .d=La /
qVM =2K T
:
(5)
It is estimated from Eq. (4) that VF reduces initially then
increases with the increase of cell pitch due to the increasing
WR . In the beginning, the P–i–N effect is enhanced by increasing WR and causes the reduction of the forward voltage drop
across the IGBT. However, with the increase of WR the reduced
channel density is dominant, which makes the forward voltage
drop across the IGBT increase. The forward drop of the IGBT
VF is called collector–emitter saturation voltage (VCE.sat/ / when
rated current flows through the IGBT. The aim of this paper is
to find the optimal cell pitch P which makes VCE.sat/ of the
IGBT the smallest, with a good trade off with the other parameters, such as forward blocking voltage (BV) and the fall time
(tf /.
3. Simulation and experiment setup
In this study, the 3.3 kV IEGT devices are simulated by using Sentaurus software, which is an advanced simulator to investigate the structure and inner physics behavior of the device.
The Sentaurus process is used to generate the device structure
of the IEGT, and the Sentaurus device is used to simulate its
characteristics. In order to evaluate device behavior accurately,
the basic semiconductor equations (Poisson and current continuity equations) and the avalanche breakdown model with an
adjustment parameter are used to simulate the physics characteristics of the device. The 3.3 kV IEGT is designed using the
simulation results and fabricated on a domestic process platform. Figure 3 shows the simulation results of a 3.3 kV IEGT
with different cell pitch of 27 m and 41 m, respectively. The
substrate is selected as N-type FZ silicon with suitable resistivity and thickness to fulfill the parameter requirement of the
device. A field stop layer is at the bottom of chipŒ9 to improve
the blocking voltage performance of the IEGT. The width and
depth of trench are the same in the two structures.
To evaluate the performance of the optimum device, high
voltage testing equipment is used to compare the static and dynamic characteristics of the fabricated devices. The QT2 transistor curve tracer is used to find the blocking voltage waveform of the device. The Tesec 3620TT is used to test the forward conducting voltage of the device. The Tesec 3430 dynamic tester is used to measure the switching time of the device.
4. Results and discussion
The 3.3 kV IEGTs are designed and fabricated on a domestic process platform. Figure 4 shows the SEM images of IEGTs
with different cell pitch of 27 m and 41 m.
Figure 5 shows the simulation results of the forward blocking state of the two different 3.3 kV IEGTs described above
and a traditional trench IGBT. The cell pitch of the traditional
trench IGBT is the same as one of the IEGTs: 27 m. The
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Fig. 3. Simulation results of the IEGT with different cell pitch. (a) Cell pitch D 27 m. (b) Cell pitch D 41 m.
Fig. 4. SEM images of the fabricated IEGT with different cell pitch. (a) Cell pitch D 27 m. (b) Cell pitch D 41 m.
Fig. 5. Simulation results of the forward blocking state of the traditional trench IGBT and IEGTs.
blocking voltages of these three structures (traditional trench
IGBT, IEGT with cell pitch 41 m and IEGT with cell pitch
27 m) are 3 kV, 4.3 kV and 4.6 kV, respectively. According
to the simulation results, the blocking voltage of the traditional
trench IGBT is much smaller than that of an IEGT with dummy
cell in the same cell pitch width. What is more, the blocking
voltage of the IEGT with a larger cell pitch is slightly smaller
than that of the IEGT with a smaller cell pitch.
Figure 6 shows an experimental result of the forward
blocking stateŒ10 of IEGTs with cell pitch D 27 m and 41 m.
VCE is plotted on the horizontal axis and ICE on the vertical.
Each grid square in horizontal direction indicates 500 V. The
actual blocking voltages of IEGTs with cell pitch D 27 m and
41 m are about 3.7 kV and 3.5 kV, respectively. The testing
result shows that the blocking voltage realized design objective
and the trend influenced by cell pitch agrees with simulation
results.
The isopotential curve is bent more seriously in the traditional trench IGBT than that in IEGT with the same cell pitch.
Therefore the electric field at the trench corner is larger in a
traditional trench IGBT, which leads to a lower blocking voltage. Similarly a larger cell pitch results in a large electric field
at the trench corner and leads to a low blocking voltage.
Figure 7 shows the simulation result of the collector–
emitter voltage of IEGTs with different cell pitch. It is observed
that VCE at the rated current of 25 A reduces initially, and then
increases with the increase of cell pitch. In the beginning, the
P–i–N effect is enhanced by increasing cell pitch and causes the
reduction of the forward voltage drop across the IGBT. However, with the increase of cell pitch, the reduced channel density
is dominant, which makes the forward voltage drop across the
IGBT increase. Comparison of VCE at the rated current of 25 A
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Fig. 6. Experimental result of the forward blocking state of IEGTs with different cell pitch. (a) Cell pitch D 27 m. (b) Cell pitch D 41 m.
Fig. 7. Simulated result of VCE.sat/ of 3.3 kV IEGTs with different cell
pitch.
results in 3.4 V in cell pitch D 13.5 m, 2.7 V in cell pitch D
27 m, 2.85 V in cell pitch D 41 m, 2.93 V in cell pitch D 60
m. The simulation result indicates that 27 m is the optimal
cell pitch.
Figure 8 shows the experimental result of the I –V curves
of IEGTs with cell pitch of 27 m and 41 m. A comparison
of VCE at the rated current of 25 A results in 2.25 V in cell pitch
D 27 m, 3.0 V in cell pitch D 41 m. Obviously, 27 m is
just or near the optimal cell pitch which is in good agreement
with the simulation result.
The experimental switching characteristics of the fabricated IEGTs with different cell pitches of 27 m and 41 m are
illustrated in Figs. 9 and 10, respectively. The curve b indicates
the gate voltage (VG /, the curve a is the collector current (IC /,
and the curve c is the collector voltage (VC /. The IEGT device
is tested with an inductive load, and the rated current is 25 A
(IC D 25 A). The fall time (tf / is defined as the time it takes for
the collector current to decrease from 90% of its steady state
value to 10%. The fall time of the IEGT with cell pitch 27 m
is about 41 ns, and it is 86 ns for the IEGT with cell pitch of
Fig. 8. Experimental IC –VC characteristics of 3.3 kV IEGTs with different cell pitch.
Fig. 9. (color online) Experimental switching waveform of the IEGT
with a cell pitch of 27 m.
41 m. The testing results show that an IEGT with a cell pitch
of 27 m is better than an IEGT with a cell pitch of 41 m.
There is an optimal cell pitch for an IEGT according to
the theoretical analysis of P–i–N rectifier/MOSFET model of
IGBT. A 3.3 kV IEGT with the smallest VCE.sat/ and suitable
switching characteristics is fabricated, based on the simulation
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References
Fig. 10. (color online) Experimental switching waveform of the IEGT
with a cell pitch of 41 m.
result and experiment test of the IEGT.
5. Conclusion
In this paper a homemade trench FS IEGT with blocking
voltage of 3.3 kV is proposed. The dummy cell is adopted in the
IEGT to reduce VCE.sat/ by enhancing the P–i–N effect. However, VCE.sat/ increases if the cell pitch is too large due to the
decrease of the channel density. An optimal cell pitch is selected by simulation and experimental test. The optimal cell
pitch is 27 m in this device and the actual blocking voltage
reaches 3.7 kV.
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