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THS4521, THS4522, THS4524
SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
THS452x Very Low Power, Negative Rail Input, Rail-To-Rail Output, Fully Differential
Amplifier
1 Features
3 Description
•
•
•
•
•
•
•
The THS4521, THS4522, and THS4524 family of
devices are very low-power, fully differential
amplifiers with rail-to-rail output and an input
common-mode range that includes the negative rail.
These amplifiers are designed for low-power data
acquisition systems and high-density applications
where power dissipation is a critical parameter, and
provide
exceptional
performance
in
audio
applications.
1
•
•
•
•
•
•
Fully Differential Architecture
Bandwidth: 145 MHz (AV = 1 V/V)
Slew Rate: 490 V/μs
HD2: –133 dBc at 10 kHz (1 VRMS, RL = 1 kΩ)
HD3: –141 dBc at 10 kHz (1 VRMS, RL = 1 kΩ)
Input Voltage Noise: 4.6 nV/√Hz (f = 100 kHz)
THD+N: –112dBc (0.00025%) at 1 kHz (22-kHz
BW, G = 1, 5 VPP)
Open-Loop Gain: 119 dB (DC)
NRI—Negative Rail Input
RRO—Rail-to-Rail Output
Output Common-Mode Control (with Low Offset)
Power Supply:
– Voltage: +2.5 V (±1.25 V) to +5.5 V (±2.75 V)
– Current: 1.14 mA/ch
Power-Down Capability: 20 μA (typical)
The family includes single FDA (THS4521), dual FDA
(THS4522), and quad FDA (THS4524) versions.
Device Information(1)
PART NUMBER
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
THS4522
TSSOP (16)
5.00 mm × 4.40 mm
THS4524
TSSOP (38)
9.70 mm × 4.40 mm
THS4521
(1) For all available packages, see the package option addendum
at the end of the datasheet.
2 Applications
•
•
•
•
PACKAGE
Low-Power SAR and ΔΣ ADC Drivers
Low-Power Differential Drivers
Low-Power Differential Signal Conditioning
Low-Power, High-Performance Differential Audio
Amplifiers
THS4521 and ADS1278 Combined Performance
1-kHz FFT
1 kΩ
0
1.5 nF
AINN1
THS4521
VIN-
49.9 Ω
2.2 nF
ADS1278 (CH 1)
AINP1
VOCM
VCOM
1/2
OPA2350
1.5 nF
-40
-60
-80
-100
-120
x1
0.1 μF
Magnitude (dBFS)
49.9 Ω
1 kΩ
VIN+
1 kΩ
G=1
RF = RG = 1 kΩ
CF = 1.5 nF
VS = 5 V
Load = 2.2 nF
-20
5V
0.1 μF
-140
-160
0
4
8
12
16
20
24 26
Frequency (kHz)
1 kΩ
Tone
(Hz)
1k
Signal
(dBFS)
-0.50
SNR (dBc)
THD (dBc)
109.1
-107.9
SINAD
(dBc)
105.5
SFDR
(dBc)
113.7
For more information on this circuit, view SBAU197.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THS4521, THS4522, THS4524
SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
1
1
1
2
3
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings ............................................................ 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics: VS+ – VS– = 3.3 V ............ 8
Electrical Characteristics: VS+ – VS– = 5 V ............. 10
Typical Characteristics ............................................ 12
Typical Characteristics: VS+ – VS– = 3.3 V.............. 14
Typical Characteristics: 5 V .................................... 19
Detailed Description ............................................ 24
8.1 Overview ................................................................. 24
8.2 Functional Block Diagram ....................................... 25
8.3 Feature Description................................................. 25
8.4 Device Functional Modes........................................ 34
8.5 Programming........................................................... 40
9
Application and Implementation ........................ 41
9.1 Application Information............................................ 41
9.2 Typical Applications ............................................... 41
10 Power Supply Recommendations ..................... 51
11 Layout................................................................... 51
11.1 Layout Guidelines ................................................. 51
11.2 Layout Example .................................................... 52
12 Device and Documentation Support ................. 53
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
53
53
53
53
53
53
13 Mechanical, Packaging, and Orderable
Information ........................................................... 53
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (December 2014) to Revision H
Page
•
Changed capacitor units in front page diagram from mF to µF (typo) ................................................................................... 1
•
Changed RF and RG unit in front page FFT plot from kW to kΩ (typo)................................................................................. 1
•
Changed Absolute Maximum Ratings minimum storage temperature value from 65 to –65 (typo) ..................................... 7
•
Added Community Resources section ................................................................................................................................. 53
Changes from Revision F (September 2011) to Revision G
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision E (December 2010) to Revision F
Page
•
Changed Input Offset Current values in 3.3 V Electrical Characteristics ............................................................................... 8
•
Changed Input Offset Current Drift values in 3.3 V Electrical Characteristics ....................................................................... 8
•
Changed Input Offset Current values in 5 V Electrical Characteristics ................................................................................ 11
•
Changed Input Offset Current Drift values in 5 V Electrical Characteristics ........................................................................ 11
•
Changed R41 and R42 in Figure 79..................................................................................................................................... 42
Changes from Revision D (August 2010) to Revision E
•
2
Page
Changed test level indication for 5-V input offset voltage drift from B to C.......................................................................... 10
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Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: THS4521 THS4522 THS4524
THS4521, THS4522, THS4524
www.ti.com
SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
5 Device Comparison Table
These fully differential amplifiers feature accurate output common-mode control that allows for dc-coupling when
driving analog-to-digital converters (ADCs). This control, coupled with an input common-mode range below the
negative rail as well as rail-to-rail output, allows for easy interfacing between single-ended, ground-referenced
signal sources. Additionally, these devices are ideally suited for driving both successive-approximation register
(SAR) and delta-sigma (ΔΣ) ADCs using only a single +2.5V to +5V and ground power supply.
The THS4521, THS4522, and THS4524 family of fully differential amplifiers is characterized for operation over
the full industrial temperature range from –40°C to +85°C. Table 1 shows a comparison of the THS4521 device
to similar TI devices.
Table 1. THS4521 Device Comparison
DEVICE
BW
(MHz)
IQ
(mA)
THD (dBc)
AT 100 kHz
VN
(nV/√Hz)
RAIL-TO-RAIL
DUAL PART
NUMBERS
THS4531
36
0.25
–104
10.0
Neg In, Out
—
THS4521
145
0.95
–102
4.6
Neg In, Out
THS4522
THS4520
620
14.2
–107
2.0
Out
—
THS4541
850
10.1
–137
2.2
Neg In, Out
—
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: THS4521 THS4522 THS4524
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THS4521, THS4522, THS4524
SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
www.ti.com
6 Pin Configuration and Functions
THS4521 D and DGK Package
8-Pin SOIC and VSSOP
Top View
VIN- 1
8
VIN+
VOCM 2
7
PD
VS+ 3
6
VS-
VOUT+ 4
5
VOUT-
THS4524 DBT Package
38-Pin TSSOP
Top View
THS4522 PW Package
16-Pin TSSOP
Top View
PD1
1
38
VS-
VIN1+
2
37
VOUT1-
VIN1-
3
36
VOUT1+
VOCM1
4
35
VS1+
VS-
5
34
VS-
PD2
6
33
VS-
VIN2+
7
32
VOUT2-
VIN2-
8
31
VOUT2+
PD1
1
16
VS-
VOCM2
9
30
VS2+
VIN1+
2
15
VOUT1-
VS-
10
29
VS-
VIN1-
3
14
VOUT1+
PD3
11
28
VS-
VOCM1
4
13
VS1+
VIN3+
12
27
VOUT3-
PD2
5
12
VS-
VIN3-
13
26
VOUT3+
VIN2+
6
11
VOUT2-
VOCM3
14
25
VS3+
VIN2-
7
10
VOUT2+
VS-
15
24
VS-
VOCM2
8
9
VS2+
PD4
16
23
VS-
VIN4+
17
22
VOUT4-
VIN4-
18
21
VOUT4+
VOCM4
19
20
VS4+
Pin Functions: THS4521
PIN
NAME
DESCRIPTION
NO.
VIN–
1
Inverting amplifier input
VOCM
2
Common-mode voltage input
VS+
3
Amplifier positive power-supply input
VOUT+
4
Noninverting amplifier output
VOUT–
5
Inverting amplifier output
VS–
6
Amplifier negative power-supply input. Note that VS– is tied together on multi-channel devices.
PD
7
Power down. PD = logic low puts device into low-power mode. PD = logic high or open for normal operation.
VIN+
8
Noninverting amplifier input
4
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SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
Pin Functions: THS4522
PIN
NAME
DESCRIPTION
NO.
PD 1
1
Power down 1. PD = logic low puts device into low-power mode. PD = logic high or open for normal operation.
VIN1+
2
Noninverting amplifier 1 input
VIN1–
3
Inverting amplifier 1 input
VOCM1
4
Common-mode voltage input 1
PD 2
5
Power down 2. PD = logic low puts device into low-power mode. PD = logic high or open for normal operation.
VIN2+
6
Noninverting amplifier 2 input
VIN2–
7
Inverting amplifier 2 input
VOCM2
8
Common-mode voltage input 2
VS+2
9
Amplifier 2 positive power-supply input
VOUT2+
10
Noninverting amplifier 2 output
VOUT2–
11
Inverting amplifier 2 output
VS–
12
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
VS+1
13
Amplifier 1 positive power-supply input
VOUT1+
14
Noninverting amplifier 1 output
VOUT1–
15
Inverting amplifier 1 output
VS–
16
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: THS4521 THS4522 THS4524
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THS4521, THS4522, THS4524
SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
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Pin Functions: THS4524
PIN
NAME
DESCRIPTION
NO.
PD 1
1
Power down 1. PD = logic low puts channel into low-power mode. PD = logic high or open for normal operation.
VIN1+
2
Noninverting amplifier 1 input
VIN1–
3
Inverting amplifier 1 input
VOCM1
4
Common-mode voltage input 1
VS–
5
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
PD 2
6
Power down 2. PD = logic low puts channel into low-power mode. PD = logic high or open for normal operation.
VIN2+
7
Noninverting amplifier 2 input
VIN2–
8
Inverting amplifier 2 input
VOCM2
9
Common-mode voltage input 2
VS–
10
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
PD 3
11
Power down 3. PD = logic low puts channel into low-power mode. PD = logic high or open for normal operation.
VIN3+
12
Noninverting amplifier 3 input
VIN3–
13
Inverting amplifier 3 input
VOCM3
14
Common-mode voltage input 3
VS–
15
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
PD 4
16
Power down 4. PD = logic low puts channel into low-power mode. PD = logic high or open for normal operation.
VIN4+
17
Noninverting amplifier 4 input
VIN4–
18
Inverting amplifier 4 input
VOCM4
19
Common-mode voltage input 4
VS4+
20
Amplifier 4 positive power-supply input
VOUT4+
21
Noninverting amplifier 4 output
VOUT4–
22
Inverting amplifier 4 output
VS–
23
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
VS–
24
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
VS3+
25
Amplifier 3 positive power-supply input
VOUT3+
26
Noninverting amplifier3 output
VOUT3–
27
Inverting amplifier3 output
VS–
28
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
VS–
29
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
VS2+
30
Amplifier 2 positive power-supply input
VOUT2+
31
Noninverting amplifier 2 output
VOUT2–
32
Inverting amplifier 2 output
VS–
33
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
VS–
34
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
VS1+
35
Amplifier 1 positive power-supply input
VOUT1+
36
Noninverting amplifier 1 output
VOUT1–
37
Inverting amplifier 1 output
VS–
38
Negative power-supply input. Note that VS– is tied together on multi-channel devices.
6
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SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). (1)
MIN
MAX
UNIT
5.5
V
(VS+) + 0.7
V
Supply voltage, VS– to VS+
Input/output voltage, VI (VIN±, VOUT±, VOCM pins)
(VS–) – 0.7
Differential input voltage, VID
Output current, IO
1
V
100
mA
10
mA
Input current, II (VIN±, VOCM pins)
Continuous power dissipation
See Thermal Information table
Maximum junction temperature, TJ
150
°C
Maximum junction temperature, TJ (continuous operation, long-term reliability)
125
°C
Operating free-air temperature, TA
–40
85
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±1300
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
±1000
Machine model (MM)
(1)
(2)
UNIT
V
±50
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VS+ single-supply voltage
2.7
5.0
5.4
UNIT
V
TA Ambient temperature
–40
25
85
°C
THS4522
THS4524
7.4 Thermal Information
THS4521
THERMAL METRIC (1)
RθJA
DGK
PW
DBT
8 PINS
8 PINS
16 PINS
38 PINS
127.8
193.8
124.2
106.2
RθJC(top) Junction-to-case (top) thermal resistance
81.8
84.1
62.8
60.9
RθJB
Junction-to-board thermal resistance
68.3
115.3
68.5
65.5
ψJT
Junction-to-top characterization parameter
32.2
17.9
15.8
18.5
ψJB
Junction-to-board characterization parameter
67.8
113.6
68
65.1
RθJC(bot) Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
N/A
(1)
Junction-to-ambient thermal resistance
D
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: THS4521 THS4522 THS4524
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THS4521, THS4522, THS4524
SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
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7.5 Electrical Characteristics: VS+ – VS– = 3.3 V
At VS+ = 3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RL = 1 kΩ differential, G = 1 V/V, single-ended input,
differential output, and input and output referenced to midsupply, unless otherwise noted.
PARAMETER
TEST CONDITIONS
TEST
LEVEL (1)
MIN
TYP
MAX
UNIT
AC PERFORMANCE
VOUT = 100 mVPP, G = 1
C
135
MHz
VOUT = 100 mVPP, G = 2
C
49
MHz
VOUT = 100 mVPP, G = 5
C
18.6
MHz
VOUT = 100 mVPP, G = 10
C
9.3
MHz
Gain bandwidth product
VOUT = 100 mVPP, G = 10
C
93
MHz
Large-signal bandwidth
VOUT = 2 VPP, G = 1
C
95
MHz
Bandwidth for 0.1-dB flatness
VOUT = 2 VPP, G = 1
C
20
MHz
Rising slew rate (differential)
VOUT = 2-V Step, G = 1, RL = 200 Ω
C
420
V/μs
Falling slew rate (differential)
VOUT = 2-V Step, G = 1, RL = 200 Ω
C
460
V/μs
Overshoot
VOUT = 2-V Step, G = 1, RL = 200 Ω
C
1.2%
Undershoot
VOUT = 2-V Step, G = 1, RL = 200 Ω
C
2.1%
Rise time
VOUT = 2-V Step, G = 1, RL = 200 Ω
C
4
ns
Fall time
VOUT = 2-V Step, G = 1, RL = 200 Ω
C
3.5
ns
Settling time to 1%
VOUT = 2-V Step, G = 1, RL = 200 Ω
C
13
ns
f = 1 MHz, VOUT = 2 VPP, G = 1
C
–85
dBc
f = 1 kHz, VOUT = 1 VRMS, G = 1 (2),
differential input
C
–133
dBc
f = 1 MHz, VOUT = 2 VPP, G = 1
C
–90
dBc
f = 1 kHz, VOUT = 1 VRMS, G = 1 (2),
differential input
C
–141
dBc
Second-order intermodulation distortion
Two-tone, f1 = 2 MHz, f2 = 2.2 MHz,
VOUT = 2-VPP envelope
C
–83
dBc
Third-order intermodulation distortion
Two-tone, f1 = 2 MHz, f2 = 2.2 MHz,
VOUT = 2-VPP envelope
C
–90
dBc
Input voltage noise
f > 10 kHz
C
4.6
nV/√Hz
Input current noise
f > 100 kHz
C
0.6
pA/√Hz
Overdrive recovery time
Overdrive = ±0.5 V
C
80
ns
Output balance error
VOUT = 100 mV, f ≤ 2 MHz (differential input)
C
–57
dB
Closed-loop output impedance
f = 1 MHz (differential)
C
0.3
Ω
Channel-to-channel crosstalk (THS4522,
THS4524)
f = 10 kHz, measured differentially
C
–125
dB
Small-signal bandwidth
HARMONIC DISTORTION
2nd harmonic
3rd harmonic
DC PERFORMANCE
Open-loop voltage gain (AOL)
Input-referred offset voltage
Input offset voltage drift (3)
Input bias current (4)
Input bias current drift
(3)
Input offset current
Input offset current drift (3)
(1)
(2)
(3)
(4)
8
A
TA = +25°C
100
116
dB
A
±0.2
±2
mV
TA = –40°C to +85°C
B
±0.5
±3.5
TA = –40°C to +85°C
C
±2
TA = +25°C
B
0.65
0.85
μA
TA = –40°C to +85°C
B
0.75
0.95
μA
TA = –40°C to +85°C
B
±1.75
±2
TA = +25°C
B
±30
±180
TA = –40°C to +85°C
B
±30
±215
nA
TA = –40°C to +85°C
B
±100
±600
pA/°C
mV
μV/°C
nA/°C
nA
Test levels: (A) 100% tested at 25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
Not directly measurable; calculated using noise gain of 101 as described in the Applications section, Audio Performance.
Input offset voltage drift, input bias current drift, input offset current drift, and VOCM drift are average values calculated by taking data at
the maximum-range ambient-temperature end points, computing the difference, and dividing by the temperature range. Maximum drift is
set by the distribution of a large sampling of devices. Drift is not specified by a test or a quality assurance (QA) sample test.
Input bias current is positive out of the device.
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SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
Electrical Characteristics: VS+ – VS– = 3.3 V (continued)
At VS+ = 3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RL = 1 kΩ differential, G = 1 V/V, single-ended input,
differential output, and input and output referenced to midsupply, unless otherwise noted.
PARAMETER
TEST CONDITIONS
TEST
LEVEL (1)
MIN
TYP
MAX
UNIT
INPUT
TA = +25°C
A
–0.2
–0.1
V
TA = –40°C to +85°C
B
–0.1
0
V
TA = +25°C
A
1.9
2
TA = –40°C to +85°C
B
1.8
1.9
V
Common-mode rejection ratio (CMRR)
A
80
100
dB
Input impedance
C
0.7 pF
TA = +25°C
A
0.08
0.15
V
TA = –40°C to +85°C
B
0.09
0.2
V
TA = +25°C
A
3.0
3.1
TA = –40°C to +85°C
B
2.95
3.05
V
RL = 50 Ω
C
±35
mA
Common-mode input voltage low
Common-mode input voltage high
V
kΩ∥pF
OUTPUT
Output voltage low
Output voltage high
Output current drive (for linear operation)
V
POWER SUPPLY
Specified operating voltage
Quiescent operating current, per channel
B
2.5
3.3
5.5
V
TA = +25°C
A
0.9
1.0
1.2
mA
TA = –40°C to +85°C
B
0.85
1.0
1.25
mA
A
80
100
Power-supply rejection ratio (±PSRR)
dB
POWER DOWN
Enable voltage threshold
Assured on above 2.1 V
A
Disable voltage threshold
Assured off below 0.7 V
A
Disable pin bias current
1.6
0.7
2.1
V
1.6
V
C
1
μA
C
10
μA
Turn-on time delay
Time to VOUT = 90% of final value, VIN= 2 V,
RL = 200 Ω
B
108
ns
Turn-off time delay
Time to VOUT = 10% of original value, VIN= 2
V, RL = 200 Ω
B
88
ns
Small-signal bandwidth
C
23
MHz
Slew rate
C
55
Gain
A
Power-down quiescent current
VOCM VOLTAGE CONTROL
Common-mode offset voltage from VOCM input
Measured at VOUT with VOCM input driven,
VOCM = 1.65 V ±0.5 V
B
Input bias current
VOCM = 1.65 V ±0.5 V
0.98
V/μs
0.99
1.02
V/V
±2.5
±4
mV
μA
B
±5
±8
VOCM voltage range
A
1 0.8 to 2.5
2.3
Input impedance
C
72∥1.5
A
±1.5
Default output common-mode voltage offset from
(VS+– VS–) / 2
Measured at VOUT with VOCM input open
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kΩ∥pF
±5
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7.6 Electrical Characteristics: VS+ – VS– = 5 V
At VS+ = 5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, input and output referenced to midsupply, unless otherwise noted.
PARAMETER
TEST CONDITIONS
TEST
LEVEL (1)
MIN
TYP
MAX
UNIT
AC PERFORMANCE
VOUT = 100 mVPP, G = 1
C
145
MHz
VOUT = 100 mVPP, G = 2
C
50
MHz
VOUT = 100 mVPP, G = 5
C
20
MHz
VOUT = 100 mVPP, G = 10
C
9.5
MHz
Gain bandwidth product
VOUT = 100 mVPP, G = 10
C
95
MHz
Large-signal bandwidth
VOUT = 2 VPP, G = 1
C
145
MHz
Bandwidth for 0.1-dB flatness
VOUT = 2 VPP, G = 1
C
30
MHz
Rising slew rate (differential)
VOUT = 2-V Step, G = 1, RL = 200 Ω
C
490
V/μs
Falling slew rate (differential)
VOUT = 2-V Step, G = 1, RL = 200 Ω
C
600
V/μs
Overshoot
VOUT = 2-V Step, G = 1, RL = 200 Ω
C
1%
Undershoot
VOUT = 2-V Step, G = 1, RL = 200 Ω
C
2.6%
Rise time
VOUT = 2-V Step, G = 1, RL = 200 Ω
C
3.4
ns
Fall time
VOUT = 2-V Step, G = 1, RL = 200 Ω
C
3
ns
Settling time to 1%
VOUT = 2-V Step, G = 1, RL = 200 Ω
C
10
ns
f = 1 MHz, VOUT = 2 VPP, G = 1
C
–85
dBc
f = 1 kHz, VOUT = 1 VRMS, G = 1 (2),
differential input
C
–133
dBc
f = 1 MHz, VOUT = 2 VPP, G = 1
C
–91
dBc
f = 1 kHz, VOUT = 1 VRMS, G = 1 (2),
differential input
C
–141
dBc
Second-order intermodulation distortion
Two-tone, f1 = 2 MHz, f2 = 2.2 MHz,
VOUT = 2-VPP envelope
C
–86
dBc
Third-order intermodulation distortion
Two-tone, f1 = 2 MHz, f2 = 2.2 MHz,
VOUT = 2-VPP envelope
C
–93
dBc
Input voltage noise
f > 10 kHz
C
4.6
nV/√Hz
Input current noise
f > 100 kHz
C
0.6
pA/√Hz
SNR
VOUT = 5 VPP, 20 Hz to 22 kHz BW,
differential input
C
123
dBc
THD+N
f = 1 kHz , VOUT = 5 VPP, 20 Hz to 22 kHz
BW, differential input
C
112
dBc
Overdrive recovery time
Overdrive = ±0.5 V
C
75
ns
Output balance error
VOUT = 100 mV, f < 2 MHz, VIN differential
C
–57
dB
Closed-loop output impedance
f = 1 MHz (differential)
C
0.3
Ω
Channel-to-channel crosstalk (THS4522. THS4524)
f = 10 kHz, measured differentially
C
–125
dB
Small-signal bandwidth
HARMONIC DISTORTION
2nd harmonic
3rd harmonic
DC PERFORMANCE
Open-loop voltage gain (AOL)
Input-referred offset voltage
Input offset voltage drift (3)
Input bias current (4)
Input bias current drift (3)
(1)
(2)
(3)
(4)
10
A
TA = +25°C
100
119
dB
A
±0.24
±2
mV
TA = –40°C to +85°C
B
±0.5
±3.5
TA = –40°C to +85°C
C
±2
TA = +25°C
B
0.7
0.9
TA = –40°C to +85°C
B
0.9
1.1
μA
TA = –40°C to +85°C
B
±1.8
±2.2
nA/°C
mV
μV/°C
μA
Test levels: (A) 100% tested at 25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
Not directly measurable; calculated using noise gain of 101 as described in the Applications section, Audio Performance.
Input offset voltage drift, input bias current drift, input offset current drift, and VOCM drift are average values calculated by taking data at
the maximum-range ambient-temperature end points, computing the difference, and dividing by the temperature range. Maximum drift is
set by the distribution of a large sampling of devices. Drift is not specified by a test or a quality assurance (QA) sample test.
Input bias current is positive out of the device.
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SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
Electrical Characteristics: VS+ – VS– = 5 V (continued)
At VS+ = 5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, input and output referenced to midsupply, unless otherwise noted.
PARAMETER
TEST
LEVEL (1)
TYP
MAX
UNIT
TA = +25°C
B
±30
±180
nA
TA = –40°C to +85°C
B
±30
±215
nA
TA = –40°C to +85°C
B
±100
±600
pA/°C
TA = +25°C
A
–0.2
–0.1
V
TA = –40°C to +85°C
B
–0.1
0
V
TA = +25°C
A
3.6
3.7
TA = –40°C to +85°C
B
3.5
3.6
V
Common-mode rejection ratio (CMRR)
A
80
102
dB
Input impedance
C
Input offset current
Input offset current drift (3)
TEST CONDITIONS
MIN
INPUT
Common-mode input voltage low
Common-mode input voltage high
V
100∥0.7
kΩ∥pF
OUTPUT
Output voltage low
Output voltage high
Output current drive (for linear operation)
TA = +25°C
A
0.10
0.15
V
TA = –40°C to +85°C
B
0.115
0.2
V
TA = +25°C
A
4.7
4.75
TA = –40°C to +85°C
B
4.65
4.7
V
RL = 50 Ω
C
±55
mA
V
POWER SUPPLY
Specified operating voltage
Quiescent operating current, per channel
B
2.5
5.0
5.5
V
TA = +25°C
A
0.95
1.14
1.25
mA
TA = –40°C to +85°C
B
0.9
1.15
1.3
mA
A
80
100
Power-supply rejection ratio (±PSRR)
dB
POWER DOWN
Enable voltage threshold
Ensured on above 2.1 V
A
Disable voltage threshold
Ensured off below 0.7 V
A
Disable pin bias current
1.6
0.7
2.1
V
1.6
V
C
1
μA
C
20
μA
Turn-on time delay
Time to VOUT = 90% of final value,
VIN= 2 V, RL = 200 Ω
B
70
ns
Turn-off time delay
Time to VOUT = 10% of original value,
VIN= 2 V, RL = 200 Ω
B
60
ns
Small-signal bandwidth
C
23
MHz
Slew rate
C
55
Gain
A
Power-down quiescent current
VOCM VOLTAGE CONTROL
Common-mode offset voltage from VOCM input
Measured at VOUT with VOCM input driven,
VOCM = 2.5 V ±1 V
B
Input bias current
VOCM = 2.5V ±1 V
B
0.98
1.02
V/V
±5
±9
mV
±20
±25
μA
0.8 to 4.2
4
VOCM voltage range
A
Input impedance
C
46∥1.5
A
±1
Default output common-mode voltage offset from
(VS+– VS–) / 2
Measured at VOUT with VOCM input open
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V/μs
0.99
V
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±5
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7.7 Typical Characteristics
Table 2. Table of Graphs: VS+ – VS– = 3.3 V
FIGURE
Small-Signal Frequency Response
Figure 1
Large-Signal Frequency Response
Figure 2
Large- and Small-Signal Pulse Response
Figure 3
Slew Rate vs VOUT Step
Figure 4
Overdrive Recovery
Figure 5
10-kHz Output Spectrum on AP Analyzer
Figure 6
Harmonic Distortion vs Frequency
Figure 7
Harmonic Distortion vs Output Voltage at 1 MHz
Figure 8
Harmonic Distortion vs Gain at 1 MHz
Figure 9
Harmonic Distortion vs Load at 1 MHz
Figure 10
Harmonic Distortion vs VOCM at 1 MHz
Figure 11
Two-Tone, Second- and Third-Order Intermodulation Distortion vs Frequency
Figure 12
Single-Ended Output Voltage Swing vs Load Resistance
Figure 13
Main Amplifier Differential Output Impedance vs Frequency
Figure 14
Frequency Response vs CLOAD (RLOAD = 1 kΩ)
Figure 15
RO vs CLOAD (RLOAD = 1 kΩ)
Figure 16
Rejection Ratio vs Frequency
Figure 17
THS4522, THS4524 Crosstalk (Measured Differentially)
Figure 18
Turn-on Time
Figure 19
Turn-off Time
Figure 20
Input-Referred Voltage Noise and Current Noise Spectral Density
Figure 21
Main Amplifier Differential Open-Loop Gain and Phase
Figure 22
Output Balance Error vs Frequency
Figure 23
VOCM Small-Signal Frequency Response
Figure 24
VOCM Large-Signal Frequency Response
Figure 25
VOCM Input Impedance vs Frequency
Figure 26
12
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SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
Table 3. Table of Graphs: VS+ – VS– = 5 V
FIGURE
Small-Signal Frequency Response
Figure 27
Large-Signal Frequency Response
Figure 28
Large- and Small-Signal Pulse Response
Figure 29
Slew Rate vs VOUT Step
Figure 30
Overdrive Recovery
Figure 31
10-kHz Output Spectrum on AP Analyzer
Figure 33
Harmonic Distortion vs Frequency
Figure 34
Harmonic Distortion vs Output Voltage at 1 MHz
Figure 35
Harmonic Distortion vs Gain at 1 MHz
Figure 36
Harmonic Distortion vs Load at 1 MHz
Figure 37
Harmonic Distortion vs VOCM at 1 MHz
Figure 38
Two-Tone, Second- and Third-Order Intermodulation Distortion vs Frequency
Figure 39
Single-Ended Output Voltage Swing vs Load Resistance
Figure 40
Main Amplifier Differential Output Impedance vs Frequency
Figure 41
Frequency Response vs CLOAD (RLOAD = 1 kΩ)
Figure 42
RO vs CLOAD (RLOAD = 1 kΩ)
Figure 43
Rejection Ratio vs Frequency
Figure 44
THS4522, THS4524 Crosstalk (Measured Differentially)
Figure 45
Turn-on Time
Figure 46
Turn-off Time
Figure 47
Input-Referred Voltage Noise and Current Noise Spectral Density
Figure 48
Main Amplifier Differential Open-Loop Gain and Phase
Figure 49
Output Balance Error vs Frequency
Figure 50
VOCM Small-Signal Frequency Response
Figure 51
VOCM Large-Signal Frequency Response
Figure 52
VOCM Input Impedance vs Frequency
Figure 53
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7.8 Typical Characteristics: VS+ – VS– = 3.3 V
At VS+ = +3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, and input and output referenced to midsupply, unless otherwise noted.
6
6
3
G = 1 V/V
0
-3
Normalized Gain (dB)
Normalized Gain (dB)
3
G = 2 V/V
-6
G = 5 V/V
-9
-12
G = 10 V/V
-15
VS+ = 3.3 V
RL = 1 kW
VO = 100 mVPP
-18
-21
-24
100 k
G = 1 V/V
0
G = 2 V/V
-3
-6
G = 5 V/V
-9
-12
G = 10 V/V
-15
VS+ = 3.3 V
RL = 1 kW
VO = 2.0 VPP
-18
-21
1M
10 M
100 M
-24
100 k
1G
Figure 2. Large-Signal Frequency Response
Rising
500
0
Slew Rate (V/ms)
Differential VOUT (V)
0.5
0.5-V Step
-0.5
400
Falling
300
200
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 200 W
2-V Step
-1.0
100
-1.5
0
0
20
40
60
80
100
0
1
2
Time (ns)
1.5
2
1.0
1
0.5
0
0
-1
-0.5
VS+ = 3.3 V
G = 2 V/V
RF = 1 kW
RL = 200 W
-3
-4
0
100 200
-1.0
-1.5
-2.0
300 400 500 600
800
900
1k
Input Voltage (V)
Differential VOUT (V)
2.0
VOUT Diff
Input
3
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
VOUT = 5 VPP
0
5k
THS4521
10 k
Time (ns)
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15 k
20 k
25 k
30 k
35 k
Frequency (Hz)
Figure 5. Overdrive Recovery
14
5
4
Figure 4. Slew Rate vs VOUT
Magnitude (dBv)
4
3
Differential VOUT (V)
Figure 3. Large- and Small-Signal Pulse Response
-2
1G
600
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 200 W
1.0
100 M
Frequency (Hz)
Figure 1. Small-Signal Frequency Response
1.5
10 M
1M
Frequency (Hz)
Figure 6. 10-kHz Output Spectrum On AP Analyzer
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SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
Typical Characteristics: VS+ – VS– = 3.3 V (continued)
At VS+ = +3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, and input and output referenced to midsupply, unless otherwise noted.
Harmonic Distortion (dBc)
-50
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
VOUT = 2.0 VPP
-20
-30
-40
-50
Third
Harmonic
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
f = 1 MHz
-55
Harmonic Distortion (dBc)
-10
Second
Harmonic
-60
-70
-80
-90
-100
-60
-65
-70
-75
Second
Harmonic
-80
-85
-90
Third
Harmonic
-95
-110
-100
10
1
100
1
2
Frequency (MHz)
Figure 7. Harmonic Distortion vs Frequency
Figure 8. Harmonic Distortion vs VOUT at 1 MHz
-70
-75
Second
Harmonic
-80
-85
VS+ = 3.3 V
RF = 1 kW
RL = 1 kW
f = 1 MHz
VOUT = 2.0 VPP
Third
Harmonic
-90
-95
-100
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
6
5
4
VOUT (VPP)
-70
-75
Second
Harmonic
-80
-85
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
f = 1 MHz
VOUT = 2.0 VPP
-90
-95
Third
Harmonic
-100
1
3
2
5
4
6
7
8
9
10
0
100 200
Figure 9. Harmonic Distortion vs Gain at 1 MHz
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
f = 1 MHz
VOUT = 2.0 VPP
-40
-50
-60
-70
Second
Harmonic
-80
-90
Third
Harmonic
-100
0
0.5
1.0
1.5
800
900
1k
Figure 10. Harmonic Distortion vs Load at 1 MHz
-10
2.0
2.5
3.0
Intermodulation Distortion (dBc)
-30
300 400 500 600
Load (W)
Gain (V/V)
Harmonic Distortion (dBc)
3
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
VOUT = 2.0 VPP
envelope
-20
-30
-40
-50
Second
Intermodulation
-60
-70
Third
Intermodulation
-80
-90
-100
-110
1
10
100
Frequency (MHz)
VOCM (V)
Figure 11. Harmonic Distortion vs VOCM at 1 MHz
Figure 12. Two-Tone Intermodulation Distortion vs
Frequency
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Typical Characteristics: VS+ – VS– = 3.3 V (continued)
At VS+ = +3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, and input and output referenced to midsupply, unless otherwise noted.
3.5
Differential Output Impedance (W)
3.0
Single-Ended VOUT (V)
100
Linear Voltage Range
VOCM = 1.65 V
2.5
VOUT max
2.0
1.5
VOUT min
1.0
0.5
100
1k
10 k
0.1
Load Resistance (W)
Figure 14. Main Amplifier Differential Output Impedance vs
Frequency
1k
CL = 4.7 pF
RO = 150 W
CL = 1000 pF
RO = 7.15 W
-10
100
RO (W)
-5
CL = 100 pF
RO = 35.7 W
10
-15
CL = 10 pF
RO = 124 W
-20
1
-25
100 k
1M
100 M
10 M
10
1G
100
Frequency (Hz)
Figure 15. Frequency Response vs CLOAD RLOAD = 1 kΩ
Figure 16. RO vs CLOAD RLOAD = 1 kΩ
Channel-to-Channel Crosstalk (dB)
-100
100
90
80
CMRR
70
60
50
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
10 k
1000
CLOAD (pF)
110
Common-Mode Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
100 M
Figure 13. Single-Ended Output Voltage Swing vs Load
Resistance
0
-PSRR
+PSRR
-105
-110
-115
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
Active Channel VOUT = 1 VRMS
-120
-125
-130
-135
-140
100 k
10 M
1M
100 M
10
100
Frequency (Hz)
Figure 17. Rejection Ratio vs Frequency
16
10 M
1M
Frequency (Hz)
5
Normalized Gain (dB)
1
0.01
100 k
0
10
10
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1k
10 k
100 k
1M
Frequency (Hz)
Figure 18. THS4522, THS4524 Crosstalk (Differential
Measurement)
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SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
Typical Characteristics: VS+ – VS– = 3.3 V (continued)
At VS+ = +3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, and input and output referenced to midsupply, unless otherwise noted.
3.5
1.5
2.0
1.0
1.5
VOUT Diff
PD
1.0
2.5
100 120
0.6
1.0
0
80
0.8
VOUT Diff
PD
0.5
0
60
1.2
1.0
0
40
140 160
0.4
0.2
0
0
180 200
20
40
60
80
100 120
140 160
180 200
Time (ns)
Time (ns)
Figure 19. Turn-On Time
Figure 20. Turn-Off Time
100
0
120
Gain
Voltage
Noise
10
Current
Noise
1
OPen-Loop Gain (dB)
100
80
-45
60
40
-90
20
Phase
0
0.1
10
100
1k
10 k
100 k
1M
-135
-20
10
1
100
1k
Frequency (Hz)
10 k
100 k
1M
10 M 100 M
Frequency (Hz)
Figure 21. Input-Referred Voltage and Current Noise
Spectral Density
-20
Open-Loop Phase (Degrees)
Input-Referred Voltage Noise (nV/√Hz)
Input-Referred Current Noise (pA/√Hz)
1.4
1.5
0.5
20
1.6
2.0
0.5
0
1.8
Differential VOUT (V)
PD Pulse (V)
3.0
2.5
2.0
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 200 W
2.0
Differential VOUT (V)
3.0
3.5
2.5
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 200 W
PD Pulse (V)
4.0
Figure 22. Main Amplifier Differential Open-Loop Gain and
Phase
0
G = 0 dB
-30
-5
-35
Gain (dB)
Output Balance Error (dB)
-25
-40
-45
-50
-10
-15
G = 0 dB
VIN = -20 dBm
-55
-60
100 k
1M
10 M
100 M
-20
100 k
1M
Frequency (Hz)
Figure 23. Output Balance Error vs Frequency
10 M
100 M
1G
Frequency (Hz)
Figure 24. VOCM Small-Signal Frequency Response
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Typical Characteristics: VS+ – VS– = 3.3 V (continued)
At VS+ = +3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, and input and output referenced to midsupply, unless otherwise noted.
100 k
2.3
VOCM Input Impedance (W)
VOUT Common-Mode Voltage (V)
2.5
2.1
1.9
1.7
1.5
1.3
1.1
VS+ = 3.3 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
0.9
0.7
0.5
0
100
200
300
400
10 k
1k
100
100 k
1M
Figure 25. VOCM Large-Signal Pulse Response
18
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10 M
100 M
Frequency (Hz)
Time (ns)
Figure 26. VOCM Input Impedance vs Frequency
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7.9 Typical Characteristics: 5 V
At VS+ = +5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, and input and output referenced to midsupply, unless otherwise noted.
6
6
3
3
G = 1 V/V
-3
G = 2 V/V
-6
G = 5 V/V
-9
-12
G = 10 V/V
-15
-3
-21
-24
100 k
-12
100 M
G = 10 V/V
-15
-21
10 M
G = 5 V/V
-9
-18
1M
G = 2 V/V
-6
VS+ = 5.0 V
RL = 1 kW
VO = 100 mVPP
-18
G = 1 V/V
0
Normalized Gain (dB)
Normalized Gain (dB)
0
VS+ = 5.0 V
RL = 1 kW
VO = 2.0 VPP
-24
100 k
1G
10 M
1M
Frequency (Hz)
Figure 27. Small-Signal Frequency Response
1.5
Figure 28. Large-Signal Frequency Response
700
Falling
600
0
Slew Rate (V/ms)
Differential VOUT (V)
0.5
0.5-V Step
-0.5
500
Rising
400
300
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 200 W
200
2-V Step
-1.0
100
-1.5
0
0
20
40
60
80
100
0
1
2
3
Time (ns)
Figure 29. Large- and Small-Signal Pulse Response
-80
2
-90
2
1
0
0
-2
-1
VS+ = 5 V
G = 2 V/V
RF = 1 kW
RL = 200 W
100 200
-2
Input Voltage (V)
Differential VOUT (V)
4
0
5
6
7
Figure 30. Slew Rate vs VOUT
3
Harmonic Distortion (dBC)
VOUT Diff
Input
-6
4
Differential VOUT (V)
6
-4
1G
800
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 200 W
1.0
100 M
Frequency (Hz)
Second Harmonic
Third Harmonic
-100
-110
-120
-130
-140
-3
300 400 500 600 700 800 900
1k
-150
1
Time (ns)
10
100
Frequency (kHz)
Figure 31. Overdrive Recovery
1000
D001
Figure 32. Harmonic Distortion vs Frequency Below 1 MHz
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Typical Characteristics: 5 V (continued)
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
VS+ = 5.0 V
G = 1 V/V
RF = 1 kΩ
VOUT = 8 VPP
-10
THS4521
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
VOUT = 2.0 VPP
-20
Harmonic Distortion (dBc)
Magnitude (dBv)
At VS+ = +5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, and input and output referenced to midsupply, unless otherwise noted.
-30
-40
-50
Third
Harmonic
Second
Harmonic
-60
-70
-80
-90
-100
-110
0
5k
10 k
15 k
20 k
25 k
30 k
10
1
35 k
Figure 33. 10-kHz Output Spectrum On AP Analyzer at
VOUT = 8 VPP
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
f = 1 MHz
-75
-80
Figure 34. Harmonic Distortion vs Frequency
-70
Second
Harmonic
-85
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-70
Third
Harmonic
-90
-95
-75
Second
Harmonic
-80
-85
VS+ = 5 V
RF = 1 kW
RL = 1 kW
f = 1 MHz
VOUT = 2.0 VPP
-90
Third
Harmonic
-95
-100
-100
1
2
3
4
5
7
6
1
8
2
3
VOUT (VPP)
-75
-40
Second
Harmonic
-85
VS+ = 5 V
G = 1 V/V
RF = 1 kW
f = 1 MHz
VOUT = 2.0 VPP
-95
Third
Harmonic
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-30
-90
6
7
8
9
10
Figure 36. Harmonic Distortion vs Gain at 1 MHz
-70
-80
5
4
Gain (V/V)
Figure 35. Harmonic Distortion vs VOUT at 1 MHz
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
f = 1 MHz
VOUT = 2.0 VPP
-50
-60
-70
Third
Harmonic
-80
Second
Harmonic
-90
-100
-100
0
100 200
300 400 500 600
800
900
1k
0
1.0
Load (W)
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2.0
3.0
4.0
5.0
VOCM (V)
Figure 37. Harmonic Distortion vs Load at 1 MHz
20
100
Frequency (MHz)
Frequency (Hz)
Figure 38. Harmonic Distortion vs VOCM at 1 MHz
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Typical Characteristics: 5 V (continued)
At VS+ = +5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, and input and output referenced to midsupply, unless otherwise noted.
5.0
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
VOUT = 2.0 VPP
envelope
-20
-30
-40
-50
Linear Output Voltage Range
VOCM = 2.5 V
4.5
-60
Single-Ended VOUT (V)
Intermodulation Distortion (dBc)
-10
Second
Intermodulation
-70
-80
4.0
3.5
VOUT max
3.0
2.5
2.0
VOUT min
1.5
1.0
-90
Third
Intermodulation
-100
0.5
-110
0
10
1
10
100
100
Frequency (MHz)
10 k
Figure 40. Single-Ended Output Voltage Swing vs
Differential Load Resistance
Figure 39. Two-Tone Intermodulation Distortion vs
Frequency
100
5
CL = 4.7 pF
RO = 150 W
0
10
Normalized Gain (dB)
Differential Output Impedance (W)
1k
Load Resistance (W)
1
0.1
CL = 1000 pF
RO = 7.15 W
-5
-10
CL = 100 pF
RO = 35.7 W
-15
CL = 10 pF
RO = 124 W
-20
0.01
100 k
10 M
1M
-25
100 k
100 M
1M
10 M
100 M
1G
Frequency (Hz)
Frequency (Hz)
Figure 41. Main Amplifier Differential Output Impedance vs
Frequency
Figure 42. Frequency Response vs CLOAD RLOAD = 1 kΩ
1k
Common-Mode Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
110
RO (W)
100
10
1
VS+ = 5.0 V
G = 1 V/V
RF = 1 kW
100
90
80
CMRR
70
-PSRR
60
+PSRR
50
10
100
1000
10 k
100 k
1M
10 M
100 M
Frequency (Hz)
CLOAD (pF)
Figure 43. RO vs CLOAD RLOAD = 1 kΩ
Figure 44. Rejection Ratio vs Frequency
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Typical Characteristics: 5 V (continued)
At VS+ = +5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, and input and output referenced to midsupply, unless otherwise noted.
-110
-115
3.0
-120
-125
2.5
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 200 W
3.5
PD Pulse (V)
-105
4.0
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
Active Channel VOUT = 1 VRMS
2.0
2.5
1.5
2.0
1.0
1.5
-130
1.0
-135
0.5
0.5
VOUT Diff
PD
0
-140
10
100
1k
10 k
100 k
0
1M
20
40
60
1.6
1.4
1.2
2.0
1.0
1.5
0.8
0.6
1.0
0.4
VOUT Diff
PD
0.5
0.2
0
Input-Referred Voltage Noise (nV/√Hz)
Input-Referred Current Noise (pA/√Hz)
1.8
Differential VOUT (V)
PD Pulse (V)
2.0
VS+ = 5 V
G = 1 V/V
RF = 1 kW
RL = 200 W
2.5
0
0
20
40
60
80
100 120
140 160
Voltage
Noise
1
Current
Noise
0.1
10
100
1k
0
-20
60
40
-90
20
Phase
-135
-20
100 k
1M
10 M 100 M
Output Balance Error (dB)
OPen-Loop Gain (dB)
-45
Open-Loop Phase (Degrees)
80
0
G = 0 dB
-30
-35
-40
-45
-50
-55
-60
100 k
1M
Frequency (Hz)
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10 M
100 M
Frequency (Hz)
Figure 49. Main Amplifier Differential Open-Loop Gain and
Phase
22
1M
-25
100
10 k
100 k
Figure 48. Input-Referred Voltage and Current Noise
Spectral Density
Gain
1k
10 k
Frequency (Hz)
120
100
0
180 200
10
180 200
Figure 47. Turn-Off Time
10
140 160
100
Time (ns)
1
100 120
Figure 46. Turn-On Time
Figure 45. THS4522, THS4524 Crosstalk (Measured
Differentially)
3.0
80
Time (ns)
Frequency (Hz)
3.5
Differential VOUT (V)
Channel-to-Channel Crosstalk (dB)
-100
Figure 50. Output Balance Error vs Frequency
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Typical Characteristics: 5 V (continued)
At VS+ = +5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended
input, differential output, and input and output referenced to midsupply, unless otherwise noted.
0
VOUT Common-Mode Voltage (V)
3.5
Gain (dB)
-5
-10
-15
G = 0 dB
VIN = -20 dBm
-20
100 k
1M
3.3
3.1
2.9
2.7
2.5
2.3
2.1
VS+ = 5.0 V
G = 1 V/V
RF = 1 kW
RL = 1 kW
1.9
1.7
1.5
10 M
100 M
1G
0
100
200
Frequency (Hz)
300
400
Time (ns)
Figure 51. VOCM Small-Signal Frequency Response
Figure 52. VOCM Large-Signal Pulse Response
VOCM Input Impedance (W)
100 k
10 k
1k
100
100 k
1M
10 M
100 M
Frequency (Hz)
Figure 53. VOCM Input Impedance vs Frequency
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8 Detailed Description
8.1 Overview
The THS4521, THS4522, and THS4524 family is tested with the test circuits shown in this section; all circuits are
built using the available THS4521 evaluation module (EVM). For simplicity, power-supply decoupling is not
shown; see the layout in the Typical Applications section for recommendations. Depending on the test conditions,
component values change in accordance with Table 4 and Table 5, or as otherwise noted. In some cases the
signal generators used are ac-coupled and in others they dc-coupled 50-Ω sources. To balance the amplifier
when ac-coupled, a 0.22-μF capacitor and 49.9-Ω resistor to ground are inserted across RIT on the alternate
input; when dc-coupled, only the 49.9-Ω resistor to ground is added across RIT. A split power supply is used to
ease the interface to common test equipment, but the amplifier can be operated in a single-supply configuration
as described in the Typical Applications section with no impact on performance. Also, for most of the tests,
except as noted, the devices are tested with single-ended inputs and a transformer on the output to convert the
differential output to single-ended because common lab test equipment has single-ended inputs and outputs.
Similar or better performance can be expected with differential inputs and outputs.
As a result of the voltage divider on the output formed by the load component values, the amplifier output is
attenuated. The Atten column in Table 5 shows the attenuation expected from the resistor divider. When using a
transformer at the output (as shown in Figure 55), the signal sees slightly more loss because of transformer and
line loss; these numbers are approximate.
Table 4. Gain Component Values for Single-Ended Input (see Figure 54)
Gain
RF
RG
RIT
1 V/V
1 kΩ
1 kΩ
52.3 Ω
2 V/V
1 kΩ
487 Ω
53.6 Ω
5 V/V
1 kΩ
191 Ω
59.0 Ω
10 V/V
1 kΩ
86.6 Ω
69.8 Ω
1. Gain setting includes 50-Ω source impedance. Components are chosen to achieve gain and 50-Ω input
termination.
Table 5. Load Component Values For 1:1 Differential To Single-Ended Output Transformer (See
Figure 55)
RL
RO
ROT
100 Ω
24.9 Ω
Open
Atten
6 dB
200 Ω
86.6 Ω
69.8 Ω
16.8 dB
499 Ω
237 Ω
56.2 Ω
25.5 dB
1 kΩ
487 Ω
52.3 Ω
31.8 dB
1. Total load includes 50-Ω termination by the test equipment. Components are chosen to achieve load and 50Ω line termination through a 1:1 transformer.
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8.2 Functional Block Diagram
Vs+
(RGT Package) FB+
OUT+
–
IN–
5 kΩ
High-Aol +
Differential I/O
Amplifier –
IN+
5 kΩ
+
OUT–
(RGT Package) FB–
Vs+
275 kΩ
–
Vcm
Error
Amplifier
+
PD
Vocm
CMOS
Buffer
275 kΩ
Vs–
8.3 Feature Description
8.3.1 Frequency Response
The circuit shown in Figure 54 is used to measure the frequency response of the circuit.
A network analyzer is used as the signal source and the measurement device. The output impedance of the
network analyzer is dc-coupled and is 50 Ω. RIT and RG are chosen to impedance-match to 50 Ω and maintain
the proper gain. To balance the amplifier, a 49.9-Ω resistor to ground is inserted across RIT on the alternate
input.
The output is probed using a Tektronix high-impedance differential probe across the 953-Ω resistor and referred
to the amplifier output by adding back the 0.42-dB because of the voltage divider on the output.
From
50-W
Source
VIN+
RG
Calibrated
Differential
Probe
Across
RIT
1 kW
VS+
RIT
24.9 W
PD
Open
THS452x
0.22 mF
VOCM
Installed to
Balance
Amplifier
VS-
49.9 W
RIT
RG
24.9 W
953 W
Measure with
Differential
Probe
Across ROT
Open
0.22 mF
1 kW
Figure 54. Frequency Response Test Circuit
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Feature Description (continued)
8.3.2 Distortion
The circuit shown in Figure 55 is used to measure harmonic and intermodulation distortion of the amplifier.
A signal generator is used as the signal source and the output is measured with a Rhode and Schwarz spectrum
analyzer. The output impedance of the HP signal generator is ac-coupled and is 50 Ω. RIT and RG are chosen to
impedance match to 50 Ω and maintain the proper gain. To balance the amplifier, a 0.22-μF capacitor and 49.9Ω resistor to ground are inserted across RIT on the alternate input.
A low-pass filter is inserted in series with the input to reduce harmonics generated at the signal source. The level
of the fundamental is measured and then a notch filter is inserted at the output to reduce the fundamental so it
does not generate distortion in the input of the spectrum analyzer.
The transformer used in the output to convert the signal from differential to single-ended is an ADT1–1WT. It
limits the frequency response of the circuit so that measurements cannot be made below approximately 1 MHz.
From
50-W
Source
VIN+
RG
RF
VS+
RIT
VOUT
RO
PD
Open
THS452x
0.22 mF
RO
VOCM
Installed to
Balance
Amplifier
RIT
ROT
To 50-W
Test
Equipment
Open
0.22 mF
VS0.22 mF
1:1
RF
RG
49.9 W
Figure 55. Distortion Test Circuit
8.3.3 Slew Rate, Transient Response, Settling Time, Output Impedance, Overdrive, Output Voltage, and
Turn-On/Turn-Off Time
The circuit shown in Figure 56 is used to measure slew rate, transient response, settling time, output impedance,
overdrive recovery, output voltage swing, and ampliifer turn-on/turn-off time. Turn-on and turn-off time are
measured with the same circuit modified for 50-Ω input impedance on the PD input by replacing the 0.22-μF
capacitor with a 49.9-Ω resistor. For output impedance, the signal is injected at VOUT with VIN open; the drop
across the 2x 49.9-Ω resistors is then used to calculate the impedance seen looking into the amplifier output.
From
50-W
Source
VIN+
RG
1 kW
VS+
RIT
49.9 W
PD
Open
THS452x
0.22 mF
VOCM
Installed to
Balance
Amplifier
VS-
49.9 W
RIT
RG
49.9 W
VOUT-
VOUT+
To Oscilloscope
with 50-W Input
Open
0.22 mF
1 kW
Figure 56. Slew Rate, Transient Response, Settling Time, Output Impedance, Overdrive Recovery, VOUT
Swing, and Turn-On/Turn-Off Test Circuit
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Feature Description (continued)
8.3.4 Common-Mode and Power-Supply Rejection
The circuit shown in Figure 57 is used to measure the CMRR. The signal from the network analyzer is applied
common-mode to the input. Figure 58 is used to measure the PSRR of VS+ and VS–. The power supply under
test is applied to the network analyzer dc offset input. For both CMRR and PSRR, the output is probed using a
Tektronix high-impedance differential probe across the 953-Ω resistor and referred to the amplifier output by
adding back the 0.42-dB as a result of the voltage divider on the output. For these tests, the resistors are
matched for best results.
From
Network
Analyzer
VIN+
1 kW
1 kW
VS+
24.9 W
PD
Open
Calibrated
Differential
Probe
THS452x
24.9 W
0.22 mF
52.3 W
VOCM
Measure with
Differential
Probe
Open
0.22 mF
VS1 kW
953 W
1 kW
Figure 57. CMRR Test Circuit
Power
Supply
Network
Analyzer
1 kW
1 kW
Open
Calibrated Differential
Probe
Across
VS+ and GND
VS+
52.3 W
24.9 W
PD
Open
THS452x
0.22 mF
VOCM
VS-
24.9 W
953 W
Measure with
Differential
Probe
Across ROT
Open
0.22 mF
Open
1 kW
52.3 W
1 kW
Figure 58. PSRR Test Circuit
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Feature Description (continued)
8.3.5 VOCM Input
The circuit illustrated in Figure 59 is used to measure the frequency response and skew rate of the VOCM input.
Frequency response is measured using a Tektronix high-impedance differential probe, with
RCM = 0 Ω at the common point of VOUT+ and VOUT–, formed at the summing junction of the two matched 499-Ω
resistors, with respect to ground. The input impedance is measured using a Tektronix high-impedance differential
probe at the VOCM input with RCM = 10 kΩ and the drop across the 10-kΩ resistor is used to calculate the
impedance seen looking into the amplifier VOCM input.
The circuit shown in Figure 60 measures the transient response and slew rate of the VOCM input. A 1-V step input
is applied to the VOCM input and the output is measured using a 50-Ω oscilloscope input referenced back to the
amplifier output.
1 kΩ
1 kΩ
Open
VS+
49.9 Ω
499 Ω
PD
Open
THS452x
0.22 μF
499 Ω
RCM
VOCM
VS
Open
1 kW
1 kW
49.9 Ω
Measurement
Point for Bandwidth
From
Network
Analyzer
Calibrated
Measurement Differential
Probe
Point for ZIN
Across
49.9 Ω
Resistor
49.9 Ω
Figure 59. VOCM Input Test Circuit
1 kW
1 kW
Open
VS+
52.3 W
499 W
PD
Open
THS452x
0.22 mF
To Oscilloscope
50-W Input
499 W
49.9 W
VOCM
VS-
Step
Input
Open
1 kW
52.3 W
1 kW
49.9 W
Figure 60. VOCM Transient Response and Slew Rate Test Circuit
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Feature Description (continued)
8.3.6 Typical Performance Variation With Supply Voltage
The THS4521, THS4522, and THS4524 family of devices provide excellent performance across the specified
power-supply range of 2.5 V to 5.5 V with only minor variations. The input and output voltage compliance ranges
track with the power supply in nearly a 1:1 correlation. Other changes can be observed in slew rate, output
current drive, open-loop gain, bandwidth, and distortion. Table 6 shows the typical variation to be expected in
these key performance parameters.
8.3.7 Single-Supply Operation
To facilitate testing with common lab equipment, the THS4521EVM allows for split-supply operation; most of the
characterization data presented in this data sheet is measured using split-supply power inputs. The device can
easily be used with a single-supply power input without degrading performance.
Figure 61 shows a dc-coupled single-supply circuit with single-ended inputs. This circuit can also be applied to
differential input sources.
VIN+
RG
RF
VS+
RIT
RO
VOUT-
PD
PD Control
THS452x
0.22 mF
RO
VOUT+
VS-
VOCM
VOCM Control
0.22 mF
Optional;
installed to
balance
impedance seen
at VIN+
RIT
RG
RF
Figure 61. THS4521 DC-Coupled Single-Supply With Single-Ended Inputs
The input common-mode voltage range of the THS4521, THS4522, and THS4524 family is designed to include
the negative supply voltage. in the circuit shown in Figure 61, the signal source is referenced to ground. VOCM is
set by an external control source or, if left unconnected, the internal circuit defaults to midsupply. Together with
the input impedance of the amplifier circuit, RIT provides input termination, which is also referenced to ground.
Note that RIT and optional matching components are added to the alternate input to balance the impedance at
signal input.
Table 6. Typical Performance Variation Versus Power-Supply Voltage
VS = 5 V
VS = 3.3 V
VS = 2.5 V
–3-dB Small-signal bandwidth
PARAMETER
145 MHz
135 MHz
125 MHz
Slew rate (2-V step)
490 V/μs
420 V/μs
210 V/μs
Second harmonic
–85 dBc
–85 dBc
–84 dBc
Third harmonic
–91 dBc
–90 dBc
–88 dBc
Open-loop gain (dc)
119 dB
116 dB
115 dB
Linear output current drive
55 mA
35 mA
24 mA
Harmonic distortion at 1 MHz, 2 VPP, RL = 1 kΩ
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8.3.8 Low-Power Applications and the Effects of Resistor Values on Bandwidth
For low-power operation, it may be necessary to increase the gain setting resistors values to limit current
consumption and not load the source. Using larger value resistors lowers the bandwidth of the THS4521,
THS4522, and THS4524 family as a result of the interactions between the resistors, the device parasitic
capacitance, and printed circuit board (PCB) parasitic capacitance. Figure 62 shows the small-signal frequency
response with 1-kΩ and 10-kΩ resistors for RF, RG, and RL (impedance is assumed to typically increase for all
three resistors in low-power applications).
SMALL-SIGNAL FREQUENCY RESPONSE
Gain = 1, RF = RG = RL = 1 kΩ and 10 kΩ
6
1 kΩ
3
Signal Gain (dB)
0
–3
10 kΩ
–6
–9
–12
–15
–18
VS+ = 5.0 V
–21
VO = 100 mVPP
–24
Gain = 1 V/V
0.1
1
10
100
1000
Frequency (MHz)
Figure 62. THS4521 Frequency Response With Various Gain Setting and Load Resistor Values
8.3.9 Frequency Response Variation due to Package Options
Users can see variations in the small-signal (VOUT = 100 mVPP) frequency response between the available
package options for the THS4521, THS4522, and THS4524 family as a result of parasitic elements associated
with each package and board layout changes. Figure 63 shows the variance measured in the lab; this variance is
to be expected even when using a good layout.
SMALL-SIGNAL FREQUENCY RESPONSE
Device and Package Option Comparison
6
THS4522,
THS4524
3
Signal Gain (dB)
0
THS4521
SOIC
THS4521
MSOP
-3
-6
-9
-12
-15
-18
-21
-24
VS+ = 5.0 V
Gain = 1 V/V
RF = 1 kW
RL = 1 kW
0.1
1
10
100
1000
Frequency (MHz)
Figure 63. Small-Signal Frequency Response: Package Variations
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8.3.10 Driving Capacitive Loads
The THS4521, THS4522, and THS4524 family is designed for a nominal capacitive load of 1 pF on each output
to ground. When driving capacitive loads greater than 1 pF, it is recommended to use small resistors (RO) in
series with the output, placed as close to the device as possible. Without RO, capacitance on the output interacts
with the output impedance of the amplifier and causes phase shift in the loop gain of the amplifier that reduces
the phase margin. This reduction in phase margin results in frequency response peaking; overshoot, undershoot,
and/or ringing when a step or square-wave signal is applied; and may lead to instability or oscillation. Inserting
RO isolates the phase shift from the loop gain path and restores the phase margin, but it also limits bandwidth.
Figure 64 shows the recommended values of RO versus capacitive loads (CL), and Figure 65 shows an
illustration of the frequency response with various values.
RECOMMENDED RO vs CLOAD
For Flat Frequency Response
FREQUENCY RESPONSE vs CLOAD
5
RO = 150 W
CL = 4.7 pF
each output
1k
Normalized Gain (dB)
Series Output Resistor (W)
0
100
10
1
VS+ = 5.0 V
Gain = 1 V/V
RF = 1 kW
RL = 1 kW Differential
VOUT = 100 mVPP
-5
-15
-25
100
RO = 37.5 W
CL = 100 pF each output
-10
-20
10
RO = 7.15 W
CL = 1000 pF each output
1000
VS+ = 5.0 V, Gain = 1 V/V
RO = 124 W
RF = 1 kW differential
CL = 10 pF
RL = 1 kW
each output
VOUT = 100 mVPP
0.1
1
10
100
1000
CLOAD (pF)
Frequency (MHz)
Figure 64. Recommended Series Output Resistor Versus
Capacitive Load for Flat Frequency Response, With RLOAD
= 1 kΩ
Figure 65. Frequency Response for Various RO and CL
Values, With RLOAD = 1 kΩ
8.3.11 Audio Performance
The THS4521, THS4522, and THS4524 family provide excellent audio performance with very low quiescent
power. To show performance in the audio band, the device was tested with a SYS-2722 audio analyzer from
Audio Precision. THD+N and FFT tests were performed at 1-VRMS output voltage. Performance is the same on
both 3.3-V and 5-V supplies. Figure 66 shows the test circuit used; see Figure 67 and Figure 68 for the
performance of the analyzer using internal loopback mode (generator) together with the THS4521.
1 kW
1 kW
VS+
VIN+
From
AP
Analyzer
VOUT-
24.9 W
VIN-
Open
PD
THS452x
0.22 mF
VOCM
VS1 kW
VOUT+
24.9 W
To AP
Analyzer
Open
0.22 mF
1 kW
Figure 66. THS4521 AP Analyzer Test Circuit
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Note that the harmonic distortion performance is very close to the same with and without the device meaning the
THS4521 performance is actually much better than can be directly measured by this method. The actual device
performance can be estimated by placing the device in a large noise gain and using the reduction in loop gain
correction. The THS4521 is placed in a noise gain of 101 by adding a 10-Ω resistor directly across the input
terminals of the circuit shown in Figure 66. This test was performed using the AP instrument as both the signal
source and the analyzer. The second-order harmonic distortion at 1 kHz is estimated to be –122 dBc with VO =
1VRMS; third-order harmonic distortion is estimated to be –141 dBc. The third-order harmonic distortion result
matches exactly with design simulations, but the second-order harmonic distortion is about 10 dB worse. This
result is not unexpected because second-order harmonic distortion performance with a differential signal
depends heavily on cancellation as a result of the differential nature of the signal, which depends on board
layout, bypass capacitors, external cabling, and so forth. Note that the circuit of Figure 66 is also used to
measure crosstalk between channels.
The THS4521 shows even better THD+N performance when driving higher amplitude output, such as 5 VPP that
is more typical when driving an ADC. To show performance with an extended frequency range, higher gain, and
higher amplitude, the device was tested with 5 VPP up to 80 kHz with the AP. Figure 69 shows the resulting
THD+N graph with no weighting.
10-kHz OUTPUT SPECTRUM
THS4521 on AP Analyzer
TOTAL HARMONIC DISTORTION + NOISE
THS4521 Measured on AP Analyzer
-50
-60
Magnitude (dBv)
THD+N (dBv)
-70
-80
-90
THS4521
-100
Signal Generator
-110
-120
0
5
10
15
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
VS+ = 5.0 V
G = 1 V/V
RF = 1 kW
VOUT = 1 VRMS
0
5k
Generator
THS4521
10 k
Frequency (kHz)
15 k
20 k
25 k
30 k
35 k
Frequency (Hz)
Figure 67. THS4521 1-VRMS 20-Hz to 20-kHz Thd+N
Figure 68. THS4521 1-VRMS 10-kHz FFT Plot
TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY (No Weighting)
-95
-97
-99
THD+N (dB)
-101
-103
-105
-107
-109
-111
-113
-115
10
100
1k
10 k
100 k
Frequency (Hz)
Figure 69. Thd+N (No Weighting) on Ap, 80-kHz Bandwidth at G = 1 With 5-V PP Output
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8.3.12 Audio On/Off Pop Performance
The THS4521 was tested to show on and off pop performance by connecting a speaker between the differential
outputs and switching the power supply on and off, and also by using the PD function of the THS4521. Testing
was done with and without tones. During these tests, no audible pop could be heard.
With no tone input, Figure 70 shows the pop performance when switching power on to the THS4521 and
Figure 71 shows the device performance when turning the power off. The transients during power on and off
illustrate that no audible pop should be heard
POWER-SUPPLY TURN-OFF POP PERFORMANCE
POWER-SUPPLY TURN-ON POP PERFORMANCE
5.0
5.0
4.5
4.5
4.0
4.0
Power
Supply
Power
Supply
3.5
Outputs
Voltage (V)
Voltage (V)
3.5
3.0
2.5
2.0
2.5
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
Outputs
3.0
0
0
50
100
150
200
0
50
100
150
200
Time (ms)
Time (ms)
Figure 70. THS4521 Power-Supply Turn-On Pop
Performance
Figure 71. THS4521 Power-Supply Turn-Off Pop
Performance
With no tone input, Figure 72 shows the pop performance using the PD pin to enable the THS4521, and
Figure 73 shows performance using the PD pin to disable the device. Again, the transients during power on and
off show that no audible pop should be heard. It should also be noted that the turn on/off times are faster using
the PD pin technique.
PD ENABLE POP PERFORMANCE
5.0
4.5
4.5
4.0
4.0
PD
3.5
PD
3.5
Outputs
3.0
Voltage (V)
Voltage (V)
PD DISABLE POP PERFORMANCE
5.0
2.5
2.0
2.5
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
Outputs
3.0
0
0
50
100
150
200
0
50
100
150
200
Time (ms)
Time (ms)
Figure 72. THS4521 PD Pin Enable Pop Performance
Figure 73. THS4521 PD Pin Disable Pop Performance
The power on/off pop performance of the THS4521, whether by switching the power supply or when using the
power-down function built into the chip, shows that no special design should be required to prevent an audible
pop.
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8.4 Device Functional Modes
This wideband FDA requires external resistors for correct signal-path operation. When configured for the desired
input impedance and gain setting with these external resistors, the amplifier can be either on with the PD pin
asserted to a voltage greater than VS– + 1.7 V, or turned off by asserting PD low. Disabling the amplifier shuts off
the quiescent current and stops correct amplifier operation. The signal path is still present for the source signal
through the external resistors.
The VOCM control pin sets the output average voltage. Left open, VOCM defaults to an internal midsupply value.
Driving this high-impedance input with a voltage reference within its valid range sets a target for the internal VCM
error amplifier.
8.4.1 Operation from Single-Ended Sources to Differential Outputs
One of the most useful features supported by the FDA device is an easy conversion from a single-ended input to
a differential output centered on a user-controlled, common-mode level. While the output side is relatively
straightforward, the device input pins move in a common-mode sense with the input signal. This common-mode
voltage at the input pins moving with the input signal acts to increase the apparent input impedance to be greater
than the RG value. This input-active-impedance issue applies to both ac- and dc-coupled designs, and requires
somewhat more complex solutions for the resistors to account for this active impedance, as shown in the
following subsections.
8.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
When the signal path can be ac-coupled, the dc biasing for the THS452x family becomes a relatively simple task.
In all designs, start by defining the output common-mode voltage. The ac-coupling issue can be separated for the
input and output sides of an FDA design. The input can be ac-coupled and the output dc-coupled, or the output
can be ac-coupled and the input dc-coupled, or they can both be ac-coupled.
One situation where the output might be dc-coupled (for an ac-coupled input), is when driving directly into an
ADC where the VOCM control voltage uses the ADC common-mode reference to directly bias the FDA output
common-mode to the required ADC input common-mode. In any case, the design starts by setting the desired
VOCM.
When an ac-coupled path follows the output pins, the best linearity is achieved by operating VOCM at midsupply.
The VOCM voltage must be within the linear range for the common-mode loop, as specified in the headroom
specifications (approximately 0.91 V greater than the negative supply and 1.1 V less than the positive supply). If
the output path is also ac-coupled, simply letting the VOCM control pin float is usually preferred in order to get a
midsupply default VOCM bias with minimal elements. To limit noise, place a 0.1-µF decoupling capacitor on the
VOCM pin to ground.
After VOCM is defined, check the target output voltage swing to ensure that the VOCM plus the positive or negative
output swing on each side do not clip into the supplies. If the desired output differential swing is defined as VOPP,
divide by 4 to obtain the ±VP swing around VOCM at each of the two output pins (each pin operates 180° out of
phase with the other). Check that VOCM ±VP does not exceed the absolute supply rails for this rail-to-rail output
(RRO) device.
Going to the device input pins side, because both the source and balancing resistor on the non-signal input side
are dc-blocked (see Figure 74), no common-mode current flows from the output common-mode voltage, thus
setting the input common-mode equal to the output common-mode voltage.
This input headroom also sets a limit for higher VOCM voltages. Because the input VICM is the output VOCM for accoupled sources, the 1.2-V minimum headroom for the input pins to the positive supply overrides the 1.1-V
headroom limit for the output VOCM. Also, the input signal moves this input VICM around the dc bias point, as
described in the section Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA.
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Device Functional Modes (continued)
THS452x Wideband,
Fully-Differential Amplifier
50-Input Match,
Gain of 2 V/V from Rt,
Single-Ended Source to
Differential Output
C1
100 nF
50-Ω
Source
Rf1
1.02 kΩ
Vcc
Rg1
499 Ω
–
Rt
52.3 Ω
Vocm
Output
Rload
Measurement
500 Ω
Point
+
FDA
–
+
PD
Rg2
523 Ω
Vcc
C2
100 nF
Rf2
1.02 kΩ
Figure 74. AC-coupled, Single-ended Source to a Differential Gain of 2 V/V Test Circuit
8.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
The output considerations remain the same as for the ac-coupled design. Again, the input can be dc-coupled
while the output is ac-coupled. A dc-coupled input with an ac-coupled output might have some advantages to
move the input VICM down if the source is ground referenced. When the source is dc-coupled into the THS452x
family (see Figure 75 ), both sides of the input circuit must be dc-coupled to retain differential balance. Normally,
the non-signal input side has an RG element biased to whatever the source midrange is expected to be.
Providing this midscale reference gives a balanced differential swing around VOCM at the outputs.
Often, RG2 is simply grounded for dc-coupled, bipolar-input applications. This configuration gives a balanced
differential output if the source is swinging around ground. If the source swings from ground to some positive
voltage, grounding RG2 gives a unipolar output differential swing from both outputs at VOCM (when the input is at
ground) to one polarity of swing. Biasing RG2 to an expected midpoint for the input signal creates a differential
output swing around VOCM.
One significant consideration for a dc-coupled input is that VOCM sets up a common-mode bias current from the
output back through RF and RG to the source on both sides of the feedback. Without input balancing networks,
the source must sink or source this dc current. After the input signal range and biasing on the other RG element
is set, check that the voltage divider from VOCM to VIN through RF and RG (and possibly RS) establishes an input
VICM at the device input pins that is in range.
If the average source is at ground, the negative rail input stage for the THS452x family is in range for
applications using a single positive supply and a positive output VOCM setting because this dc current lifts the
average FDA input summing junctions up off of ground to a positive voltage (the average of the V+ and V– input
pin voltages on the FDA).
THS452x Wideband,
Fully-Differential Amplifier
50-Input Match,
Gain of 5 V/V from Rt,
Single-Ended Source to
Differential Step-Response Test
Rf1
1 kΩ
Vcc
Rg1
187 Ω
50-Ω
Source
–
Rt
59 Ω
Vocm
FDA
+
R1
500 Ω
–
+
Rg2
215 Ω
Output
Measurement
Point
PD
Vcc
Rf2
1 kΩ
Figure 75. DC-Coupled, Single-Ended-to-Differential, Set for a Gain of 5 V/V
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Device Functional Modes (continued)
8.4.1.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA
The design equations for setting the resistors around an FDA to convert from a single-ended input signal to
differential output can be approached from several directions. Here, several critical assumptions are made to
simplify the results:
• The feedback resistors are selected first and set equal on the two sides.
• The dc and ac impedances from the summing junctions back to the signal source and ground (or a bias
voltage on the non-signal input side) are set equal to retain feedback divider balance on each side of the
FDA.
Both of these assumptions are typical for delivering the best dynamic range through the FDA signal path.
After the feedback resistor values are chosen, the aim is to solve for the RT (a termination resistor to ground on
the signal input side), RG1 (the input gain resistor for the signal path), and RG2 (the matching gain resistor on the
nonsignal input side); see Figure 74 and Figure 75. The same resistor solutions can be applied to either ac- or
dc-coupled paths. Adding blocking capacitors in the input-signal chain is a simple option. Adding these blocking
capacitors after the RT element (as shown in Figure 74) has the advantage of removing any dc currents in the
feedback path from the output VOCM to ground.
Earlier approaches to the solutions for RT and RG1 (when the input must be matched to a source impedance, RS)
follow an iterative approach. This complexity arises from the active input impedance at the RG1 input. When the
FDA is used to convert a single-ended signal to differential, the common-mode input voltage at the FDA inputs
must move with the input signal to generate the inverted output signal as a current in the RG2 element. A more
recent solution is shown as Equation 1, where a quadratic in RT can be solved for an exact value. This quadratic
emerges from the simultaneous solution for a matched input impedance and target gain. The only inputs required
are:
1. The selected RF value.
2. The target voltage gain (Av) from the input of RT to the differential output voltage.
3. The desired input impedance at the junction of RT and RG1 to match RS.
Solving this quadratic for RT starts the solution sequence, as shown in Equation 1:
RS 2
2R S (2R F +
A )
2R F RS2 A V
2 V
R T2 - R T
=0
2R F (2 + A V ) - R S A V (4 + A V ) 2R F (2 + A V ) - R S A V (4 + A V)
(1)
Being a quadratic, there are limits to the range of solutions. Specifically, after RF and RS are chosen, there is
physically a maximum gain beyond which Equation 1 starts to solve for negative RT values (if input matching is a
requirement). With RF selected, use Equation 2 to verify that the maximum gain is greater than the desired gain.
é
ù
RF
ê
ú
4
ú
æ RF
ö ê
RS
ú
A V(MAX) = ç
- 2 ÷ ´ ê1 + 1 +
2
çRS
÷ ê
æ RF
ö ú
è
ø
ê
- 2÷ ú
ç
çRS
÷ ú
ê
è
ø û
ë
(2)
If the achievable AV(MAX) is less than desired, increase the RF value. After RT is derived from Equation 1, the RG1
element is given by Equation 3:
RF
2
- RS
AV
R G1 =
RS
1+
RT
(3)
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Device Functional Modes (continued)
Then, the simplest approach is to use a single RG2 = RT || RS + RG1 on the non-signal input side. Often, this
approach is shown as the separate RG1 and RS elements. Using these separate elements provides a better
divider match on the two feedback paths, but a single RG2 is often acceptable. A direct solution for RG2 is given
as Equation 4:
RF
2
AV
R G2 =
RS
1+
RT
(4)
This design proceeds from a target input impedance matched to RS, signal gain Av from the matched input to the
differential output voltage, and a selected RF value. The nominal RF value chosen for the THS452x family
characterization is 402 Ω. As discussed previously, going lower improves noise and phase margin, but reduces
the total output load impedance possibly degrading harmonic distortion. Going higher increases the output noise,
and might reduce the loop-phase margin because of the feedback pole to the input capacitance, but reduces the
total loading on the outputs.
Using Equation 2 to Equation 4 to sweep the target gain from 1 to AV(MAX) < 14.3 V/V gives Table 7, which shows
exact values for RT, RG1, and RG2, where a 50-Ω source must be matched while setting the two feedback
resistors to 402 Ω. One possible solution for 1% standard values is shown, and the resulting actual input
impedance and gain with % errors to the targets are also shown in Table 7.
Table 7. Rf = 1 kΩ, Matched Input to 50 Ω, Gain from 1 V to 10 V/V Single to Differential (1)
Av
Rt, EXACT
(Ω)
Rt 1%
Rg1,
EXACT (Ω)
Rg1 1%
Rg2,
EXACT (Ω)
Rg2 1%
ACTUAL
ZIN
%ERR TO
Rs
ACTUAL
GAIN
%ERR TO
Av
1
51.95
52.3
996.92
1000
1022.48
1020
50.32
0.64%
0.997
–0.30%
2
53.59
53.6
491.51
487
517.37
523
49.95
–0.10%
2.018
0.88%
3
55.21
54.9
322.74
324
348.90
348
49.70
–0.60%
2.989
–0.36%
4
56.88
56.2
238.14
237
264.60
267
49.37
–1.25%
4.017
0.43%
5
58.63
59
189.45
191
216.51
215
50.23
0.47%
4.964
–0.71%
6
60.47
60.4
155.01
154
182.37
182
49.82
–0.37%
6.033
0.56%
7
62.42
61.9
130.39
130
158.05
158
49.51
–0.98%
7.017
0.25%
8
64.49
64.9
112.97
113
141.21
140
50.12
0.23%
7.998
–0.02%
9
66.70
66.5
98.31
97.6
126.85
127
49.69
–0.62%
9.050
0.56%
10
69.06
69.8
87.40
86.6
116.53
118
50.29
0.57%
10.069
0.69%
(1)
RF = 1 kΩ, RS = 50 Ω.
These equations and design flow apply to any FDA. Using the feedback resistor value as a starting point is
particularly useful for current-feedback-based FDAs such as the LMH6554, where the value of these feedback
resistors determines the frequency response flatness. Similar tables can be built using the equations provided
here for other source impedances, RF values, and gain ranges.
The TINA model correctly shows this actively-set input impedance in the single-ended to differential
configuration, and is a good tool to validate the gains, input impedances, response shapes, and noise issues.
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8.4.1.4 Input Impedance for the Single-Ended to Differential FDA Configuration
The designs so far have included a source impedance, RS, that must be matched by RT and RG1. The total
impedance at the junction of RT and RG1 for the circuit of Figure 75 is the parallel combination of RT to ground,
and the ZA (active impedance) presented by RG1. The expression for ZA, assuming RG2 is set to obtain the
differential divider balance, is given by Equation 5:
æ
R G1 ö æ
RF ö
ç1 +
÷ ç1 +
÷
ç
R G2 ÷ø çè
R G1 ÷ø
è
ZA = R G1
RF
2+
R G2
(5)
For designs that do not need impedance matching, for instance where the input is driven from the low-impedance
output of another amplifier, RG1 = RG2 is the single-to-differential design used without an RT to ground. Setting
RG1 = RG2 = RG in Equation 5 produces Equation 6, which is the input impedance of a simple-input FDA driven
from a low-impedance, single-ended source.
æ
RF ö
ç1 +
÷
ç
R G ÷ø
è
ZA = 2R G
RF
2+
RG
(6)
In this case, setting a target gain as RF / RG ≡ α, and then setting the desired input impedance allows the RG
element to be resolved first. Then the RF is set to get the target gain. For example, targeting an input impedance
of 200 Ω with a gain of 4 V/V, Equation 7 calculates the RG value. Multiplying this required RG value by a gain
of 4 gives the RF value and the design of Figure 76.
2+a
R G = ZA
2 (1 + a )
(7)
THS452x Wideband,
Fully-Differential Amplifier
Rf1
480 Ω
200-Ω Input Impedance
Gain of 4 V/V Design
Vcc
Rg1
120 Ω
–
+
–
Vocm
Vs
FDA
+
+
Rg2
120 Ω
R1
500 Ω
–
Output
Measurement
Point
PD
Vcc
Rf2
480 Ω
Figure 76. 200-Ω Input Impedance, Single-Ended to Differential DC-Coupled Design With Gain of 4 V/V
After being designed, this circuit can also be ac-coupled by adding blocking caps in series with the two 120-Ω RG
resistors. This active input impedance has the advantage of increasing the apparent load to the prior stage using
lower resistors values, leading to lower output noise for a given gain target.
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8.4.2 Differential-Input to Differential-Output Operation
In many ways, this method is a much simpler way to operate the FDA from a design-equations perspective.
Again, assuming the two sides of the circuit are balanced with equal RF and RG elements, the differential input
impedance is now just the sum of the two RG elements to a differential inverting summing junction. In these
designs, the input common-mode voltage at the summing junctions does not move with the signal, but must be
dc biased in the allowable range for the input pins with consideration given to the voltage headroom required
from each supply. Slightly different considerations apply to ac- or dc-coupled, differential-in to differential-out
designs, as described in the following sections.
8.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
There are two typical ways to use the THS452x family with an ac-coupled differential source. In the first method,
the source is differential and can be coupled in through two blocking capacitors. The second method uses either
a single-ended or a differential source and couples in through a transformer (or balun). Figure 77 shows a typical
blocking capacitor approach to a differential input. An optional differential-input termination resistor (RM) is
included in this design. This RM element allows the input RG resistors to be scaled up while still delivering lower
differential input impedance to the source. In this example, the RG elements sum to show a 500-Ω differential
impedance, while the RM element combines in parallel to give a net 100-Ω, ac-coupled, differential impedance to
the source. Again, the design proceeds ideally by selecting the RF element values, then the RG to set the
differential gain, then an RM element (if needed) to achieve the target input impedance. Alternatively, the RM
element can be eliminated, the RG elements set to the desired input impedance, and RF set to the get the
differential gain (RF / RG).
THS452x Wideband,
Fully-Differential Amplifier
Rf1
1 kΩ
C1
100 nF
Vcc
Rg1
250 Ω
–
Downconverter
Differential
Output
Vocm
C2
100 nF
Rm
125 Ω
Rg2
250 Ω
FDA
+
R1
500 Ω
–
+
Output
Measurement
Point
PD
Vcc
Rf2
1 kΩ
Figure 77. Example Down-Converting Mixer Delivering an AC-Coupled Differential Signal to the THS452x
The dc biasing here is very simple. The output VOCM is set by the input control voltage; and because there is no
dc-current path for the output common-mode voltage, that dc bias also sets the input pins common-mode
operating points.
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8.5 Programming
8.5.1 Input Common-Mode Voltage Range
The input common-mode voltage of a fully-differential amplifier is the voltage at the + and – input pins of the
device.
It is important to not violate the input common-mode voltage range (VICR) of the amplifier. Assuming the amplifier
is in linear operation, the voltage across the input pins is only a few millivolts at most. Therefore, finding the
voltage at one input pin determines the input common-mode voltage of the amplifier.
Treating the negative input as a summing node, the voltage is given by Equation 8:
VOUT+ ´
RF
RG
+ VIN- ´
R G + RF
RG + RF
(8)
To determine the VICR of the amplifier, the voltage at the negative input is evaluated at the extremes of VOUT+. As
the gain of the amplifier increases, the input common-mode voltage becomes closer and closer to the input
common-mode voltage of the source.
8.5.1.1 Setting the Output Common-Mode Voltage
The output common-model voltage is set by the voltage at the VOCM pin. The internal common-mode control
circuit maintains the output common-mode voltage within 5-mV offset (typ) from the set voltage. If left
unconnected, the common-mode set point is set to midsupply by internal circuitry, which may be overdriven from
an external source.
Figure 78 represents the VOCM input. The internal VOCM circuit has typically 23 MHz of –3 dB bandwidth, which is
required for best performance, but it is intended to be a dc bias input pin. A 0.22-μF bypass capacitor is
recommended on this pin to reduce noise. The external current required to overdrive the internal resistor divider
is given approximately by the formula in Equation 9:
2VOCM - (VS+ - VS-)
IEXT =
50 kW
where:
•
VOCM is the voltage applied to the VOCM pin
(9)
VS+
275 kΩ
To internal
VOCM circuit
IEXT
VOCM
275 kΩ
VS–
Figure 78. VOCM Input Circuit
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The following circuits show application information for the THS4521, THS4522, and THS4524 family. For
simplicity, power-supply decoupling capacitors are not shown in these diagrams; see Layout Guidelines for
suggested guidelines. For more details on the use and operation of fully differential amplifiers, refer to the
Application Report Fully-Differential Amplifiers (SLOA054), available for download from the TI web site at
www.ti.com.
9.2 Typical Applications
9.2.1 Audio ADC Driver Performance: THS4521 and PCM4204 Combined Performance
To show achievable performance with a high-performance audio ADC, the THS4521 is tested as the drive
amplifier for the PCM4204. The PCM4204 is a high-performance, four-channel ADC designed for professional
and broadcast audio applications. The PCM4204 architecture uses a 1-bit delta-sigma (ΔΣ) modulator per
channel that incorporates an advanced dither scheme for improved dynamic performance, and supports PCM
output data. The PCM4204 provides a flexible serial port interface and many other advanced features. Refer to
the PCM4204 product data sheet for more information.
The PCM4204EVM can test the audio performance of the THS4521 as a drive amplifier. The standard
PCM4204EVM is provided with four OPA1632 fully-differential amplifiers, which use the same device pinout as
the THS4521. For testing, one of these amplifiers is replaced with a THS4521 device in same package (MSOP),
and the power supply changes to a single-supply +5V. Figure 79 shows the modifications made to the circuit.
Note the resistor connecting the VOCM input of the THS4521 to the input common-mode drive from the PCM4204
is shown removed and is optional; no performance change was noted with it connected or removed. The
THS4521 is operated with a +5-V single-supply so the output common-mode defaults to +2.5 V as required at
the input of the PCM4204. The EVM power connections were modified by connecting positive supply inputs, +15
V, +5 VA and +5 VD, to a +5-V external power supply (EXT +3.3 was not used) and connecting –15 V and all
ground inputs to ground on the external power supply. Note only one external +5-V supply was needed to power
all devices on the EVM.
A SYS-2722 Audio Analyzer from Audio Precision (AP) provides an analog audio input to the EVM; the PCMformatted digital output is read by the digital input on the AP.
Data were taken using a 256-fS system clock to achieve fS = 48-kHz measurements, and audio output uses PCM
format. Other data rates and formats are expected to show similar performance in line with that shown in the
product data sheet.
Figure 82 shows the THD+N vs Frequency response with no weighting; Figure 83 shows an FFT of the output
with 1-kHz input tone. Input signals to the PCM4204 for these tests is 0.5 dBFS. Dynamic range is also tested at
–60 dBFS, fIN = 1 kHz, and A-weighted. Table 8 summarizes testing results using the THS4521 together with the
PCM4204 versus typical data sheet performance measurements, and show that it make an excellent drive
amplifier for this ADC.
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Typical Applications (continued)
The test circuit shown in Figure 79 has a gain = 0.27 and attenuates the input signal. For applications that
require higher gain, the circuit was modified to gains of G = 1, G = 2, and G = 5 by replacing the feedback
resistors (R33 and R34) and re-tested to show performance.
R33
270 W
TP4
GND
C21
1 nF
+
+5 V
C29
+15 V
10 mF
C73
100 pF
C41
0.01 mF
R23
1 kW
Audio
Inputs
R41
40.2 W
R13
0W
C79
2.7 nF
THS4521
R24
1 kW
C83
0.1 mF
R42
40.2 W
PCM4204
Inputs
R14
0W
C74
100 pF
GND
+15 V
R27
1 kW
+
C42
0.01 mF
C30
10 mF
C22
1 nF
R34
270 W
Figure 79. THS4521 and PCM4204 Test Circuit
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Typical Applications (continued)
Figure 84 shows the THS4521 and PCM4204 THD+N versus frequency with no weighting at higher gains.
9.2.1.1 Design Requirements
Table 8. 1-kHz AC Analysis: Test Circuit Versus PCM4204 Data Sheet Typical Specifications
(FS = 48 kSPS)
Configuration
Tone
THD+N
Dynamic Range
THS4521 and PCM4204
1 kHz
–106 dBc
117 dB
PCM4204 Data sheet (typ)
1 kHz
–105 dBc
118 dB
9.2.1.2 Detailed Design Procedure
Table 9. THS4521EVM Parts List
ITEM
DESCRIPTION
SMD SIZE
REFERENCE
DESIGNATOR
QTY
MANUFACTURER
PART NUMBER
1
Capacitor, 10.0 μF, ceramic, X5R, 6.3 V
0805
C7, C8, C9, C10
4
(AVX) 08056D106KAT2A
2
Capacitor, 0.1 μF, ceramic, X7R, 16 V
0603
C3, C5, C11, C12
4
(AVX) 0603YC104KAT2A
3
Capacitor, 0.22 μF, ceramic, X7R, 10 V
0603
C1, C4, C6
3
(AVX) 0603ZC224KAT2A
4
Open
0603
C2, C13, C14, C15, C16
5
5
Open
0603
R1, R2, R3, R7, R8, R9, R18,
R19, R21, R22, R23, R26
12
6
Resistor, 0 Ω
0603
R24, R25
2
(ROHM) MCR03EZPJ000
7
Resistor, 49.9 Ω, 1/10W, 1%
0603
R6
1
(ROHM) MCR03EZPFX49R9
8
Resistor, 52.3 Ω, 1/10W, 1%
0603
R10, R11, R20
3
(ROHM) MCR03EZPFX52R3
9
Resistor, 487 Ω, 1/10W, 1%
0603
R16, R17
2
(ROHM) MCR03EZPFX4870
10
Resistor, 1k Ω, 1/10W, 1%
0603
R12, R13, R14, R15
4
(ROHM) MCR03EZPFX1001
11
Resistor, 0 Ω
0805
R4, R5
2
(ROHM) MCR10EZPJ000
12
Open
T1
1
13
Transformer, RF
14
Jack, Banana receptance, 0.25-in dia.
hole
15
Open
16
Connector, edge, SMA PCB jack
17
Header, 0.1 in CTRS, 0.025-in sq. pins
18
Shunts
19
Test point, Red
20
Test point, Black
21
IC, THS4521
22
Standoff, 4-40 hex, 0.625 in length
23
24
T2
1
(MINI-CIRCUITS) ADT1-1WT
J4, J5, J8
3
(SPC) 813
J1, J3, J6, J7, J10, J11
6
J2, J9
2
(JOHNSON) 142-0701-801
JP1
1
(SULLINS) PBC36SAAN
JP1
1
(SULLINS) SSC02SYAN
TP1
1
(KEYSTONE) 5000
TP2, TP3
2
(KEYSTONE) 5001
U1
1
(TI) THS4521D
4
(KEYSTONE) 1808
Screw, Phillips, 4-40, .250 in
4
SHR-0440-016-SN
Board, printed circuit
1
(TI) EDGE# 6494532
2 POS.
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J4
VS-
VS-
C3
0.1mF
www.ti.com
C5
0.1mF
C7
10mF
C603
J5
GND
J8
VS+
C8
10mF
C9
10mF
C0805
VS+
C10
10mF
C11
0.1mF
VS+
C15
Open
C12
0.1mF
C0805
C13
Open
C14
Open
C603
TP2
C16
Open
TP3
VS-
J11
J1
JP1
C1
R6
0.22mF 49.9W
VS-
C4
0.22mF
J6
R14
1kW
R4
0W
R1
R10
52.3W
3 T1 4
R12
1kW
PW
R2
2
5
1
6
R5
0W
J2
C2
1
R7
6
4
R9
R20
52.3W
5
R13
1kW
8
VOUTVS+
CM
R21
5
2
R19
R17
487W
4
3
J9
R26
J10
R24
0W
J7
R15
1kW
R25
0W
R22
3
2
R11
52.3W
6 T2 1
R16
487W
VOUT+
7
R3
R23
R18
VS-
R8
TP1
C6
0.22mF
J3
Figure 80. THS4521EVM: Schematic
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9.2.1.2.1 Audio ADC Driver Performance: THS4521 and PCM3168 Combined Performance
The THS4521 is also tested as the drive amplifier for the PCM3168A ADC input. The PCM3168A is a highperformance, single-chip, 24-bit, 6-in/8-out, audio coder/decoder (codec) with single-ended and differential
selectable analog inputs and differential outputs. The six-channel, 24-bit ADC employs a ΔΣ modulator and
supports 8-kHz to 96-kHz sampling rates and a 16-bit/24-bit width digital audio output word on the audio
interface. The eight-channel, 24-bit digital-to-analog converter (DAC) employs a ΔΣ modulator and supports 8kHz to 192-kHz sampling rates and a 16-bit/24-bit width digital audio input word on the audio interface. Each
audio interface supports I2S™, left-/right-justified, and DSP formats with 16-bit/24-bit word width. In addition, the
PCM3168A supports the time-division-multiplexed (TDM) format.. The PCM3168A provides flexible serial port
interface and many other advanced features. Refer to the PCM3168A product data sheet for more information.
The PCM3168A EVM is used to test the audio performance of the THS4521 as a drive amplifier. The standard
PCM3168A EVM is provided with OPA2134 operational amplifiers that are used to convert single-ended inputs to
differential to drive the ADC. For testing, the operational amplifier output series resistors are removed from one of
the channels and a THS4521, mounted on its standard EVM, is connected to the ADC inputs via short coaxial
cables. The THS4521 EVM is configured for both differential inputs as shown in Figure 91 and for single-ended
input as shown in Figure 92 with 1-kΩ resistors for RF and RG, and 24.9-Ω resistors in series with each output to
isolate the outputs from the reactive load of the coaxial cables. To limit the noise from the external EVM and
cables, a 2.7-nF capacitor is placed differentially across the PCM3168A inputs. The THS4521 is operated with a
single-supply +5-V supply so the output common-mode of the THS4521 defaults to +2.5 V as required at the
input of the PCM3168A. The PCM3168A EVM is configured and operated as described in the PCM3168AEVM
User's Guide. The ADC was tested with an external THS4521 EVM with both single-ended input and differential
inputs. In both configurations, the results are the same. Figure 81 shows the THD+N versus frequency and
Table 10 compares the result to the PCM3168 data sheet typical specification at 1 kHz. Both graphs show that it
makes an excellent drive amplifier for this ADC. Note: a 2700 series Audio Analyzer from Audio Precision is
used to generate the input signals to the THS4521 and to analyze the digital data from the PCM3168.
THS4521 and PCM3168 THD+N vs FREQUENCY
(No Weighting)
-80
-82
-84
THD+N (dB)
-86
-88
-90
-92
-94
-96
-98
-100
10
100
1k
10 k 20 k
Frequency (Hz)
Figure 81. THS4521 and PCM3168: Thd+N Versus Frequency With No Weighting
Table 10. 1-kHz AC Analysis: Test Circuit vs PCM3168 Data Sheet Typical Specifications (FS = 48 kSPS)
Configuration
Tone
THD+N
THS4521 and PCM3168
1 kHz
–92.6 dBc
PCM3168A Data sheet (typ)
1 kHz
–93 dBc
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9.2.1.3 Application Curves
THS4521 and PCM4204
1-kHz FFT
THS4521 and PCM4204 THD+N
vs FREQUENCY (No Weighting)
-95
-97
-99
FFT (dBFS)
THD+N (dB)
-101
-103
-105
-107
-109
-111
-113
-115
0
100
1k
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
0
10 k 20 k
100
1k
10 k 20 k
Frequency (Hz)
Frequency (Hz)
Figure 83. THS4521 and PCM4204 1-kHz FFT
Figure 82. THS4521 and PCM4204: Thd+N Versus
Frequency With No Weighting
THS4521 and PCM4204 THD+N
vs FREQUENCY (No Weighting, at Higher Gains)
-95
-97
-99
G=5
THD+N (dB)
-101
-103
G=2
-105
G=1
-107
-109
-111
-113
-115
0
100
1k
10 k 20 k
Frequency (Hz)
Figure 84. THS4521 and PCM4204: Thd+N Versus Frequency With No Weighting at Higher Gains
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9.2.2 ADC Driver Performance: THS4521 and ADS1278 Combined Performance
The THS4521 provides excellent performance when driving high-performance ΔΣ and successive approximation
register (SAR) ADCs in audio and industrial applications using a single 3-V to 5-V power supply. To show
achievable performance, the THS4521 is tested as the drive amplifier for the ADS1278 24-bit ADC. The
ADS1278 offers excellent ac and DC performance, with four selectable operating
modes from 10 kSPS to 128 kSPS to enable the user to fine-tune performance and power for specific application
needs. The circuit shown in Figure 85 was used to test the performance. Data were taken using the HighResolution mode (52 kSPS) of the ADS1278 with input frequencies at 1 kHz and 10 kHz and signal levels 1/2 dB
below full-scale (–0.5 dBFS). FFT plots showing the spectral performance are given in Figure 87 and Figure 88;
tabulated ac analysis results are shown in Table 11 and compared to the ADS1278 data sheet typical
performance specifications.
1 kW
1.5 nF
5V
49.9 W
1 kW
AINN1
VIN+
THS4521
VIN-
49.9 W
2.2 nF
ADS1278 (CH 1)
AINP1
1 kW
VOCM
VCOM
x1
0.1 mF
1/2
OPA2350
0.1 mF
1.5 nF
1 kW
Figure 85. THS4521 and ADS1278 (Ch 1) Test Circuit
9.2.2.1 Design Requirements
Table 11. AC Analysis
Configuration
Tone
Signal (dBFS)
SNR (dBc)
THD (dBc)
SINAD (dBc)
SFDR (dBc)
THS4521 and
ADS1278
1 kHz
–0.5
109
–108
105
114
10 kHz
–0.5
102
–110
101
110
1 kHz
–0.5
110
–108
—
109
ADS1278 Data
sheet (typ)
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9.2.2.2 Detailed Design Procedure
9.2.2.2.1 ADC Driver Performance: THS4521 and ADS8321 Combined Performance
To demonstrate achievable performance, the THS4521 is tested as the drive amplifier for the ADS8321 16-bit
SAR ADC. The ADS8321 offers excellent ac and dc performance, with ultra-low power and small size. The circuit
shown in Figure 86 was used to test the performance.
Data were taken using the ADS8321 at 100 kSPS with input frequencies of 2 kHz and 10 kHz and signal levels
that were -0.5 dBFS. FFT plots that illustrate the spectral performance are given in Figure 89 and Figure 90.
Tabulated ac analysis results are listed in Table 12 and compared to the ADS8321 data sheet typical
performance. Note the significant improvement in SFD using the THS4521 driver over just the ADC by itself.
1 kW
5V
68 pF
49.9 W
1 kW
-IN
VIN+
THS4521
VIN-
1 nF
49.9 W
ADS8321
+IN
1 kW
VOCM
68 pF
Open
0.22 mF
1 kW
Figure 86. THS4521 and ADS8321 Test Circuit
Table 12. AC Analysis
Configuration
Tone
Signal (dBFS)
SNR (dBc)
THD (dBc)
SINAD (dBc)
SFDR (dBc)
THS4521 and
ADS8321
2 kHz
–0.5
86.7
–97.8
86.4
100.7
10 kHz
–0.5
85.2
–98.1
85.2
102.2
10 kHz
–0.5
87
–86
84
86
ADS8321 Data
sheet (typ)
48
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THS4521, THS4522, THS4524
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SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
9.2.2.3 Application Curves
The application curves below apply to the ADS14278 test.
10-kHz FFT
1-kHz FFT
0
G=1
RF = RG = 1 kW
CF = 1.5 nF
VS = 5 V
Load = 2 x 49.9 W + 2.2 nF
Magnitude (dBFS)
-20
-40
-60
-80
-100
G=1
RF = RG = 1 kW
CF = 1.5 nF
VS = 5 V
Load = 2 x 49.9 W + 2.2 nF
-20
Magnitude (dBFS)
0
-40
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
4
8
12
16
20
0
24 26
4
8
16
12
20
24 26
Frequency (kHz)
Frequency (kHz)
Figure 88. 10-kHz FFT
Figure 87. 1-kHz FFT
The application curves below apply to the ADS8321 test.
10-kHz FFT
10-kHz FFT
G=1
RF = RG = 1 kW
CF = 1.5 nF
VS = 5 V
Load = 2 x 49.9 W + 2.2 nF
Magnitude (dBFS)
-20
-40
-60
-80
-100
0
-40
-60
-80
-100
-120
-120
-140
-140
-160
VS = 5.0 V
G = 1 V/V
RF = RG = 1 kW
Load = 2 x 49.9 W + 2 pF
-20
Magnitude (dBFS)
0
-160
0
4
8
12
16
20
24 26
0
10 k
Frequency (kHz)
Figure 89. 2-kHZ FFT
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: THS4521 THS4522 THS4524
20 k
30 k
40 k
50 k
Frequency (Hz)
Figure 90. 10-kHz FFT
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THS4521, THS4522, THS4524
SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
www.ti.com
9.2.3 Differential Input to Differential Output Amplifier
The THS4521, THS4522, and THS4524 family are fully-differential operational amplifiers that can be used to
amplify differential input signals to differential output signals. Figure 91 shows a basic block diagram of the circuit
(VOCM and PD inputs not shown). The gain of the circuit is set by RF divided by RG.
RF
VS+
Differential
Input
Differential
Output
RG
VOUT-
VIN+
THS452x
VIN-
VOUT+
RG
VSRF
Figure 91. Differential Input to Differential Output Amplifier
9.2.4 Single-Ended Input to Differential Output Amplifier
The THS4521, THS4522, and THS4524 family can also amplify and convert single-ended input signals to
differential output signals. Figure 92 illustrates a basic block diagram of the circuit (VOCM and PD inputs not
shown). The gain of the circuit is again set by RF divided by RG.
Single-Ended
Input
RF
RG
VS+
Differential
Output
VOUT-
RG
THS452x
VOUT+
VS-
RF
Figure 92. Single-Ended Input to Differential Output Amplifier
50
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THS4521, THS4522, THS4524
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SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
10 Power Supply Recommendations
The THS452x family is principally intended to operate with a nominal single-supply voltage of +3 V to +5 V.
Supply-voltage tolerances are supported with the specified operating range of 2.5 V (10% low on a 3-V nominal
supply) and 5.5 V (8% high on a 5-V nominal supply). Supply decoupling is required, as described in the
Application and Implementation. Split (or bipolar) supplies can be used with the THS452x family, as long as the
total value across the device remains less than 5.5 V (absolute maximum).
Using a negative supply to deliver a true swing to ground output in driving SAR ADCs may be desired. While the
THS452x family quotes a rail-to-rail output, linear operation requires approximately a 200-mV headroom to the
supply rails. One easy option for extending the linear output swing to ground is to provide the small negative
supply voltage required using the LM7705 fixed –230-mV, negative-supply generator. This low-cost, fixed
negative-supply generator accepts the 3- to 5-V positive supply input used by the THS452x and provides a –230mV supply for the negative rail. Using the LM7705 provides an effective solution, as shown in the TI Designs
TIDU187, Extending Rail-to-Rail Output Range for Fully Differential Amplifiers to Include True Zero Volts.
11 Layout
11.1 Layout Guidelines
Figure 80 shows the THS4521EVM schematic. PCB layers 1 through 4 are shown in Figure 93; Table 9 lists the
bill of materials for the THS4521EVM as supplied from TI. It is recommended to follow the layout of the external
components near to the amplifier, ground plane construction, and power routing as closely as possible. Follow
these general guidelines:
• Signal routing should be direct and as short as possible into and out of the amplifier circuit.
• The feedback path should be short and direct.
• Ground or power planes should be removed from directly under the amplifier input and output pins.
• An output resistor is recommended in each output lead, placed as near to the output pins as possible.
• Two 0.1-μF power-supply decoupling capacitors should be placed as near to the power-supply pins as
possible.
• Two 10-μF power-supply decoupling capacitors should be placed within 1 inch of the device and can be
shared among multiple analog devices.
• A 0.22-μF capacitor should be placed between the VOCM input pin and ground near to the pin. This capacitor
limits noise coupled into the pin.
• The PD pin uses TTL logic levels; a bypass capacitor is not necessary if actively driven, but can be used for
robustness in noisy environments whether driven or not.
• If input termination resistors R10 and R11 are used, a single point connection to ground on L2 is
recommended.
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: THS4521 THS4522 THS4524
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SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
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11.2 Layout Example
Figure 93. THS4521EVM: Layer 1 to Layer 4 Images
52
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THS4521, THS4522, THS4524
www.ti.com
SBOS458H – DECEMBER 2008 – REVISED JUNE 2015
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Related Links
Table 13 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 13. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
THS4521
Click here
Click here
Click here
Click here
Click here
THS4522
Click here
Click here
Click here
Click here
Click here
THS4524
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
I2S is a trademark of NXP Semiconductor.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: THS4521 THS4522 THS4524
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53
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jun-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THS4521ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TH4521
THS4521IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
4521
THS4521IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
4521
THS4521IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TH4521
THS4522IPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
THS4522
THS4522IPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
THS4522
THS4524IDBT
ACTIVE
TSSOP
DBT
38
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
THS4524
THS4524IDBTR
ACTIVE
TSSOP
DBT
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
THS4524
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
5-Jun-2015
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS4521, THS4524 :
• Enhanced Product: THS4524-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
THS4521IDGKR
VSSOP
DGK
8
THS4521IDGKT
VSSOP
DGK
THS4521IDR
SOIC
D
THS4522IPWR
TSSOP
PW
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS4521IDGKR
VSSOP
DGK
8
2500
367.0
367.0
35.0
THS4521IDGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
THS4521IDR
SOIC
D
8
2500
367.0
367.0
35.0
THS4522IPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
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