Download Class 4 Bitwise logic and Immediate operands

Class 4
Bitwise Logic and Immediate Operands





Bitwise operations
Assembly bitwise instructions (ori, andi, xori)
Zero Extension
Immediate operand
Bitwise operations usage (masking, inversion, setup, comparison)
Textbook: Appendix A – A.10. MIPS R2000 assembly language.
Central Connecticut State University, MIPS Tutorial. Chapter 11.
Basic MIPS operations we are going to learn are arithmetic, logic, memory access and control
branches. This chapter presents the bitwise operations with immediate operands.
Bitwise Operation
With a bitwise logic operation two bit patterns are "lined up" and then a logic operation
(such as OR or AND) is performed between pairs of bits.
OR Operation on Bits
first operand
0
0
1
1
second operand
0
1
0
1
__
__
__
__
0
1
1
1
result
3 decimal
5 decimal
7 decimal
Here is the bitwise OR between two 8-bit patterns.
A bitwise operation is where a logical operation is performed on the bits
of each column of the operands.
0110 1100
0101 0110
-----------0111 1110
operand
operand
result
1
Zero Extension of decimal numbers
When doing operations with decimal numbers everyday we do zero extension of that
numbers intuitively if they have different amount of digits.
This is what we
write usually
1
+
125
------126
Zero Extension or
Padding with Zeros
on the left
This is what we
do really
001
+
125
------126
Zero Extension or padding with zeros with binary numbers
Suppose we have this 16 bit number as a first operand
0000 0000 0000 0010
And this 32 bit number as a second operand 0000 0000 0000 0000 0000 0000 0000 0000
We want to perform OR operation between 2 operands.
 First we should do zero extension of the first operand
 Then perform the operation with the full length of both operands.
zero extended part
---- ---- ---- ---0000 0000 0000 0000 0000 0000 0000 0010
0000 0000 0000 0000 0000 0000 0000 0000
--------------------------------------0000 0000 0000 0000 0000 0000 0000 0010
-- zero extended 1st operand
-- 2nd operand
-- result
2
What is immediate operand ?
A machine instruction can use some of its bits as one of the operands for a machine
operation. This is called an immediate operand.
Using this kind of operations the program can set up the registers with the desirable
known values.
add $10,$8,$9
addi $10,$8,0x2
0x2 goes to ALU from
the instruction body
ALU gets both
operands from the
Registers
ALU gets one operand
from Register $8
(The assembly language instruction can just say "0x2"). The machine instruction tells the ALU to
perform a bitwise OR between the contents of register $0 and the immediate operand 0x0002.
The result is put in register $8.
Immediate operand example. Here is one of the instructions from the previous sample program:
address
——————————
0x00400000
machine code
——————————
0x34080002
assembly code
—————————————
ori $8,$0,0x2
The last 16 bits (4 nibbles) of the machine instruction contain the immediate operand 0x0002.
3
OR Immediate Instruction
OR Immediate used with Non-zero Operands
ori
d,s,const
# register d <-- bitwise OR of const
# with the contents of register $s (source)
const represents a positive integer 0 <= const <= 65535 (0xFFFF -16 bits).
The three operands of the assembly instruction d, $s, and const must appear in that order.
:
OR Immediate used with Zero Register
ori
d,$0,const
# register d <-- const.
(d – destination)
const represents a positive integer 0 <= const <= 65535 (0xFFFF -16 bits) .
The three operands of the assembly instruction d, $0, and const must appear in that order.
Because the OR operation was done with the zeros in register $0, the result was a copy of the
zero-extended immediate operand. Copying a bit pattern into a register is usually called loading
the register. Register $8 was loaded with a 32-bit pattern. The pattern could represent a positive
two. If so, register $8 was loaded with positive two. Here is a description of the ori instruction
when used to load a register
Sixteen bits of immediate operand, are to be bitwise ORed with the thirty-two bits of register zero.
MIPS zero extends the sixteen-bit operand so the operands are the same length. Sometimes
this is called padding with zeros on the left.
Zero Extension or padding with zeros
Sixteen bits of immediate operand
0000 0000 0000 0010
thirty-two bits of register zero
0000 0000 0000 0000 0000 0000 0000 0000
zero extension
---- ---- ---- ---0000 0000 0000 0000 0000 0000 0000 0010
0000 0000 0000 0000 0000 0000 0000 0000
--------------------------------------0000 0000 0000 0000 0000 0000 0000 0010
-- zero extended immediate operand
-- data in register $0
-- result, put in register $8
An OR operation is done in each column. The 32-bit result is placed in register $8.
4
The three operands of the instruction must appear in the correct order, and const must be within
the specified range.
If the immediate operand in a source instruction is less than sixteen bits (such as 0x2) the
assembler expands it to sixteen. If it is more than sixteen bits the assembler writes an error
message.
The const part of the assembly language instruction can be a positive decimal or a hexadecimal
constant. The assembler translates the constant into a 16-bit pattern in the machine instruction.
The following two assembly language instructions translate into the same machine
language instruction:
ori
ori
$5,$4,0x10
$5,$4,16
Below is an incorrect loading instruction example:
ori
$0,$9,0x32
It says to put the result into register $0 (which is always zero and can't be loaded with anything
else).
The assembler part of the SPIM simulator does not write an error message for the above
mistaken instruction. But the instruction does not change register zero when executed.
ORI Example
Here is a tiny program that bitwise ORs two patterns. First one pattern is loaded into
register $8, then the register is ORed with an immediate operand. The result goes into
register $10.
## Program to bitwise OR two patterns
.text
.globl main
main:
ori
ori
$8,$0,0x0FA5
$10,$8,0x368F
# put first pattern into register $8
# or ($8)with second pattern.Result to $10.
## End of file
Below is what did the program with our two operands:
0000 1111 1010 0101
0FA5
0011 0110 1000 1111
368F
---- ---- ---- ----
----
0011 1111 1010 1111
3FAF
5
To run the program:
1.
2.
3.
4.
Create a source file.
Start SPIM.
Load the source file.
Set simulator switches (only the following matter at this time):
o ON --- general registers in hexadecimal.
o ON --- bare machine.
o OFF --- allow pseudo instructions.
o OFF --- load trap file.
5. Initialize the PC to the first instruction address.
6. Push F10 once per instruction.
The picture shows the result of running the program. The result in $10 is what was expected. The
source code is at the right of each line in the code window (not seen in the cropped window of the
picture). The version of the code in the middle column gives the bit patterns in decimal.
ORI Machine Code
Below is the machine code for the instruction. In the third line the bits have been grouped
according to their functional meaning. Documentation for the MIPS shows this grouping for each
instruction. It is not something you can determine by inspection.
Look this over to get an idea of how it works. The left six bits of the instruction are the opcode,
the bit pattern that specifies the machine operation. The next group of five bits specifies the
6
operand register. The group of five after that specifies the destination register. The remaining bits
are the immediate operand.
ORI Machine Code
3
4
0
8
0
f
a
5
-- machine instruction in hex
0011 0100 0000 1000 0000 1111 1010 0101
-- machine instruction in bits
001101
00000 01000 0000 1111 1010 0101
-- fields of the instruction
ori
opcode
$0
operand
reg.
ori
$8,
$8
dest
reg.
$0,
0
f
a
5
immediate operand
-- meaning of the fields
0x0fa5
-- assembly language instruction
(Notice that the register numbers
are not in the same order as they
are in the machine instruction).
Machine Instructions Compared (addu, ori)
Here again is the ori machine instruction:
3
001101
opcode
4
0
8
0
f
a
5
00000 01000 0000 1111 1010 0101
oper dest immediate operand
-and reg.
reg.
ori
$0
$8
0
f
a
-- machine instruction in hex
-- fields of the instruction
-- meaning of the fields
5
The layout of this machine instruction is different from the addu instruction we looked at:
0
1
0
9
5
0
2
1
000000 01000 01001 01010 00000 100001
opcode oprnd oprnd dest ----- 2ndary
ALUop
$8
$9
$10
-- machine instruction in hex
-- fields of the instruction
-- meaning of the fields
addu
Both instructions are 32 bits wide (as are all MIPS R2000/R3000 instructions). The first six bits are the
opcode, which calls for an ALU operation. The addu instruction further specifies the operation in the last six
bits, the secondary opcode. The addu instruction does not have an immediate operand.
The first six bits of the instruction (the opcode) specify the machine operation. (Sometimes a secondary
opcode is needed). The opcode also determines how the rest of the instruction is laid out. A human needs to
look at documentation to figure out the bit fields of an instruction and what they mean. The MIPS processor
does this automatically.
7
AND Immediate Instruction
The andi instruction does a bitwise AND of two 32-bit patterns. At run time the 16-bit immediate
operand is padded on the left with zero bits to make it a 32-bit operand.
andi d,s,const
# register d <-- bitwise AND of immediate operand const
#
and the contents of register $s.
#
const is a 16-bit pattern, so
#
0x0000 ... const ... 0xFFFF
Simple AND Rules
AND Operation on Bits
0
0
1
1
1. AND the Register with 0s sets the Register value to 0s.
second operand 0
1
0
1
2. AND the Register with the pattern (mask) 0s and 1s
first operand
result
__ __ __ __
selects the original Register’s bits by mask of 1s. The
original values are not changed only where the mask bits
0
are 1s. The other bits are set to 0s.
0
0
1
The three operands of the instruction must appear in the correct order, and const must be within
the specified range. The immediate operand in the source instruction always specifies sixteen bits
although the zeros on the left can be omitted (such as 0x2).
Exclusive Or Immediate (XOR)
An exclusive OR is nearly the same as the more common OR (the inclusive OR) except that the
result is zero when both operands are one.
Simple XOR Rules
XOR Operation on Bits
first operand
0
0
1
1
second operand 0
1
0
1
__ __ __ __
result
0
1
1
0
4. XOR the Register with itself sets the Register value to
0s.
5. XOR the Register with 1s inverts the original Register’s
content.
6. XOR compares 2 operand and sets 1s in result bits where
the operands are different.
Here is a description of the assembly language instruction. The machine language for the
instruction looks much the same as the ori and the andi instruction.
xori d,s,const
# register d <-- bitwise XOR of immediate operand const
#
and the contents of register $s.
#
const is a 16-bit pattern, so
#
0x0000 ... const ... 0xFFFF
8
The three operands of the instruction must appear in the correct order, and const must be within
the specified range. If the immediate operand in a source instruction is less than sixteen bits
(such as 0x2) the assembler expands it to sixteen. If it is more than sixteen bits the assembler
writes an error message.
Example Program
Here is a program that does all three bitwise operations between the same two patterns. The
register is different in each case.
## Program to bitwise OR, AND, and XOR two patterns
.text
.globl main
main:
ori
ori
andi
xori
$15, $0,0x0FA5
$8,$15,0x368F
$9,$15,0x368F
$10,$15,0x368F
#
#
#
#
put bit pattern into register $15
OR with second pattern
AND with second pattern
XOR with second pattern
## End of file
Running it in SPIM (pushing F10 four times) results in the following:
9