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Isolated IGBT Gate Driver Evaluation Platform for 3-Phase
Inverter System
TI Designs
Design Features
This reference design consists of a 22-kW power
stage with TI’s new reinforced isolated IGBT gate
driver ISO5852S intended for 3-phase inverters in
various applications like AC drives. This design allows
performance evaluation of the ISO5852S in a 3-phase
inverter incorporating 1200-V rated IGBT modules of
current ratings ranging from 50 to 200 A.
a
Some of the important functionality and performance
evaluated are short circuit protection using DESAT
detection, soft-shutdown, effectiveness of the Active
Miller Clamp at different inverter dv/dt, ESD, and EFT
performance of the IGBT gate driver at system level
derived from adjustable speed electrical power drive
systems (IEC61800-3). Piccolo LaunchPad
LAUNCHXL-F28027 generates the PWM signals
required for controlling the inverter.
•
•
•
•
Design Resources
Design Folder
TIDA-00195
ISO5852S
AMC1200
SN6501
UCC27211
CSD88537ND
TPS54286
LP38691
SN74ALVC125
Product Folder
Product Folder
Product Folder
Product Folder
Product Folder
Product Folder
Product Folder
Product Folder
•
•
3-Phase Inverter System With
– 1200-V Rated IGBT Module of Current Ratings
From 50 to 200 A (Supporting Multiple Vendors)
– Seven Reinforced Isolated IGBT Gate Drivers:
ISO5852S With Working Voltage Isolation of
1.5 kVRMS With Minimum CMTI of 50 kV/μs
Incorporates Protection Against Overcurrent and
False Turn ON Using
– DESAT Detection
– Soft Shutdown
– Active Miller Clamp
Meets IEC61800-3 EMC Immunity Requirements:
– ±8-kV ESD CD per IEC 61000-4-2
– ±4-kV EFT per IEC 61000-4-4
Onboard Half-bridge Isolated Power Supply
Generating 16 V/–8 Vfor Gate Drivers With
Provision to Operate Gate Drivers With Unipolar or
Bipolar Supply With External BJT/MOSFET Buffers
Can Configure Gate Driver Input for Inverting or
Non-Inverting Operation
Option to Evaluate the System With
– Twisted Pair Cable Between the Gate Driver
and IGBT
– External Capacitance Between Gate and
Emitter
Featured Applications
ASK Our E2E Experts
WEBENCH® Calculator Tools
•
•
•
•
Industrial Variable Speed Drives
Servo Drives
Solar Inverters
UPS
+24-V DC
VDC_PLUS
C2000 LaunchPAD interface
SMPS
PWMs
HALF
BRIDGE
SMPS
IGBT power
module
+16 V
-8 V
+16 V
-8 V
Inverter PWM signals
Reinforced
isolated
IGBT gate
driver ±
ISO5852S
Inverter
output
Gate
drive
signals
VDC_MINUS
DC bus sensing
NTC output
IGBT brake
TIDUA15A – June 2015 – Revised August 2015
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Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System
Copyright © 2015, Texas Instruments Incorporated
1
Introduction to IGBT Gate Drivers
www.ti.com
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.
1
Introduction to IGBT Gate Drivers
Insulated gate bipolar transistors (IGBTs) are considerably used in 3-phase inverters that have numerous
applications like variable-frequency drives that control the speed of AC motors, uninterruptible power
supply, solar inverters, and other similar inverter applications.
IGBTs have the advantages of high input impedance as the gate is insulated, has a rapid response ability,
good thermal stability, simple driving circuit, good ability to withstand high voltage, snubber-less operation,
and controllability of switching behavior providing reliable short-circuit protection. The IGBT is a voltagecontrolled device, which gives it the ability to turn ON/OFF very quickly.
A typical application of a three-phase inverter using six isolated gate drivers is shown in Figure 1. Note
that each phase uses a high-side and a low-side IGBT switch to apply positive and negative high-voltage
DC pulses to the motor coils in an alternating mode.
The output voltage to the motor is controlled by pulse-width modulation (PWM). PWM is accomplished by
turning the transistor on and off several times. The output voltage is an average of the peak or maximum
voltage and the amount of time the transistor is turned on or off.
VBUS
VBUS
From
Controller
ISOLATION
From
Controller
+16 V
ISOLATION
From
Controller
+16 V
ISOLATION
+16 V
VBUS
±8V
±8V
±8V
+16 V
+16 V
+16 V
From
Controller
ISOLATION
From
Controller
ISOLATION
ISOLATION
+5 V
From
Controller
+
+
TI
'DYH¶V
Control
Center
+5 V
To ADC or Controller
±8V
±8V
VGND
±8V
VGND
VGND
Figure 1. 3-Phase Inverter With Isolated Gate Drive
The ISO5852S is a reinforced isolated IGBT gate driver from TI intended for use in applications such as
motor control, industrial inverters, switched-mode power supplies, and so on. In these applications,
sophisticated PWM control signals are required to turn the power-devices on and off, which at the system
level eventually may determine, for example, the speed, position, and torque of the motor or the output
voltage, frequency, and phase of the inverter. These control signals are usually the outputs of a
microcontroller (MCU), and are at low-voltage levels such as 3.3 or 5.0 V. The gate controls required by
the IGBTs, on the other hand, are in the range of 15 to 20 V, and need high current capability to be able
to drive the large capacitive loads offered by those power transistors. Also, the gate drive needs to be
applied with reference to the emitter of the IGBT and by inverter construction, the emitter node of top
IGBT swings between 0 to the DC bus voltage, which is several hundreds of volts in magnitude. As the
IGBT can float with respect to ground at the power stage, both the power supply and the gate circuitry
should be isolated from the inverter ground. This gives room to a limited number of gate-driver
configurations:
• Gate drivers with potential separation
• Gate drivers without potential separation
2
Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System
Copyright © 2015, Texas Instruments Incorporated
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Introduction to IGBT Gate Drivers
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The ISO5852S belongs to a family of gate drivers with potential separation and can level shift the
incoming 3.3-V and 5.0-V control signals from the microcontroller to the 15-V to 20-V drive required by
IGBT while ensuring high-voltage isolation between the driver side and the MCU side.
This reference design consists of a 22-kW power stage with TI’s reinforced isolated gate drivers
ISO5852S intended to drive AC induction motor used in various industrial applications. This reference
design demonstrates the following functionality and performance of ISO5852S IGBT gate driver in the real
system:
• Unipolar and bipolar IGBT gate driver supply operation
• Undervoltage shutdown
• Interface with external BJT based current buffers
• DESAT detection
• Miller clamp
• Soft turn OFF
• Propagation delay
• ESD and EFT immunity performance of IGBT gate driver at system level
IGBT power module has been chosen such that its footprint fits multiple devices so as to perform gate
driver validation on IGBTs from different manufacturers. The footprint supports:
• Fuji Electric: 6MBL150VX-120-50, 6MBL100VX-120-50
• Mitsubishi: CM150TX-24S1
• Infineon: FS50R12KT4, FS200R12KT4R, FS100R17N3E4
The C2000 Piccolo LaunchPad evaluation kit, based on the F28027 MCU is been used to control the
inverter.
The power stage includes protection against IGBT overcurrent, over temperature of power module, and
DC bus sensing for protection against overvoltage.
TIDUA15A – June 2015 – Revised August 2015
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3
Key System Specifications
2
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Key System Specifications
Table 1. Key System Specifications of Power Stage
PARAMETER
DC link input voltage
Control voltage
IGBT power module
Maximum input DC current
Rated power capacity
Inverter switching frequency
Isolation
Operating ambient temperature
Inverter efficiency
Controller
Motor
Provision for resistive braking
Power supply specification for MCU
24-V DC
1200 V/50 to 150 A
50 A with 200 CFM Airflow
22 kW
16 kHz (Default); adjustable through software
Reinforced (IEC61800-5)
–25°C to 65°C
≥ 97% (Theoretical) at rated load
TMS320F28027
3-phase 400-V Induction motor
Yes
3.3 V ±5%
Feedbacks
DC bus voltage, IGBT temperature
Protections
Short circuit, over temperature, DC bus under- or overvoltage
ESD (IEC61000-4-2)
±8-kV Contact discharge
EFT (IEC61000-4-4)
±4-kV on motor cables (shielded and unshielded)
PCB
4
SPECIFICATION
400 to 1100 V
370 × 240 mm / 4 Layer, 2Oz copper
Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System
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System Description
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3
System Description
The system consists of
• IGBT power module: hex bridge IGBTs to provide three phases output for variable-frequency drives to
control the speed of AC motors (up to 22 kW). The PCB footprint supports mounting of different current
rated modules from different manufactures
• ISO5852S reinforced isolated gate driver capable of sourcing a 2.5-A and 5-A sink current is used to
drive the IGBTs. Half-bridge converter powered from 24-V with isolated 16-V/-8-V rails are used to
power gate drivers. The half-bridge transformer has been designed to meet safety requirements as
described in IEC61800-5
• Isolated amplifiers for measuring DC link voltage
• C2000 LaunchPad for controlling the inverter. This design uses F28027 InstaSPIN™ FOC-enabled
MCU. The sinusoidal voltage waveform applied to the motor is created by using the Space Vector
modulation technique implemented in the F28027 MCU
• Buck converters for powering control electronics, operated from a 24-V supply and generates multiple
voltage rails like 15 V and 5 V. An LDO is used to generate 3.3 V from a 5-V supply for powering the
C2000 LaunchPad
• Local DC link capacitor of ~220 μF. Relay is used to bypass NTC after power up
• Discrete brake IGBT for braking during regeneration
• Provision to measure the power module temperature using NTC
• Provision for operating the FAN
PCB is designed to fulfill the requirements of IEC61800-5. Figure 2 depicts the block diagram of the
power stage.
4
Block Diagram
+24-V DC
+800-V DC
C2000 LaunchPAD interface
SMPS
PWMs
HALF
BRIDGE
SMPS
IGBT power
module
+16 V
-8 V
+16 V
-8 V
Reinforced
isolated
IGBT gate
driver ±
ISO5852S
3N ACIM
Gate
drive
signals
Inverter PWM signals
DC bus sensing
NTC output
Figure 2. Power Stage Block Diagram
TIDUA15A – June 2015 – Revised August 2015
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5
Highlighted Products
5
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Highlighted Products
Key features of the highlighted devices can be taken from product datasheets. The following are the
highlighted products used in the reference design.
5.1
ISO5852S
The ISO5852S is a 5.7 kVRMS, reinforced isolated, IGBT gate driver with split outputs, OUTH and OUTL,
providing 2.5-A source and 5-A sink currents. The primary side operates from a single 3-V or 5-V supply.
The output side allows for a supply range from minimum 15 V to maximum 30 V. An internal DESAT
detection recognizes when the IGBT is in an overload condition. Upon a DESAT detect, a Mute logic
immediately blocks the output of the isolator and initiates a soft-turn-off procedure, which disables OUTH
and reduces the voltage at OUTL over a minimum time span of 2 μs. When OUTL reaches 2 V with
respect to the most negative supply potential, VEE2, the output is hard-clamped to VEE2.
During normal operation with bipolar output supply the output is hard clamp to VEE2 when the IGBT is
turned OFF. If the output supply is unipolar, an active miller clamp connects the output to VEE2.
5.2
CSD88537
The CSD88537 is a 60-V, dual N Channel, SO-8 NexFET™ power MOSFET with very low Drain-toSource ON resistance of 12.5 mΩ. FET is capable of handling continuous current of 8 A. CSD88537 is
designed to serve in half-bridge power supplies and motor control applications to generate gate driver
supplies.
5.3
UCC27211
The UCC27211 is a MOSFET driver delivering peak source and sink current of up to 4 A. The inputs are
independent of the supply voltage and have a maximum rating of 20 V. The floating high-side driver can
operate with supply voltages of up to 120 V. The high-side driver is referred to the switch node (HS),
which is typically the source pin of the high-side MOSFET and drain pin of the low-side MOSFET. The
low-side driver is referenced to VSS, which is typically ground. Features of the UCC27211 include input
stages UVLO protection, level shift, and built-in boot diode.
5.4
Piccolo LaunchPad
The C2000 LaunchPad is based around the C2000 Piccolo TMS320F28027 MCU, which features a 60MIPS processing core, 64-KB integrated flash, 8 PWM channels with high resolution capability, 12-bit 4.6MSPS ADC, capture interface, serial connectivity, and more. It is used to generate the PWM signals for
the 3-phase inverter.
5.5
TPS54286
The TPS54286 is a dual output non-synchronous buck converter capable of supporting 2-A output
applications that operate from a 4.5-V to 28-V input supply voltage, and provides output voltages between
0.8 V and 90% of the input voltage. The outputs can be enabled independently, or it can be configured to
allow either ratio metric or sequential startup.
With an internally-determined operating frequency, soft start time, and control loop compensation, this
converter provides many features with a minimum of external components. Other features include pulseby-pulse overcurrent protection and thermal shutdown protection at 148ºC.
6
Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System
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Highlighted Products
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5.6
AMC1200
The AMC1200 is a precision isolation amplifier with an output separated from the input circuitry by a
silicon dioxide (SiO2) barrier that is highly resistant to magnetic interference. This barrier has been certified
to provide galvanic isolation of up to 4000 VPEAK according to UL1577 and IEC60747-5-2. The input of the
AMC1200 is optimized for direct connection to shunt resistors with a voltage range of ±250 mV. The
device has low offset error of 1.5 mV max, BW of 60 KHz and CMMR of 108 dB. The AMC1200 has a
working voltage rating of 1200 VPEAK.
The MC1200 is fully specified over the extended industrial temperature range of –40°C to 105°C and are
available in a wide-body SOIC-8 package (DWV) and a gullwing 8 package (DUB).
5.7
SN6501
The SN6501 is a monolithic oscillator/power-driver, specifically designed for small form factor, isolated
power supplies in isolated interface applications. The device drives a low-profile, center-tapped
transformer primary from a 3.3-V or 5-V DC power supply. The secondary can be wound to provide any
isolated voltage based on transformer turns ratio. The SN6501 consists of an oscillator followed by a gate
drive circuit that provides the complementary output signals to drive the ground referenced N channel
power switches. The internal logic ensures break-before-make action between the two switches. The
SN6501 is available in a small SOT-23 (5) package, and is specified for operation at temperatures from
–40°C to 125°C.
TIDUA15A – June 2015 – Revised August 2015
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System Design Theory
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6
System Design Theory
6.1
Main Power Input
The main power input section is shown in Figure 3. D1 is the reverse polarity protection diode and has
reverse breakdown voltage of 1600 V. The input bulk aluminum electrolytic capacitors C3, C6, and C7
serve as local reservoirs for the IGBT module. These capacitors are rated to carry ripple current of 7.7 A.
The rest of ripple current is expected to be sourced from external capacitors. In addition to the bulk
aluminum capacitor, a polyester capacitor is used across the DC bus to suppress high frequency noises.
The startup current through the bulk capacitor is limited using thermistor, and the thermistor is bypassed
after one second using a relay.
D1
CN1
1
Terminal bush
A
C
RHRG75120
R208
200K
C3
680µF
R209
200K
R212
200K
C7
680µF
R213
200K
C154
FILM CAP
0.22µF
R210
200K
C6
680µF
R211
200K
PGND
4
1
INRUSH_BYPASS
t°
RL1
5
6
HE1aN-P-DC24V-Y5
+24V
R103
RT1
100R_PTC
B59109J0130A020
CN2
1
C
10R
D22
SK310A-LTP
A
C131
10µF
C
DNP
R104
PGND
Q5
PZT2222A
B
470R
E
BYPASS_RELAY
DGND
Figure 3. Main Power Input
8
Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System
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6.2
Inverter Stage
The IGBT-based 3-phase hex bridge inverter is shown in Figure 4. The decoupling capacitor (C154)
should be placed near to DC bus entry of inverter for better filtering. An improper layout or position of the
decoupling capacitors can cause undesired switching voltage spikes. IGBT (Q1) and free-wheeling diode
(D2) is added externally to the hex bridge IGBT module for braking.
The brake IGBT (APT70GR120L) is rated for 70 A (at TC = 110°C) current rating and 1200 V.
When DC bus voltage increases above the pre-defined value (this reference design uses a 1-kV
threshold) brake operation is enabled through controller and the excessive energy will be dissipated
through the resistive bank. The resistor bank is connected across the terminal blocks CN11 and CN12.
The rating of external brake resistor is selected on the basis of the VFD rating, braking duty cycle, and
magnitude of the energy to be dissipated.
IGBT Module
U1
FS200R12KT4R
30
31
CN11
1 DC_POS
C
Terminal bush
16
D2
RHRG75120
CN12
17
MOT_R_PHASE1
DC_VOLT_POS2
MOT_R_PHASE2
DC_VOLT_POS3
MOT_R_PHASE3
27
MOTOR_R_PHASE
28
29
DC_VOLT_POS4
DC_VOLT_POS5
A
C154
FILM CAP
0.22 µF
32
DC_VOLT_POS1
1 BRAKE
18
DC_VOLT_POS6
MOT_Y_PHASE3
C
GATE_BRAKE
Q1
G
APT70GR120L
33
E
34
35
15
14
13
MOT_Y_PHASE2
DC_VOLT_NEG1
MOT_Y_PHASE1
1
GATE_R_TOP_RTN
2
GATE_Y_TOP
5
GATE_Y_TOP_RTN
6
GATE_B_TOP
GATE_B_TOP_RTN
9
10
GATE_R_BOTTOM
3
GATE_R_BOT_RTN
4
GATE_Y_BOTTOM
7
GATE_Y_BOT_RTN
8
GATE_B_BOTTOM
11
GATE_B_BOT_RTN
12
MOTOR_Y_PHASE
25
24
DC_VOLT_NEG2
DC_VOLT_NEG3
DC_VOLT_NEG6
DC_VOLT_NEG5
MOT_B_PHASE1
DC_VOLT_NEG4
MOT_B_PHASE2
MOT_B_PHASE3
GATE_R_TOP
26
21
MOTOR_B_PHASE
22
23
GATE_R_TOP
GATE_R_TOP_RTN
GATE_Y_TOP
NTC_1
NTC_2
19
NTC_1
20
NTC_2
GATE_Y_TOP_RTN
GATE_B_TOP
DGND
GATE_B_TOP_RTN
GATE_R_BOTTOM
GATE_R_BOT_RTN
GATE_Y_BOTTOM
GATE_Y_BOT_RTN
GATE_B_BOTTOM
GATE_B_BOT_RTN
IC_FS200R12KT4R
Figure 4. 3-Phase Inverter of Power Stage
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System Design Theory
6.2.1
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IGBT module
This reference design is intended to support various makes of IGBT modules like Infineon, Fuji &
Mitsubishi, and so on. The power stage is designed to deliver up to 22-kW power. The power stage was
supplied with 800-V DC replicating high DC bus voltage during regeneration. Considering the safety factor
and switching spikes, IGBTs were selected with the voltage rating greater than or equal to 1200 V. The
current rating of the IGBT depends on the peak winding current.
The 3-phase inverter bridge is switched such that the sinusoidal current is injected into the motor
windings.
• Motor rating = 22 kW
• Line-to-line voltage = 415-V AC
• Power factor considered = 0.8
• Motor efficiency = 85%
Pout
I LL =
h motor ´ V LL ´ 3 ´ cos Æ
(1)
Current through the winding = 47 A
Therefore, the peak value of the winding current = √2 × IRMS = 66 A.
(2)
Considering an overloading of 200%, the peak winding current would be 132 A.
The IGBT module used in this reference design (CM150TX-24S1) has continuous collector current
carrying capacity of 150 A at TC = 100°C and peak current capacity of 300 A.
The selection of IGBT module with inbuilt NTC Thermistor is preferred to avoid thermal breakdown of the
IGBT. This IGBT temperature rise information is routed to the MCU to take necessary action.
IGBTs can be driven into saturation to provide a very low voltage drop between the emitter and collector.
10
Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System
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6.3
DC Link Voltage Sense Circuit
The DC bus input voltage to the inverter module is scaled down and fed to the MCU using the AMC1200
isolation amplifier, which has a gain of 8. The differential output of the AMC1200 can directly drive an
analog-to-digital converter (ADC) input or can be further filtered before being processed by the ADC.
The resistor divider network is chosen considering the maximum voltage for the MCU ADC input as 3.3 V
and the maximum DC link voltage to be measured as 1200 V.
To achieve better linearity and the noise performance of the device, the allowable input voltage between
the amplifier pin VINP and VINN is ±250 mV. The voltage divider resistor is selected such that input voltage
to the amplifier is less than ±250 mV at maximum DC bus condition.
Resistors R76 to R81 (see Figure 5) are selected as 1-M high-voltage resistors and R85 = 1K and R88 =
10K. The differential output of the AMC1200 is directly routed to ADC of MCU.
AMC Output = AMC Gain × VIN
æ R 85
V IN = ç
ç R IN
è
ö
÷ ´ V DC
÷
ø
(3)
æ
ö
1K
V IN = ç
÷ ´ V DC
è 6 M + 11 K ø
V IN = 0.00017 ´ V DC
For 400-V DC input
VIN = 0.00017 × 400 ≈ 0.0665 V and VOUT = 8 × 0.0665 V ≈ 0.532 V.
For 1200-V DC
VIN = 0.00017 × 1200 ≈ 0.2 V
VOUT = 8 × 0.2 V ≈ 1.6 V
A decoupling capacitor of 4.7 μF and 0.1 μF is used for filtering the power-supply path of the AMC1200. A
capacitor (C166 and C84 in Figure 5) should be placed as close as possible to the VDD1 pin for best
performance.
+5V_ISO
DC_POS
R76
R77
R78
R79
1M
1M
1M
1M
C166
3V3
4.7µF
C83
R80
1M
0.1µF
R81
1M
0.1µF
C84
U14
GND_ISO
R83
1
10 Ohm
R85
1K
R87
2
C85
0.01µF
4
10 Ohm
R88
10K
C86
10pF
3
C87
10pF
VDD1
VINP
VDD2
VOUTP
VINN
VOUTN
GND1
GND2
DGND
8
7
R84
0R
DC_BUS_SENSE_POS
6
R86
0R
DC_BUS_SENSE_NEG
5
AMC1200SDUBR
DGND
GND_ISO
GND_ISO
Figure 5. DC Voltage Sensing Module
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System Design Theory
6.4
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ISO5852S: Isolated IGBT Gate Driver
The ISO5852S is a 5.7-kVRMS, reinforced, isolated IGBT gate driver with split outputs OUTH and OUTL
capable of providing a 2.5-A source and 5-A sink currents. The primary side operates from a single 3.3-V
or 5-V supply. The output side allows for a supply range from minimum of 15 V to maximum 35 V. The
ISO5852S has both inverting and non-inverting gate control inputs, an active low reset input, and an open
drain fault output suitable for wired-OR applications.
Figure 6 shows the one section of the gate driver schematic. This IC can be powered with either a
unipolar or bipolar supply. If the IC is powered by unipolar supply, the VEE2 PIN should be connected to
GND2. The supply bypass capacitors provide the large transient currents necessary during a switching
transition.
The ISO5852S has the following features:
• 5.7-kVRMS reinforced isolation voltage
• 1.5-kVRMS working voltage
• 12-kV surge rating
• Split outputs providing 2.5-A peak source and 5-A peak sink currents
• Short propagation delay: 76 ns typical
• Active miller and short-circuit clamp
• Soft turn-off during short circuit
• FAULT alarm and RESET
• Input and output supply UVLO with ready (RDY) output
• CMOS compatible inputs
+15V R
3V3
C172
1µF
U7
15
VCC1
VCC2
GATE_R_TOP_GND
VEE2
VEE2
IN+
C174
1µF
1
8
1µF
C35
C33
10uF
0.1µF
J1
QPC02SXGN-RC
J2
QPC02SXGN-RC
2
1
VEE_R
13
RST1
14
RDY
CLAMP
FLT
OUTH
RST
OUTL
7
R34
0R
D69
TP44
4
R35
220R
R48
TP17
6
R38
220R
R37
0R
0R
1
2
GATE_R_TOP
J3
QPC02SXGN-RC
D24
3V3
DNP
2
R60
0R
1
R62
0R
DNP
D23
C
C40
200pF
C39
100pF
GL41Y-E3/96
A
C
DC_POS
GL41Y-E3/96
J4
QPC02SXGN-RC
DNP
GATE_R_TOP_GND
R49
0R
IN+_R_TOP
0R
PWM_DRV_R_TOP
A
NOTE:
To disable DESAT
DNP DESAT Capcitor
Populate Jumper
C38
10nF
ISO5852
R61
D4
R39
1k
C
12
FLT1
DESAT
A
RDY1
IN-
TP1
-8V R
2
1
11
1
IN-_R_TOP
1
DGND
1
10
C173
2
GND2
C
GND1
GND1
DNP
IN+_R_TOP
5
3
A
MM3Z12VB
4.7µF
9
16
RB160M-60TR
C31
0.1µF
NOTE:
Unipolar supply- Populate J1 only
Bipolar supply- Populate J2 only
1
R219
C29
C28
0.1µF
2
10R
C25
10uF
2
IN-_R_TOP
1
R63
0R
GATE_R_TOP_GND
J16
QPC02SXGN-RC
2
1
R233
0R
GATE_R_TOP_RTN
3
DGND
NOTE :
1. Non-inverting Configuration
2. Inverting Configuration
Figure 6. ISO5852S Application Schematic
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6.4.1
Power Supply
VCC1 and GND1 are the supply pins for the input side of the ISO5852S. The supply voltage at VCC1 can
range from 3 to 5.5 V with respect to GND1, thus supporting the direct interface to 3.3 V low-power
controllers as well as legacy 5 V controllers.
VCC2 and GND2 are the supply pins for the output side of the ISO5852S. VEE2 is the supply return for
the output driver and GND2 is the reference for the logic circuitry. The supply voltage at VCC2 can range
from 15 V up to 30 V with respect to VEE2.
A positive VGE of typically 15 V is required to switch the IGBT well into saturation. In this design, VCC2 is
fed with 16 V to ensure that IGBT is in full saturation.
For low power IGBTs, miller clamp functionality of the gate driver enables it to be operated with unipolar
voltage (VEE2 connected to GND2). For larger IGBTs, negative values of VGE, ranging from a required
minimum of –5 V up to the recommended –15 V, are necessary to keep the IGBT turned off and to
prevent it from unintentional conducting due to noise transients, particularly during short circuit faults. The
board has provision for connecting VEE2 to either 0 V or –8 V through jumpers.
+15V B_BOT
C187
1µF
U26
3V3
R217
C156
4.7µF
15
VCC1
VCC2
GND1
GND1
GND2
3
C188
1µF
DNP
10
C189
1µF
1
8
VEE2
VEE2
IN+
C101
10uF
J37
QPC02SXGN-RC
C159
0.1µF
2
IN+_B_BOT
C155
0.1µF
GATE_B_BOT_GND
C157
0.1µF
9
16
C98
10uF
5
1
10R
VEE_B_BOT
DGND
IN-_B_BOT
11
RDY6
12
FLT6
13
RST6
14
IN-
DESAT
RDY
CLAMP
FLT
OUTH
RST
OUTL
J38
QPC02SXGN-RC
2
1
-8V B_BOT
2
7
4
6
ISO5852
Figure 7. ISO5852S Supply Voltages
6.4.2
Control Signal Inputs
The two digital control inputs, IN+ and IN–, allow for inverting and non-inverting control of the gate driver
output. In the non-inverting configuration, IN+ receives the control input signal and VIN– is connected to
GND1. In the inverting configuration, VIN– is the control input while VIN+ is connected to VCC1.
U26
15
VCC1
VCC2
5
3V3
DNP
2
R167
0R
R1681
PWM_DRV_B_BOT
0R
R169 2
0R
DNP
1
R170
0R
9
16
IN+_B_BOT
10
IN-_B_BOT
11
12
13
GND1
GND1
GND2
IN+
VEE2
VEE2
IN-
DESAT
RDY
CLAMP
FLT
OUTH
RST
OUTL
3
1
8
2
7
4
DGND
14
6
ISO5852
Figure 8. ISO5852 Non-Inverting and Inverting Input Configurations
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Gate Resistance
The gate current and the appropriate power of the voltage supply depend on the operating frequency, bias
control voltages, and total gate charge. The total gate charge is published in IGBT datasheets, depending
on gate-control voltage. The gate charge necessary for switching is very important to establish the
switching performance of a MOSFET or IGBT. The lower the charge, the lower is the gate-drive current
needed for a given switching time. The gate current can be controlled using external gate resistor between
driver output and gate of IGBT. The value of the gate resistor determines the peak charge and discharge
currents.
The ISO5852S device features a split-output configuration where the gate drive current is sourced through
the OUTH pin and sunk through the OUTL pin. This pin arrangement provides flexibility to apply
independent turn-on and turn-off resistors to the OUTH and OUTL pins respectively and easily control the
switching slew rates. The value of the gate resistor influences different aspects of the switching process
like:
• IGBT switching losses
• Control di/dt
• Cross conduction
• Reverse recovery losses of the diode
The value of gate resistor is system dependent and usually chosen a value to provide optimum
performance. Strong sink capability (5 A) in an asymmetrical drive also boosts immunity against parasitic
Miller turn-on effect.
U7
15
9
16
10
11
12
13
VCC1
VCC2
GND1
GND1
GND2
IN+
VEE2
VEE2
IN-
DESAT
RDY
CLAMP
FLT
OUTH
5
3
1
8
2
7
4
RG(ON)
220R
6
RG(OFF)
220R
GATE
14
RST
OUTL
ISO5852
Figure 9. Gate Drive Split Outputs
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6.4.4
Optional External Current Buffer
When driving larger IGBTs requiring gate currents more than 5 A, an external current boost circuit can be
built with discrete NPN/PNP complimentary pair. One possible implementation is shown in Figure 10. The
selected BJT should be of fast switching and to have sufficient current gain to deliver the desired peak
output current. The circuit, in Figure 10, with a MJD3055T4/MJD2955 pair can drive gate currents up to 10
A.
+15V R_BOT
+15V R_BOT
2
+15V R_BOT
2
2
OUTH
MJD3055T4
1
220R
1
3
MJD3055T4
1
220R
3
220R
3
OUTH
OUTH
MJD3055T4
C
10R
SK310A-LTP
2.2R
2.2R
A
GATE
SK310A-LTP
10R
GATE
C
A
GATE
0R
2.2R
1
OUTL
MJD2955T4
220R
1
3
220R
220R
OUTL
2
2
OUTL
0R
3
3
2.2R
MJD2955T4
VEE_R_BOT
2
VEE_R_BOT
MJD2955T4
1
VEE_R_BOT
Figure 10. Options in Using External Current Buffer
6.4.5
Undervoltage Lockout
The undervoltage lockout feature prevents the application of insufficient gate voltage (VGE-ON) to the power
device by forcing OUTH/OTL low during power-up and whenever supply voltage drops below 11 V. IGBTs
typically require gate voltages of VGE = 15 V to achieve their rated, low saturation voltage, VCES. At gate
voltages below 13 V typically, their VCE-ON increases drastically, especially at higher collector currents. At
even lower voltages, that is VGE < 10 V, an IGBT starts operating in the linear region and quickly
overheats. The UVLO feature of ISO5852S avoids operating the IGBT in linear region by shutting it off
during insufficient gate supply voltage.
The UVLO feature has a hysteresis of 1 V typical and the typical values for the positive and negative
going input threshold voltages are VTH+ = 12 V and VTH– = 11 V.
6.4.6
Desaturation Protection (DESAT)
The DESAT fault detection prevents IGBT destruction due to excessive collector currents during a short
circuit fault. Short circuits caused by bad wiring, or overload conditions induced by the load can cause a
rapid increase in IGBT current, leading to excessive power dissipation and heating. IGBTs become
damaged when the current approaches the saturation current of the device and the collector-emitter
voltage, VCE, rises above the saturation voltage level, VCE-sat. The drastically increased power dissipation
overheats and destroys the IGBT.
To prevent damage to IGBT, ISO5852S slowly turns OFF the IGBT in the event of fault detection. Slow
turn OFF ensures the overcurrent is reduced in a controlled manner during the fault condition. The DESAT
fault detection involves a comparator that monitors the IGBT’s VCE and compares it to an internal 9-V
reference. If voltage across the IGBT reaches the threshold, DESAT detects immediately and blocks the
gate driver output and initiates a soft-turn-off procedure that disables the OUTH, and reduces the voltage
at OUTL over a minimum time span of 2 μs. The output is hard clamped to VEE2 when OUTL reaches 2 V
with respect to VEE2.
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DESAT Pin Protection
The diodes (GL41Y in Figure 11) at the DESAT signal block the high voltage during the IGBT OFF state
and conduct forward current, which allows the sensing of the IGBT’s saturated collector-to-emitter voltage
(VCESAT) when the IGBT is "ON". To avoid false DESAT triggering, fast switching diodes with low
capacitance are recommended. Because the sum of the DESAT diode forward-voltage and the IGBT
collector-emitter voltage make up the voltage at the DESAT-pin, VF + VCE = VDESAT, the VCE level, which
triggers a fault condition, can be modified by adding multiple DESAT diodes in series: VCE-FAULT (TH) = 9 V –
n × VF (where n is the number of DESAT diodes). When using two diodes instead of one, diodes with half
the required maximum reverse-voltage rating may be chosen. See Figure 11 where provision is provided
to mount two DESAT diodes.
Switching inductive loads causes large instantaneous forward voltage transients across the freewheeling
diodes of IGBTs. These transients result in large negative voltage spikes on the DESAT pin which draw
substantial current out of the device. To limit this current below damaging levels, a 100-Ω to 1-kΩ resistor
can be connected in series with the DESAT diode. Further protection is possible through an optional
Schottky diode (MM3Z12VB), whose low forward voltage assures clamping of the DESAT input to GND
potential at low voltage levels.
U24
14
DESAT
RDY
CLAMP
FLT
OUTH
RST
OUTL
2
7
4
6
D53
R159
TP41
A
1k
D55
D73
D54
C
A
GL41Y-E3/96
1
IN-
TP6
1
VEE2
VEE2
C
IN+
3
1
8
C149
200pF
C150
100pF
C
DC_POS
GL41Y-E3/96
J33
QPC02SXGN-RC
DNP
2
13
GND2
A
12
GND1
GND1
5
MM3Z12VB
11
VCC2
C
10
VCC1
A
9
16
RB160M-60TR
15
GATE_B_TOP_GND
ISO5852
Figure 11. DESAT Detection
DESAT Blanking Time
The DESAT fault detection must remain disabled for a short time period following the turn-on of the IGBT
to allow its collector voltage to drop below the 9-V DESAT threshold. This time period, called the DESAT
blanking time, tBLK, is controlled by an internal charge current of ICHG = 500 μA, the 9-V DESAT threshold,
VDSTH, and an external blanking capacitor, CBLK.
CDESAT = 100 pF (refer to C150 in Figure 11).
9 V ´ C DESAT
tb =
500 mA
tb =
(4)
9 V ´ 100 pF 500 mA
t b (ms ) = 1.8
The capacitor value can be scaled slightly to adjust the blanking time. However, because the blanking
capacitor and the DESAT diode capacitance build a voltage divider that attenuates large voltage transients
at DESAT, CBLK values smaller than 100 pF are not recommended.
If VCE exceeds this reference voltage (9 V) after the blanking time, the comparator inside ISO5852S
causes the gate drive and fault logic to initiate a fault shutdown sequence. This sequence starts with the
immediate generation of a fault signal, which is transmitted across the isolation barrier towards the fault
indicator circuit at the input side of the ISO5852S.
This board also provides feature of disabling the DESAT during testing by connecting the jumper at the
DESAT pin.
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6.4.7
Active Miller Clamp
During turn-on or turn-off of IGBTs, displacement current flows through the miller capacitor (gate to
collector capacitor) of the IGBT, raising its gate voltage. It could lead to unintentional turn-on of the IGBT.
When the high-side IGBT turns on within an inverter leg, the voltage across the low-side IGBT increases
with a high dv/dt. The ratio of reverse transfer capacitance to the input capacitance is larger for IGBTs
(CRES/CIES). This produces an increased Miller effect and a larger noise is coupled from the collector to the
gate.
This induces a current in the gate of the lower IGBT that may produce turn-on of the low-side device
shorting the DC bus.
However, certain low-power IGBTs have a lesser CRES (reverse transfer capacitance) and do not need
negative gate voltage for turn-off. Instead, the clamp functionality of the ISO5852S can be used to ensure
that gate is pulled to emitter thorough a low-impedance path, preventing a false turn-on.
The CLAMP transistor is turned on when OUTL reaches 2 V with regard to VEE2 during turn-off of the
IGBT. The CLAMP transistor hard clamps the OUTL pin to VEE2. The clamp transistor remains on once it
is ON even if OUTL goes above 2 V. The CLAMP transistor is again turned off during IGBT turn-on
process.
If the supply is unipolar, an active Miller clamp connects the output to VEE2 (Ground), and this condition is
latched. During a bipolar supply operation, the output is hard clamped to VEE2 (-8 V) when the IGBT is
turned off.
For larger IGBTs, a still negative gate voltage is required. Another reason for the negative gate voltage at
IGBTs is of the operation at higher voltages with increased (dv/dt) coupling of noise.
6.4.8
Fault and Protection Handling
The FAULT pin indicates an error event (with soft shutdown) has occurred such as IGBT short circuit.
Fault will be latched until the reset is applied. FAULT will go high, when the logic low pulse is applied to
RESET pin. This can be accomplished with an MCU, or an additional logic gate that synchronizes the
RESET signal with the appropriate input signal.
The ready pin is high during the primary and secondary side supplies are good. It is pulled LOW when the
supply voltage is less than the UVLO limits.
6.4.9
External Gate Emitter Capacitor to Shunt Miller Current
An option to mount external capacitor between IGBT gate and emitter has been provided to evaluate the
effectiveness of clamp functionality.
This capacitor can sink the additional charge originating from the Miller capacitance during the turn-on of
top IGBT. Due to the additional capacitance, the effective input capacitance of the IGBT is CG||CGE, the
gate charge required to reach the threshold voltage will be increased.
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Power Dissipation
In the process of turning the IGBT ON and OFF, power is dissipated by the driver IC, IGBT gate, and by
any RC circuits in the gate drive path.
VDC+
-16 V
Rg
PWM
-8 V
Cge (Ext)
VDC-
Figure 12. Driver Power Loss
The total gate power dissipation is calculated with Equation 5:
) (
P gate = P dc + Q gate ´ F sw ´ DV gate + C ge ´ F sw ´ DV 2gate
(
)
where
•
•
•
Qgate = total gate charge
Fsw = Switching frequency
ΔVgate = Gate driver output voltage swing
(5)
For CM150TX-24S1, Qg is approximated as 450 nC for bipolar switching and 300 nC for unipolar
switching with Vge = 15 V.
•
•
•
FSW = 16 KHz
ΔVgate = 15 V and 23 V
Cge = 10 nF
The static power dissipation of ISO5852S is PDC = IQ × VDD where IQ is the quiescent current for the
driver. The quiescent current is the current consumed by the device to bias all internal circuits such as
input stage, reference voltage, logic circuits, protections, and so on, and also any current associated with
switching of internal devices when the driver output changes state. The ISO5852S features very low
quiescent currents — 6 mA when supplied with 15 V and –8 V.
Power dissipation for bipolar switching: Pgate = 0.138 + 0.1656 + 0.085 = 0.4 W
Power dissipation for unipolar switching: Pgate = 0.2 W
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6.5
Half-Bridge SMPS for Gate Driver
A half-bridge SMPS is used to generate isolated positive (16 V) and negative (–8 V) voltage rails required
by IGBT gate drivers from a single 24-V DC input supply. The half-bridge driver is operated in open loop
mode with 500 kHz / 50% duty cycle generated by the Piccolo controller.
This half-bridge topology allows for more efficient use of the transformer core than the flyback or forward
converters. The transformer has two secondaries, each generating 8.7 V (required output = 8 V with a
diode drop of 0.7 V). A voltage doubler has been used to generate 16 V from the secondary generated 8
V. Each transformer is used to power TOP and BOTTOM IGBTs of each phase.
C
+15V R_BOT
D68
A
RB160M-60TR
C105
10µF
C108
10µF
C
+15V
C109
0.1µF
C106
47uF
D76
RB160M-60TR
A
R232
0R
GATE_R_BOT_GND
Half Bridge converter : SMPS
D42
A
C49
0.33 µF
C
D77
RB160M-60TR
+24V
C
LI
HS
NC
LO
UCC27211DPRT
VSS
NC
3
HSG
4
HS
10
LSG
R89
0R
R90
17.8 ohm
R92
R91
17.8 ohm
HS
D44
A
3
T2
8
D78
RB160M-60TR
2
9
13
C114
LS1
4
10µF
C97
3.3uF
CSD88537ND
C116
10µF
5
14
0R
C
+15V R
U15
1
6
5
9
6
A
SK310A-LTP
0.1µF
HO
5
C
C110
C
8
-8V R_BOT
A
0R
HI
A
C88
3.3uF
D43
7
8
R125
7
2
Transformer_SMPS
750313734
C
LI_PWM
0R
HB
3
HI_PWM
R124
DGND
VDD
DGND
C111
47uF
1
SK310A-LTP
U16
C113
0.1µF
C126
0.1µF
C115
47uF
D79
RB160M-60TR
A
C47
10µF
C112
10µF
GATE_R_TOP_GND
SK310A-LTP
DGND
DGND
C143
10µF
DGND
C
C147
0.1µF
C136
47uF
A
-8V R
D80
RB160M-60TR
Figure 13. Isolated Power Supply
During the turn-on and turn-off of IGBT, gate driver requires instant peak current from its power supply for
a short period of time, so it is important to use proper by-pass capacitors for the power supply. To achieve
the minimum output ripple with high-current load transients, a 47-μF capacitor at each of the output on the
secondary side is used.
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Transformer Specification
•
•
•
•
•
•
•
Two isolated outputs with VOUT1 = 8.7 V at 250 mA and VOUT2 = 8.7 V at 250 mA
Switching frequency = 500 kHz
Primary to secondary isolation = 7.4 kV for 1.2/50-µs impulse voltage
Type test voltage:
– Primary to Secondary = 3.6 kVRMS
– Secondary1 to Secondary2 = 1.8 kVRMS
Spacing:
– Primary to Secondary clearance = 8 mm
– Secondary1 to Secondary2 clearance = 5.5 mm
– Creepage distance = 9.2 mm
Functional Isolation Primary and secondary : 1.5-kV DC
DC isolation between secondaries: 1.5-kV DC
Figure 14. Half-Bridge Transformer Symbol
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6.6
Design of 24-V to 15-V and 5-V Step-Down DC-DC Converter
The 15-V regulated power supply for the half-bridge driver and 5 V are derived using the TPS54286
switching converter. The TPS54286 device is a dual step-down (buck) regulator with an integrated highside and low-side n-channel MOSFET. This operates in constant switching frequency, current mode
control which reduces output capacitance, and also reduces the complexity of compensation design. The
design specifications of the step-down converter are given Table 2. The schematic of the step-down
converter is shown in Figure 15.
Table 2. Design Specifications of Step-Down Converter
PARAMETER
SPECIFICATION
Output voltage
15 V and 5 V
Maximum output current
150 mA and 500 mA
Input voltage
24 V pre-regulated
Output voltage ripple
0.5% of VOUT
+24V
+24V
C117
C118
2
3.3R
0.033µF
3
4.7µF
C
C121
1nF
D21
A
C127
C123
4.7µF
SK310A-LTP
+15V
5
R97
51.1K GND
6
7
R98
10R
DNP
R101
2.87K
4
PVDD2
BOOT1
BOOT2
SW1
SW2
EN1
BP
EN2
SEQ
FB1
ILIM2
GND
15
C30
0.01µF
PVDD1
GND
FB2
10µF
14
13
12
GND
R94
3.3R
C120
11
10
9
C122
1nF
+5V
R95 0R
DNP
C128
8
DNP
C32
0.01µF
+5V
L2
47uH 1.5A
0.033µF
C
L1
100uH 0.5A
1
R93
PWPD
10µF
GND
C119
+15V
TPS54286PWP
R100
20K
R96
10R
D20
SK310A-LTP
C124
10µF
C125
4.7µF
A
U17
R99 4.7µF
0R
DNP
R102
3.83K
GND
GND
GND
GND
GND
Figure 15. 24-V to 15-V and 5-V Step-Down Converter
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Circuit Design
6.6.1.1
Output Inductor Selection (LO)
To calculate the minimum value of the output inductor,
For 5-V output
V OUT + V FD
Dmin » V IN(max ) + V FD
(6)
15 V + 0.7 V
» 0.23
24 V + 0.7 V
V IN(max ) - V OUT
1
´ D min ´ » I LRIP(max )
f SW
D min » L min
L min » (7)
24 - 5
1
´ 0.23 ´ = 48.71 mH » 47 mH
0.15
600 ´ 103
For 15-V output
15 V + 0.7 V
D min » » 0.635
24 V + 0.7 V
24 V - 15 V
1
L min » ´ 0.635 ´ = 95.25 mH » 100 mH
0.1
600 ´ 103
Ripple current for 15 V
V IN(max ) - V OUT
1
I RIPPLE »
´ Dmin ´ L
f SW
I RIPPLE »
24 V - 15 V
1
´ 0.635 ´ = 0.095 A » 0.1 A
100 mH
600 ´ 1
03
I L(rms ) =
(I ( ) ) + 121 (I
L avg
RIPPLE
I L(rms ) =
(0.2 )2 +
1
(0.1)2 = 0.202 A
12
2
(8)
2
)
(9)
Ripple current for 5 V
24 V - 5 V
1
I RIPPLE »
´ 0.230 ´ = 0.154 A » 0.15 A
47 mH
600 ´ 103
I L(rms ) =
22
(0.5 )2 +
1
(0.15 )2 = 0.501 A
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6.6.1.2
Output Capacitor
The internal compensation of the TPS54286 limits the selection of the output capacitors. Internal
compensation has a double zero resonance at about 6 kHz, so the output capacitor is selected by
Equation 10.
For 15 V
1
COUT = 2
(
4 ´ p ´ f RES
2
) ´ L
(10)
1
COUT = 2
(
4 ´ p ´ 6 ´ 10
3
2
) ´ 1 00 mH
= 7.04 mF
For 5 V
1
COUT = (
4 ´ p2 ´ 6 ´ 103
6.6.1.3
2
) ´ 47 mH
= 14.97 mF
Output Voltage Regulation
For this design feedback divider resistors (R97, R100) are 20K and 51.1K. The lower resistor R102 and
R103 are found using the following equations.
V FB ´ R97
R102 = V OUT1 - V FB
(11)
R102 = R103 = R103 = 6.6.1.4
0.8 ´ 51.1 ´ 103
= 2.873 kW
15 V - 0.8
V FB ´ R97
V OUT1 - V FB
0.8 ´ 20 ´ 10
5 - 0.8
(12)
3
= 3.809 kW
Bootstrap circuit
A 3.3-nF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. Use
a ceramic capacitor with X5R or better grade dielectric. The capacitor should be rated 50 V or higher.
A small resistor with value between 1 and 3 Ω to be placed in series with the bootstrap capacitor; this
reduces the rising edge ringing at the SW node.
6.6.1.5
Snubber
Fast switching and parasitic inductance and capacitance results in a voltage ringing at the SW node. If the
ringing results in excessive voltage on the SW node or erratic operation of the converter, an R-C snubber
(C = between 330 pF and 1 nF, R = 10 Ω) may be used to dampen the ringing at the SW node to ensure
proper operation over the full load range.
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Design of 5-V isolated DC-DC Converter
The AMC1200 requires isolated power supply for powering its input section. The SN6501 is used as a
switching device to generate a 5-V isolated output.
Table 3. Specifications for Selection of 5-V DC-DC Converter
PARAMETER
SPECIFICATION
Output voltage
5V
Output current required
10 mA
Input voltage
5V
Output voltage ripple
0.5% of VOUT
The SN6501 is a monolithic oscillator and power-driver, specifically designed for isolated power supplies
in isolated interface applications with small form factor. It drives a low-profile, center-tapped transformer
primary from a 3.3-V or 5-V DC power supply. The SN6501 consists of an oscillator followed by a gate
drive circuit that provides the complementary output signals to drive the ground referenced N-channel
power switches. The internal logic ensures break-before-make action between the two switches.
Features:
• Push-pull driver for small transformers
• Single 3.3-V or 5-V supply
+5V
C36
10uF
C37
0.1µF
+5V
D2
T1
1
2
2
D40
6
A
+5V_ISO
MBR0520LT3G
VCC
5
GND
D1
3
1
5
C41
10µF
D41
4
Wurth Elektronik
750313734
SN6501DBVR
R200
C
A
47 Ohm
C
GND
3
C43
0.1µF
DNP
C44
10µF
D63
A
DGND
U19
4
MM3Z5V1B
C
MBR0520LT3G
GND_ISO
DGND
Figure 16. Isolated 5-V Converter
Transformer Selection
To prevent a transformer from saturation its V-t product must be greater than the maximum V-t product
applied by the SN6501. The maximum voltage delivered by the SN6501 is the nominal converter input
plus 10%. The maximum time voltage is applied to the primary is half the period of the lowest frequency at
the specified input voltage. Therefore, the transformer’s minimum V-t product is determined using
Equation 13.
V IN-max
T
Vt min ³ V IN-max ´ max =
2
2 ´ f min
(13)
Vt min ³
5.5 V
= 9.1 Vms
2 ´ 300 kHz
Common V-t values for low-power center-tapped transformers range from 22 Vμs to 150 Vμs with typical
footprints of 10 × 12 mm. Other important factors to be considered in transformer selection are isolation
voltage, transformer wattage, and turns ratio.
Transformer Turns Ratio Estimation
V F-max + V DO -max + V O -max
n min = 1.031 ´
V IN-min - R DS -max ´ I D-max
24
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Table 4. Transformer Specifications
PARAMETERS
TEST CONDITIONS
VALUE
DC resistance 1-3
@ 20°C
0.419 Ω max
DC resistance 6-4
@ 20°C
0.335 Ω max
Inductance 1-3
100 kHz,10-mV AC, LS
340 µH min.
Dielectric 1-6
6250 VRMS, 1 second
5000 VRMS, 1 minute
Turns ratio
(6-4): (1-3)
1.1:1, +-2%
Figure 17. Isolated Transformer Construction
6.8
5-V To 3.3-V Regulator
Table 5. Specification of 3.3-V Output LDO
PARAMETER
SPECIFICATIONS
Input voltage
5V
Output
3.3 mA
Output current
350 mA
The LP38691 is selected is based on specifications outlined in Table 5. The LP3869x is a low-dropout
CMOS linear regulator providing tight output tolerance (2% typical), extremely low-dropout voltage (250
mV at 500-mA load current VOUT = 5 V), and excellent AC performance using ultra-low equivalent series
resistance (ESR) ceramic output capacitors.
Figure 18. 3.3-V Circuit
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Status Indications
The ISO5852S fault and ready indications are shorted and connected to two LED indications as shown in
Figure 19.
Figure 19. Status Indication Through LED
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6.10 LaunchPad Connections
The C2000 InstaSPIN™ Piccolo LaunchPad is used for controlling the inverter.
The LaunchPad has following connections to the power stage:
• Thermistor feedback from the IGBT module
• DC bus voltage feedback
• FAULT ready
• PWM enable and RESET signals from the ISO5852S
• Relay_Enable signal
• Fan drive signals
• PWM signals for half-bridge SMPS
• PWM signals for gate driver
PWM_EN is used to control the buffer providing PWM signals to ISO5852S.
Figure 20. LaunchPad Connections for C2000 Piccolo LaunchPad
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7.1
Power Supply
7.1.1
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3.3-V LDO Output (U18)
Figure 21. Output Voltage of 3.3-V LDO With Load of 100
mA
7.1.2
Buck Converter Outputs TPS54286PWP (U17)
7.1.2.1
15-V Output
Figure 23. 15-V Supply With Load of 15 mA
28
Figure 22. Ripples in 3.3-V LDO Output With Load of 100
mA
Figure 24. Ripples in 15-V Supply With Load of 15 mA
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7.1.2.2
5-V Output
Figure 25. 5-V Supply With Load of 150 mA
7.1.3
Figure 26. Ripples on 5 V With Load of 150 mA
Isolated 5-V Output SN6501DBVR (U19)
Figure 27. 5-V Isolated Supply Output With Load of 7 mA
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Figure 28. Ripple on 5-V Isolated Supply Output With
Load of 7 mA
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7.1.4
Half-Bridge Gate Driver supply
7.1.4.1
30
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16-V Output From Half-Bridge SMPS
Figure 29. 16 V during power ON
Figure 30. Ripples on 16 V at 2.5-A Source Current and
4.5-A Sink current
Figure 31. Ripples on 16 V at 2.5-A Source Current
Figure 32. Ripples on 16 V at 4.5-A Sink Current
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7.1.4.2
–8-V Output From Half-Bridge SMPS
Figure 33. –8 V During Power ON
Figure 34. Ripple on –8 V
Figure 35. Ripple on –8 V at 2.5-A Source Current
Figure 36. Ripple on –8 V at 4.5-A Sink Current
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Power ON Test Without External BJT/MOSFET Buffer
The undervoltage lockout feature monitors the secondary voltage rail and prevents the IGBT operating
with insufficient gate voltage (VGE-ON) by forcing OUTH/OUTL to low (during power-up else VCC2 drops
below 12 V). In Figure 37 and Figure 38, the gate driver output is held low (CH2) until VCC (CH3)
exceeds 12 V. CH1 represents the PWM input of ISO5852S.
Figure 37. Gate Driver Output During Power ON With
Unipolar Supply
Figure 38. Gate Driver Output (Zoomed)
NOTE: CH1: PWM from controller, CH2: Gate driver output, CH3: 16-V supply
Figure 39. Gate Driver Output During Power ON With
Bipolar Supply
Figure 40. Gate Driver Output (Zoomed)
NOTE: CH1: –8-V supply, CH2: Gate driver output, CH3: 16-V supply
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7.3
Power ON Test With External BJT Buffer
Figure 41. External BJT Buffer Output During Power ON
With Unipolar Supply
Figure 42. Gate Driver Output (Zoomed)
NOTE: CH1: PWM from controller, CH2: Gate driver output, CH3: 16-V supply
Figure 43. Gate Driver Output During Power ON With
Bipolar Supply
Figure 44. Gate Driver Output (Zoomed)
NOTE: CH1: –8-V supply, CH2: Gate driver output, CH3: 16-V supply
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2.5-A/5-A Sink and Source Current With Bipolar Supply Without BJT Buffer (Infineon
Module)
Figure 45 through Figure 47 show the sink and source currents delivered directly by ISO5852S.
Test conditions:
• RG (ON): 7.5 Ω
• RG (OFF): 0.0 Ω
• IGBT module: Infineon FS200R12KT4R_B11
• Gate charge (QG): 1.65 μC
• Internal resistance: 3.5 Ω
• Input capacitance Cies: 14 nF
Figure 45. Gate Driver Output — 2.5-A Source Current
Figure 46. Gate Driver Output — 4.5-A Sink Current
Figure 47. Source and Sink Current
NOTE: CH2: Gate current, CH3: Gate driver output
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7.5
PWM Signal Delay
Section 7.5.1 and Section 7.5.2 show the propagation delay between the Piccolo controller and the gate
driver.
Controller
PWM
PWM buffer
ISO5852S
IGBT gate driver
Figure 48. Piccolo Controller and Gate Driver Diagram
7.5.1
Delay Between PWM Buffer Input and PWM Buffer Output
Figure 49. Propagation Delay of PWM Buffer (R-Top)
(Rising Edge)
Figure 50. Propagation Delay of PWM Buffer (R-Top)
(Falling Edge)
Figure 51. Propagation Delay of PWM Buffer (R-Bot)
(Rising Edge)
Figure 52. Propagation Delay of PWM Buffer (R-Bot)
(Falling Edge)
NOTE: CH1: PWM from controller, CH2: PWM buffer output, CH3: Current buffer output
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Table 6. Delay Between PWM Signals
7.5.2
PWM BUFFER INPUT AND PWM BUFFER OUTPUT
TIME (ns)
R_Top (Rising)
5.0
R_Top (Falling)
5.0
R_Bottom (Rising)
3.0
R_Bottom (Falling)
4.0
Delay Between PWM Buffer Input and Gate Driver Output
Figure 53. Gate Driver Propagation Delay R_Top (Rising)
Figure 54. Gate Driver Propagation Delay R_Top
(Falling)
Figure 55. Gate Driver Propagation Delay R_Bottom
(Rising)
Figure 56. Gate Driver Propagation Delay R_Bottom
(Falling)
NOTE: CH1: PWM from controller, CH2: PWM buffer output, CH3: Current buffer output
Table 7. Delay Between PWM Signals
36
PWM BUFFER INPUT AND GATE DRIVER OUTPUT
TIME (ns)
R_Top (Rising)
84.0
R_Top (Falling)
80.0
R_Bottom (Rising)
82.0
R_Bottom (Falling)
81.0
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7.6
7.6.1
Induced Voltage at Gate for dV/dt of 2.5 kV/μs With 10-m Motor Cable
Active Miller Clamp Disabled
Figure 57. 2.5-kV/μs Inverter dV/dt
Figure 58. Induced Voltage at 2.5-kV/μs dV/dt
NOTE: 2.5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active miller
clamp disabled and Cge(Ext) = 0 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT
Figure 59. 2.5-kV/μs Inverter dV/dt
Figure 60. Induced Voltage at 2.5-kV/μs dV/dt
NOTE: 2.5-kV/μs inverter output and induced voltage at gate of bottom IGBT with active miller clamp
disabled and Cge(Ext) = 10 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT
Table 8. Summary of Induced Voltage for 2.5-kV/μS dV/dt (Active Miller Clamp Disabled)
TEST CONDITIONS
INDUCED VOLTAGE AT THE BOTTOM IGBT
(POSITIVE PEAK IN VOLTS)
Active Miller clamp disabled
Cge(Ext)=0nF
3.4
Active Miller clamp disabled
Cge(Ext)=10nF
2
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Active Miller Clamp Enabled
Figure 61. 2.5-kV/μs Inverter dV/dt
Figure 62. Induced Voltage at 2.5-kV/μs dV/dt
NOTE: 2.5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active miller
clamp enabled and Cge(Ext) = 0 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT
Figure 63. 2.5-kV/μs Inverter dV/dt
Figure 64. Induced Voltage at 2.5-kV/μs dV/dt
NOTE: 2.5-kV/μs inverter output and induced voltage at gate of bottom IGBT with active miller clamp
enabled and Cge(Ext) = 10 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT
Table 9. Summary of Induced Voltage for 2.5-kV/µs dV/dt (Active Miller Clamp Enabled)
38
TEST CONDITIONS
INDUCED VOLTAGE AT THE BOTTOM IGBT
(POSITIVE PEAK IN VOLTS)
Active Miller clamp enabled.
Cge(Ext) = 0 nF
0.4
Active Miller clamp enabled
Cge(Ext) = 10 nF
0.4
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7.7
7.7.1
Induced Voltage at Gate for dV/dt of 5 kV/μs With 10-m Motor Cable
Active Miller Clamp Disabled
Figure 65. 5-kV/μs Inverter dV/dt
Figure 66. Induced Voltage at 5-kV/μs dV/dt
NOTE: 5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active miller
clamp disabled and Cge(Ext) = 0 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT
Figure 67. 5-kV/μs Inverter dV/dt
Figure 68. Induced Voltage at 5-kV/μs dV/dt
NOTE: 5-kv/µs inverter output and induced voltage at the gate of bottom IGBT with active miller
clamp disabled and Cge(Ext) = 10 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT
Table 10. Summary of Induced Voltage for 5-kV/µs dV/dT (Active Miller Clamp Disabled)
TEST CONDITIONS
INDUCED VOLTAGE AT THE BOTTOM IGBT
(POSITIVE PEAK IN VOLTS)
Active Miller clamp disabled
Cge(Ext)=0nF
4
Active Miller clamp disabled
Cge(Ext)=10nF
2.8
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Active Miller Clamp Enabled
Figure 69. 5-kV/μs Inverter dV/dt
Figure 70. Induced Voltage at 5-kV/μs dV/dt
NOTE: 5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active miller
clamp enabled and Cge(Ext) = 0 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT
Figure 71. 5-kV/μs Inverter dV/dt
Figure 72. Induced Voltage at 5-kV/μs dV/dt
NOTE: 5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active miller
clamp enabled and Cge(Ext) = 10 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT
Table 11. Summary of Induced Voltage for 5-kV/μs dV/dt (Active Miller Clamp Enabled)
40
TEST CONDITIONS
INDUCED VOLTAGE AT THE BOTTOM IGBT
(POSITIVE PEAK IN VOLTS)
Active Miller clamp enabled
Cge(Ext) = 0 nF
0.44
Active Miller clamp enabled
Cge(Ext) = 10 nF
0.44
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7.8
7.8.1
Induced Voltage at Gate for dV/dt of 7.5 kV/μs With 10-m Motor Cable
Active Miller Clamp Disabled
Figure 73. 7.5-kV/μs Inverter dV/dt
Figure 74. Induced Voltage at 7.5-kV/μs dV/dt
NOTE: 7.5-kV/μs inverter output and induced voltage at the bottom IGBT - active miller clamp
disabled and Cge(Ext) = 0 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT
Figure 75. 7.5-kV/μs Inverter dV/dt
Figure 76. Induced Voltage at 7.5-kV/μs dV/dt
NOTE: 7.5-kV/μs inverter output and induced voltage at the bottom IGBT with active miller clamp
disabled and Cge(Ext) = 10 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT
Table 12. Summary of Induced Voltage for 7.5-kV/μs dV/dt (Active Miller Clamp Disabled)
TEST CONDITIONS
INDUCED VOLTAGE AT THE BOTTOM IGBT
(POSITIVE PEAK IN VOLTS)
Active Miller clamp disabled
Cge(Ext) = 0 nF
4
Active Miller clamp disabled
Cge(Ext) = 10 nF
3.2
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Active Miller Clamp Enabled
Figure 77. 7.5-kV/μs Inverter dV/dt
Figure 78. Induced Voltage at 7.5-kV/μs dV/dt
NOTE: 7.5-kV/μs inverter output and induced voltage at the gate of bottom IGBT with active miller
clamp enabled and Cge(Ext) = 0 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT
Figure 79. 7.5-kV/μs Inverter dV/dt
Figure 80. Induced Voltage at 7.5-kV/μs dV/dt
NOTE: 7.5-kV/μs inverter output and induced voltage at the gate of bottom IGBT - active miller
clamp enabled and Cge(Ext) = 10 nF
CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT
Table 13. Summary of Induced Voltage for 7.5-kV/μs dV/dt (Active Miller Clamp Enabled)
42
TEST CONDITIONS
INDUCED VOLTAGE AT THE BOTTOM IGBT
(POSITIVE PEAK IN VOLTS)
Active Miller clamp enabled
Cge(Ext) = 0 nF
0.72
Active Miller clamp enabled
Cge(Ext) = 10 nF
0.56
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7.9
Maximum Achievable dV/dt Without External BJT Buffer
Figure 81. Max dV/dt and Induced Voltage Without External Buffer With 10-m Motor Cable (Bipolar)
NOTE: CH1: Bottom gate driver output, CH2: Top gate driver output, CH3: Vce of bottom IGBT
Maximum dV/dt achieved without external BJT buffer: 8.47 kV/μs
Test conditions:
• RG (ON): 2.2 Ω
• RG (OFF): 2.2 Ω
• IGBT module: CM150TX-24S1_MITSUBISHI
• Gate charge (QG): 315 nC
• Internal resistance: 13 Ω
• Input capacitance CIES: 15 nF
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7.10 Current Through Clamp Pin
Figure 82. Current Through Clamp Pin
Test conditions:
• External buffer: without BJT
• Supply: Unipolar
• RG (ON): 2.2 Ω
• RG (OFF): 2.2 Ω
• IGBT module: CM150TX-24S1_MITSUBISHI
• Gate charge (QG): 315 nC
• Internal resistance: 13 Ω
• Input capacitance CIES: 15 nF
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7.11 Validation of Gate Signals With External Cable (Without BJT Buffer)
Figure 83. Gate signal at Gate of IGBT With 100-cm External Cable
NOTE: CH1: Gate driver output, CH3: Vce of bottom IGBT
Probe point
Out H
R1
Discharge
100 cm
cable
R3
Gate driver
ISO58252
D1
R4
Out L
I1
R2
Charge
IGBT
gate
Inverter
module
Figure 84. Block Diagram for Measurement of Gate Signal With External Cable
7.12 DESAT Signal During Normal Operation
Figure 85. DESAT During Normal Operation (Zoomed)
Figure 86. DESAT During Normal Operation
NOTE: CH1: Bottom gate driver output, CH2: DESAT signal, CH3: Vce of bottom IGBT
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7.13 Short Circuit Test — Hard Switched
NOTE: All the tests in Section 7.13 and Section 7.14 were performed using engineering samples of
ISO5852S. The final silicon has a higher pulldown drive during soft shutdown when
compared to the engineering samples, resulting in lower soft shutdown time for given Qg of
the IGBT die. Refer to the latest datasheet of ISO5852S on TI Website at
http://www.ti.com/product/ISO5852S
Figure 87 shows the block diagram of hard-switched fault setup.
+24-V DC
+800-V DC
C2000 LaunchPAD interface
SMPS
PWMs
HALF
BRIDGE
SMPS
IGBT power
module
+16 V
-8 V
+16 V
-8 V
Inverter PWM signals
Reinforced
isolated
IGBT gate
driver ±
ISO5852S
Gate
drive
signals
Short between
inverter output
to DC (-ve)
DC bus sensing
NTC output
Figure 87. Block Diagram of Short Circuit Setup (Hard Fault Switch)
A hard fault switch short circuit test was performed using the power module CM150TX24S1_MITSUBISHI. This test is performed such that one arm of the inverter bottom IGBT already has a
short (from Figure 87, Y phase output is connected to DC negative), during the same turning ON the top
IGBT (Y_Top) to know the performance of DESAT detection.
Test conditions:
• Short circuit connection: Y-phase inverter output to DC negative
• Motor connected: NO
• Inverter dV/dT: 2.5 kV/μs, 5 kV/μs, 7.5 kV/μs
• IGBT module: CM150TX-24S1_MITSUBISHI
• Gate charge (QG): 315 nC
• Internal resistance: 13 Ω
• Input capacitance CIES: 15 nF
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7.13.1
Hard Switched Fault With Inverter dV/dt of 2.5kV/μs
Figure 88. DESAT Activation to Gate Driver Turn OFF
Figure 89. DESAT Activation to Fault Indication
Figure 90. Gate Driver Output During Soft Shutdown
NOTE: CH1: Fault signal, CH2: PWM from Controller, CH3: DESAT signal, CH4: Gate driver output
Figure 91. Voltage Across (Vce) Top IGBT
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Figure 92. IC — During Short circuit
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NOTE: CH1: Short circuit current, CH2: PWM from Controller, CH3: DESAT signal, CH4: Vce of top
IGBT
Table 14. Summary of Short Circuit Test of Hard Switched Fault with 2.5 kV/µs
PARAMETER
VALUE
DESAT activation to gate driver turn OFF
360.0 ns
DESAT activation to Fault indication
1.16 µs
Soft shutdown time
10.2 µs
Short circuit current
1.04 kA
Dip in Vce
7.13.2
220 V
Hard Switched Fault With Inverter dV/dt of 5 kV/μs
Figure 93. DESAT Activation to Gate Driver Turn OFF
Figure 94. DESAT Activation to Fault Indication
Figure 95. Gate Driver Output During Soft Shutdown
NOTE: CH1: Fault signal, CH2: PWM from Controller, CH3: DESAT signal, CH4: Gate driver output
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Figure 96. Voltage Across (Vce) Top IGBT and IC– During Short Circuit
NOTE: CH1: Short circuit current, CH2: PWM from Controller, CH3: DESAT signal, CH4: Vce of top
IGBT
Table 15. Summary of Short Circuit Test of Hard Switched Fault with 5 kV/µs
PARAMETER
VALUE
DESAT activation time to gate driver turn OFF
360 ns
DESAT activation to fault output
800 ns
Soft shutdown time
10.5 µs
Short circuit current
1.05 kA
Dip in Vce
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7.13.3
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Hard Switched Fault With Inverter dV/dt of 7.5 kV/μs
Figure 97. DESAT Activation to Gate Driver Turn OFF
Figure 98. DESAT Activation to Fault Indication
NOTE: CH1: Fault signal, CH2: PWM from Controller, CH3: DESAT signal, CH4: Gate driver output
Figure 99. Voltage Across (Vce) Top IGBT
Figure 100. IC– During Short Circuit
NOTE: CH1: Short circuit current, CH2: PWM from Controller, CH3: DESAT signal, CH4: Vce of top
IGBT
Table 16. Summary of Short Circuit Test of Hard Switched Fault with 7.5 kV/µs
PARAMETER
760 ns
DESAT activation to fault
1.12 µs
Soft shutdown time
10 µs
Short circuit current
1.08 kA
Dip in Vce
50
VALUE
DESAT activation to gate driver turn OFF
270 V
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7.14 Short Circuit Test — Fault Under Load
A fault under load short circuit test was performed using the power module CM150TX-4S1_MITSUBISHI.
This test is conducted using a add on module for the short circuit consisting of high power IGBT
connected between one of the phase output to DC negative. Refer Figure 101 for the test setup.
Figure 101. Setup for Short Circuit Test — Fault Under Load
7.14.1
Fault Under Load Short Between Phase to DC –ve for 2.5-kV/µs Inverter Output
Test conditions:
• Short circuit connection: R phase inverter output to DC negative
• Motor connected: Yes
• Inverter dV/dT: 2.5 kV/µs
• IGBT module: CM150TX-24S1_MITSUBISHI
• Gate charge (QG): 315 nC
• Internal resistance: 13 Ω
• Input capacitance CIES: 15 nF
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+24-V DC
+800-V DC
C2000 LaunchPAD interface
SMPS
PWMs
HALF
BRIDGE
SMPS
IGBT power
module
+16 V
-8 V
+16 V
-8 V
Reinforced
isolated
IGBT gate
driver ±
ISO5852S
3N ACIM
Gate
drive
signals
Inverter PWM signals
DC bus sensing
Add on module for
short circuit test
NTC output
Isolated gate
driver
800 V -ve
Figure 102. Block Diagram of Fault Under Load Test Short Between Phase to DC –ve
Figure 103. DESAT Activation to Fault Output
Figure 104. Gate Driver Output During Soft Shutdown
Table 17. Summary of Short Circuit Test — Fault Under Load for 2.5 kV/µs
(Phase Output to DC Negative)
PARAMETER
52
VALUE
DESAT activation to gate driver turn OFF
1.30 µs
Soft shutdown
14.80 µs
Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System
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7.14.2
Fault Under Load — Short Circuit Between Phase to Phase
A fault under load short circuit test was performed using Mitsubishi power module CM150TX-24S1. This
test is conducted using a add-on module for the short circuit consisting of high-power IGBT connected
between R_phase and Y_phase of inverter output (see Figure 105).
+24-V DC
+800-V DC
C2000 LaunchPAD interface
SMPS
PWMs
HALF
BRIDGE
SMPS
IGBT power
module
+16 V
-8 V
+16 V
-8 V
Reinforced
isolated
IGBT gate
driver ±
ISO5852S
Inverter PWM signals
3N ACIM
Gate
drive
signals
DC bus sensing
Add on module for
short circuit test
NTC output
Isolated gate
driver
Figure 105. Block Diagram of Fault Under Load Test — Phase-to-Phase Short (dV/dt: 2.5 kV/µs)
Test conditions:
• Short circuit connection: Between R_phase and Y_phase
• Motor connected: Yes
• Inverter dV/dT: 2.5 kV/µs
• Cable length: 10 meters
• IGBT module: CM150TX-24S1_MITSUBISHI
• Gate charge (QG): 315 nC
• Internal resistance: 13 Ω
• Input capacitance CIES: 15 nF
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Figure 106. Gate Driver Output During Soft Shutdown
Figure 107. DESAT Activation to Gate Driver Turn Off
NOTE: CH1: Fault signal, CH2:PWM from Controller, CH3: DESAT signal, CH4: Gate driver output
Figure 108. IC– During Short Circuit Fault Under Load
NOTE: CH1: Short circuit current, CH2: PWM from Controller, CH3: DESAT signal, CH4: Gate driver
output
Table 18. Summary of Short Circuit Test for Fault Under Load for 2.5 kV/µs (Phase-to-Phase Short)
PARAMETER
420.0 ns
Soft shutdown of gate driver output
11.20 µs
Peak current
54
VALUE
DESAT activation to gate driver turn OFF
980 A
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7.15 EMC Test
7.15.1
Electrical Fast Transient (EFT) Test
EFT pulses were applied to motor cable using capacitive coupling clamp as per IEC 61000-4-4. This test
was conducted for multiple levels of fast transient voltages (±1 kV, ±2 kV, ±3 kV, ±4 kV) at 5 kHz for
duration of 60 seconds.
Different configurations used during testing are listed in Table 19:
Table 19. EFT Test Configurations
UUT/AUX EQUIPMENT
LOCATION
REFERENCE
Shielded
Ground plane
Figure 109
Shielded
10-cm isolated from plane
Figure 110
3
Unshielded
Ground plane
Figure 111
4
Unshielded
10-cm isolated from plane
Figure 112
TEST CONFIGURATION
MOTOR CABLE
1
2
Test setup:
• DC bus voltage: 400 V
• Auxiliary unit power rating: 2.2 kW
• Load condition: No load
• Motor rpm: 750 rpm
• Cable length: 10 meters
• EFT test equipment: emtest UCS 500N
• Capacitor coupling network
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Figure 109. Test Configuration 1
Figure 110. Test Configuration 2
Figure 111. Test Configuration 3
Figure 112. Test Configuration 4
Table 20. EFT Test Results
EFT PULSES
DURATION
TEST RESULTS
Config:1
Config:2
Config:3
Config:4
1 kV
60 seconds
PASS
PASS
PASS
PASS
–1 kV
60 seconds
PASS
PASS
PASS
PASS
2 kV
60 seconds
PASS
PASS
PASS
PASS
–2 kV
60 seconds
PASS
PASS
PASS
PASS
3 kV
60 seconds
PASS
PASS
PASS
PASS
–3 kV
60 seconds
PASS
PASS
PASS
PASS
4 kV
60 seconds
PASS
PASS
PASS
PASS
–4 kV
60 seconds
PASS
PASS
PASS
PASS
Test pass refers to motor running continuously (without unusual sound) with no malfunctioning observed in
the power stage (includes IGBT gate drivers), thereby meeting performance class B requirements as per
IEC61800-3.
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7.15.2
Electrostatic Discharge (ESD) Test
ESD pulses were applied (contact discharge) to the heat sink while the power stage was running the
motor to check for malfunctions. CD was applied on the heat sink close to the IGBT gate drivers. ESD
pulses were applied at multiple levels (±2 kV, ±4 kV, ±6 kV, ±8 kV) with 10 pulses on each polarity and
level. IEC 61000-4-2 has been used as reference for the test method.
Different configurations used during testing are listed in Table 21:
Table 21. ESD Test Configurations
TEST CONFIGURATION
UUT/AUX EQUIPMENT LOCATION
REFERENCE
1
Insulated sheet
Figure 113 and Figure 114
2
Ground reference plane
Figure 116
3
10 cm isolated from reference
Figure 115
Test setup:
• DC bus voltage: 400 V
• Auxiliary unit power rating: 2.2 kW
• Load condition: No load
• Motor rpm: 750 rpm
• Cable length: 10 meters (Unshielded)
• ESD test equipment: emtest UCS 500N
Table 22. ESD Test Results
ESD PULSES
DURATION
2 kV
TEST RESULTS
Config:1
Config:2
Config:3
10 pulses
PASS
PASS
PASS
–2 kV
10 pulses
PASS
PASS
PASS
4 kV
10 pulses
PASS
PASS
PASS
–4 kV
10 pulses
PASS
PASS
PASS
6 kV
10 pulses
PASS
PASS
PASS
–6 kV
10 pulses
PASS
PASS
PASS
8 kV
10 pulses
PASS
PASS
PASS
–8 kV
10 pulses
PASS
PASS
PASS
A test pass refers to the motor running continuously (without unusual sound) with no malfunctioning
observed in the power stage (includes IGBT gate drivers), thereby meeting performance class B
requirements as per IEC61800-3.
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Figure 113. EUT/AUX Equipment on Insulated Sheet
Figure 114. Test Configuration 1
Figure 115. EUT/AUX Equipment Isolated From
Reference Plane by 10 cm
Figure 116. Test Configuration 2: EUT/AUX Equipment on Reference Plane
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Design Files
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8
Design Files
8.1
Schematics
To download the schematics, see the design files at TIDA-00195.
D1
CN1
1
Te rminal bush
A
C
RHRG75120
R208
200K
C3
680µF
R209
200K
IGBT Module
U1
R212
200K
C7
680µF
R213
200K
FS200R12KT4R
C154
FILM CAP
0.22µF
30
31
CN11
1 DC_POS
C
Te rminal bush
R210
200K
32
16
D2
RHRG75120
CN12
17
1 BRAKE
INRUSH_BYPASS
18
GATE_BRAKE
DC_VOLT_POS3
MOT_R_PHASE3
33
E
34
35
15
CN2
1
14
13
MOTOR_R_PHASE
28
29
DC_VOLT_POS5
DC_VOLT_POS6
MOT_Y_PHASE2
DC_VOLT_NEG1
MOT_Y_PHASE1
GATE_R_TOP
1
GATE_R_TOP_RTN
2
GATE_Y_TOP
5
GATE_Y_TOP_RTN
6
GATE_B_TOP
GATE_B_TOP_RTN
9
10
GATE_R_BOTTOM
3
GATE_R_BOT_RTN
4
GATE_Y_BOTTOM
7
GATE_Y_BOT_RTN
8
GATE_B_BOTTOM
11
GATE_B_BOT_RTN
12
26
MOTOR_Y_PHASE
25
24
DC_VOLT_NEG2
DC_VOLT_NEG3
DC_VOLT_NEG6
DC_VOLT_NEG5
MOT_B_PHASE1
DC_VOLT_NEG4
MOT_B_PHASE2
MOT_B_PHASE3
PGND
27
DC_VOLT_POS4
MOT_Y_PHASE3
Q1
G
APT70GR120L
t°
MOT_R_PHASE2
C
R211
200K
RT1
100R_PTC
B59109J0130A020
MOT_R_PHASE1
DC_VOLT_POS2
A
C6
680µF
DC_VOLT_POS1
21
MOTOR_B_PHASE
22
23
GATE_R_TOP
GATE_R_TOP_RTN
NTC_1
GATE_Y_TOP
NTC_2
19
NTC_1
20
NTC_2
GATE_Y_TOP_RTN
GATE_B_TOP
DGND
GATE_B_TOP_RTN
GATE_R_BOTTOM
GATE_R_BOT_RTN
Motor connector
GATE_Y_BOTTOM
GATE_Y_BOT_RTN
MOTOR_B_PHASE
MOTOR_Y_PHASE
MOTOR_R_PHASE
GATE_B_BOTTOM
GATE_B_BOT_RTN
1
2
3
CN3
1986242-3
IC_FS200R12KT4R
Figure 117. IGBT Module
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+15V R
3V3
15
VCC1
VCC2
GND1
GND1
GND2
1µF
1
8
10uF
0.1µF
J2
QPC02SXGN-RC
13
RST1
14
RDY
CLAMP
FLT
OUTH
RST
OUTL
TP1
1
-8V R
R34
7
0R
+15V R
TP44
4
R35
6
MJD3055T4
Q6
1
D69
Q9
SUD50P08-25L-E3
D24
C40
200pF
10R C
1
R36
A
R48
R121
2.2R
SK310A-LTP
R37
A
0R
DC_POS
J4
QPC02SXGN-RC
GATE_R_TOP_GND
3
0R
DNP
1
C39
100pF
C
GL41Y-E3/96
NOTE:
To disable DESAT
DNP DESAT Capcitor
Populate umper
J
D3
R107
0R
D23
C
GL41Y-E3/96
DNP
DNP
TP18
3
ISO5852
A
1k
220R
DNP
TP17
D4
R39
TP37
1
FLT1
2
2
2
12
DESAT
C
RDY1
IN-
A
11
1
IN-_R_TOP
NOTE :
1. Non-inverting Configuration
2. Inverting Configuration
C33
VEE_R
DGND
DGND
1µF
J1
QPC02SXGN-RC
C35
1
VEE2
VEE2
IN+
C174
C
10
C173
A
IN+_R_TOP
GATE_R_TOP_GND
3
MM3Z12VB
DNP
IN-_R_TOP
1
R63
0R
5
2
R62 2
0R
DNP
9
16
RB160M-60TR
C31
0.1µF
4.7µF
0R
PWM_DRV_R_TOP
R219
C29
Gate Driver Top IGBT R
NOTE:
Unipolar supply- Populate J1 only
Bipolar supply- Populate J2 only
C28
0.1µF
1
10R
IN+_R_TOP
10uF
1
1
C25
1
R61
C172
1µF
U7
3V3
2
DNP
2
R60
0R
GATE_R_TOP
2
J3
QPC02SXGN-RC
R134
2.2R
C38
10nF
DNP
NOTE :
3. DNP While testingwith twistedpair
3
R122
0R
R38
MJD2955T4
Q8
220R
1
DNP
R49
0R
DNP
2
Q7
SUD40N08-16-E3
J16
QPC02SXGN-RC
+15V R_BOT
U9
VCC1
VCC2
GND1
GND1
GND2
C48
0.1µF
IN-
DESAT
1
8
1µF
C50
0.1µF
VEE_R_BOT
DGND
RST2
14
FLT
OUTH
RST
OUTL
R40
7
TP19
4
0R
TP20
6
R41
220R
MJD3055T4
Q10
1
DNP
Q13
SUD50P08-25L-E3
R234
3
ISO5852
1
R135
0R
R145
2.2R
3V3
PWM_DRV_R_BOT
R44
R822
0R
1
10R
C
R7
1
R105
0R
GATE_R_BOT_GND
DNP
GATE_R_BOTTOM
2
C55
10nF
A
NOTE :
3. DNP While testingwith twistedpair
0R
R235
0R
Q12
MJD2955T4
Q11
SUD40N08-16-E3
1
GATE_R_TOP_RTN
3
DNP
220R
IN-_R_BOT
C
GL41Y-E3/96
J9
QPC02SXGN-RC
SK310A-LTP
GATE_R_BOT_GND
2
DNP
R146
0R
IN+_R_BOT
0R
R161
2.2R
3
R67 1
DNP
A
DNP
DNP D5
R42
DNP
2
R66
0R
0R
D25
C
GL41Y-E3/96
C56
100pF
200pF
QPC02SXGN-RC
J8
TP21
A
C57
D26
D70
+15V R_BOT
D6
R45
1k
A
CLAMP
TP38
1
RDY
-8V R_BOT
2
13
1
1
12
FLT2
2
TP2
2
1
RDY2
Gate Driver Bottom IGBT R
J7
QPC02SXGN-RC
2
VEE2
VEE2
J6
QPC02SXGN-RC
1
IN+
C51
10uF
1
11
GATE_R_BOT_GND
C177
C
IN-_R_BOT
All Notes are app
licable for all Gate Driver Sections
C45
0.1µF
A
10
GATE_R_TOP_RTN
1
C176
3
1µF
DNP
IN+_R_BOT
C42
10uF
MM3Z12VB
9
16
C175
1µF
5
RB160M-60TR
C46
4.7µF
15
C
R220
2
1
10R
GATE_R_TOP_GND
3
R233
0R DNP
2
3V3
VEE_R
J17
QPC02SXGN-RC
2
1
DNP
GATE_R_BOT_RTN
R236 3
0R DNP
VEE_R_BOT
DGND
Figure 118. Gate Driver R
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+15V Y
3V3
U20
GND1
GND1
GND2
C179
1µF
C59
10uF
C180
1µF
1
8
J19
QPC02SXGN-RC
C61
0.1µF
J20
QPC02SXGN-RC
VEE_Y
13
RDY
CLAMP
FLT
OUTH
RST
OUTL
-8V Y
TP22
+15V Y
0R
D71
TP23
RST3
14
6
1
NOTE :
1. Non-inverting Configuration
2. Inverting Configuration
R136
220R
MJD3055T4
Q14
1
Q17
SUD50P08-25L-E3
D46
C
A
C
DC_POS
GL41Y-E3/96 GL41Y-E3/96
D47
C66
100pF
C64
200pF
DNP
J21
QPC02SXGN-RC
GATE_Y_TOP_GND
3
DNP
A
1k
R133
7
4
D45
R132
TP39
1
12
FLT3
DESAT
TP4
1
2
RDY3
IN-
2
2
C
11
2
DGND
IN-_Y_TOP
A
DGND
1
VEE2
VEE2
IN+
3
C
IN+_Y_TOP 10
GATE_Y_TOP_GND
1
DNP
IN-_Y_TOP
1
R131
0R
Gate Driver Top IGBT Y
C53
0.1µF
A
9
16
C52
10uF
C178
1µF
5
1
2
R130
0R
DNP
VCC2
C58
0.1µF
C54
4.7µF
0R
VCC1
MM3Z12VB
15
RB160M-60TR
R214
1
R1291
PWM_DRV_Y_TOP
10R
2
3V3
2
R128
0R
DNP
IN+_Y_TOP
ISO5852
TP24
R162
0R
DNP
D48
R137
1
R172
2.2R
C
10R
R138 0R
DNP
R183
2.2R
0R
3
DNP
1
GATE_Y_TOP
2
QPC02SXGN-RC
J22
C71
10nF
NOTE :
3. DNP While testingwith twistedpair
3
R173
0R
R237
A
SK310A-LTP
R139
220R
Q16
MJD2955T4
1
Q15
SUD40N08-16-E3
R238
0R
DNP
2
DNP
J24
QPC02SXGN-RC
+15V Y_BOT
GATE_Y_TOP_GND
VEE_Y
2
GATE_Y_TOP_RTN
1
R239 3
U22
10
IN-_Y_BOT
11
IN+
VEE2
VEE2
C69
10uF
C183
1µF
1
8
DGND
J26
QPC02SXGN-RC
VEE_Y_BOT
RDY
CLAMP
FLT
OUTH
RST
OUTL
TP40
R147
7
TP25
4
+15V Y_BOT
0R
D72
TP26
14
6
1
RST4
R148
220R
MJD3055T4
Q18
1
Q21
SUD50P08-25L-E3
ISO5852
DNP
2
R140
0R
IN+_Y_BOT
10R C
220R
C142
10nF
SK310A-LTP
R150
0R
Q20
MJD2955T4
1
DNP
R241
0R
Q19
SUD40N08-16-E3
GATE_Y_BOT_GND
J30
QPC02SXGN-RC
2
1
R242
0R
DGND
J27
QPC02SXGN-RC
GATE_Y_BOTTOM
2
NOTE :
3. DNP While testingwith twistedpair
DNP
R151
GATE_Y_TOP_RTN
GATE_Y_BOT_GND
3
IN-_Y_BOT
1
R143
0R
C
GL41Y-E3/96
DNP
QPC02SXGN-RC
J28
A
C139
100pF
A
GATE_Y_BOT_RTN
2
2
R142
DNP
R149
DNP
R187
2.2R
R186
0R
0R
0R
D52
C138
200pF
D50
C
GL41Y-E3/96
DNP
1
DNP
1
3V3
PWM_DRV_Y_BOT
TP27
R185
2.2R
A
3
R240
0R
R184
0R
R1411
D51
3
DNP
D49
R144
1k
C
13
-8V Y_BOT
A
FLT4
TP5
1
2
12
DESAT
2
2
1
RDY4
IN-
Gate Driver Bottom IGBT Y
J25
QPC02SXGN-RC
C137
0.1µF
2
IN+_Y_BOT
C182
1µF
1
DNP
GATE_Y_BOT_GND
3
1
GND2
C
VCC2
GND1
GND1
A
VCC1
MM3Z12VB
9
16
C133
0.1µF
RB160M-60TR
C135
0.1µF
4.7µF
0R DNP
C60
10uF
C181
1µF
5
1
C134
15
1
10R R215
2
3V3
3
DNP
VEE_Y_BOT
Figure 119. Gate Driver Y
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+15V B
U24
3V3
15
C94
10uF
C186
1µF
1
8
VEE2
VEE2
C148
0.1µF
VEE_B
IN-_B_TOP
11
IN-
2
TP6
1
-8V B
2
DESAT
RDY
CLAMP
FLT
OUTH
C
+15V B
TP28
4
TP29
14
RST
DNP
R163
220R
3
MJD3055T4
Q22
1
1
Q25
SUD50P08-25L-E3
G
2
3
NOTE :
1. Non-inverting Configuration
2. Inverting Configuration
6
OUTL
1
RST5
DGND
D55
D73
C149
RB160M-60TR 200pF
A
13
0R
1
FLT5
R160
7
TP30
C
A
10R
0R
0R
J33
QPC02SXGN-RC
DNP
GATE_B_TOP_GND
GATE_B_TOP
2
QPC02SXGN-RC
J34
C153
10nF
NOTE :
3. DNP While testingwith twistedpair
3
2
DNP
Q24
MJD2955
1T4
1
R244
0R
Q23
SUD40N08-16-E3
SD
220R
G
2
R166
DC_POS
DNP
1
DNP
R191
2.2R
C
GL41Y-E3/96
3
R243
SK310A-LTP
R165
R190
0R
C150
100pF
A
D56
R164
1
R189
2.2R
D54
C
GL41Y-E3/96
DNP
ISO5852
R188
0R
A
1k
DS
12
2
1
R158
0R
RDY5
D53
R159
TP41
IN-_B_TOP
1
DGND
Gate Driver Top IGBT B
J32
QPC02SXGN-RC
2
IN+
J31
QPC02SXGN-RC
1
C185
1µF
C
IN+_B_TOP 10
IN+_B_TOP
2
GATE_B_TOP_GND
3
1
R157
0R
DNP
GND2
C144
0.1µF
1
9
16
DNP
0R
PWM_DRV_B_TOP
GND1
GND1
C91
10uF
C184
1µF
5
A
R156 1
VCC2
C146
0.1µF
C145
4.7µF
3V3
DNP
2
R155
0R
VCC1
MM3Z12VB
R216
2
10R
3
DNP
VEE_B
J36
QPC02SXGN-RC
GATE_B_TOP_GND
2
1
GATE_B_TOP_RTN
+15V B_BOT
R245
C187
1µF
U26
3V3
15
VCC1
VCC2
5
GATE_B_BOT_GND
1
C157
0.1µF
IN-
DESAT
C189
1µF
1
8
C159
0.1µF
VEE_B_BOT
DGND
13
RDY
CLAMP
FLT
OUTH
RST
OUTL
-8V B_BOT
TP42
R174
7
TP31
4
+15V B_BOT
0R
D74
TP32
14
6
D59
MJD3055T4
R175
1
RST6
220R
1
Q26
Q29
SUD50P08-25L-E3
3
DNP
TP33
R192
0R
3V3
DNP
2
R167
0R
R1681
R195
2.2R
R194
0R
IN-_B_BOT
R178
220R
10R
R246
D60
C
A
0R
DNP
C161
100pF
J42
QPC02SXGN-RC
GATE_B_BOT_GND
2
1
R248
VEE_B_BOT
0R
A
C
GATE_B_TOP_RTN
GL41Y-E3/96
J39
QPC02SXGN-RC
DNP
GATE_B_BOT_GND
GATE_B_BOTTOM
2
QPC02SXGN-RC
J40
DGND
D58
C
GL41Y-E3/96
3
DNP
Q27
SUD40N08-16-E3
A
DNP
1
SK310A-LTP
0R
C160
200pF
C164
10nF
R247
0R
Q28
MJD2955T4
1
2
1
R170
0R
R176
R177
IN+_B_BOT
0R
R169 2
0R
DNP
R193
2.2R
3
PWM_DRV_B_BOT
DNP
1
ISO5852
D57
R171
1k
A
FLT6
TP7
1
2
12
2
2
1
RDY6
Gate Driver Bottom IGBT B
J38
QPC02SXGN-RC
2
11
VEE2
VEE2
1
IN-_B_BOT
IN+
1
10
J37
QPC02SXGN-RC
C
IN+_B_BOT
C101
10uF
A
DNP
C188
1µF
MM3Z12VB
GND2
C
GND1
GND1
3
RB160M-60TR
9
16
1
R217
C156
4.7µF
DNP
C155
0.1µF
2
10R
0R
C98
10uF
3
NOTE :
3. DNP While testingwith twistedpair
DNP
GATE_B_BOT_RTN
3
DNP
Figure 120. Gate Driver B
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Gate Driver Brake IGBT
+15V B_BOT
C65
0.1µF 9
GND1
GND1
GND2
GATE_B_BOT_GND
0.1µF
VEE_BRAKE
RST7
14
RDY
CLAMP
FLT
OUTH
RST
OUTL
TP43
TP34
4
0R
6
D75
R55
TP35
47R
A
1k
R54
7
D10
R59
1
13
-8V B_BOT
A
FLT7
TP3
1
1
12
DESAT
J12
1
RDY7
IN
2
QPC02SXGN-RC
2
1
11
J11
QPC02SXGN-RC
D39
C74
200pF
C73
100pF
D62
C
A
GL41Y-E3/96
C
BRAKE
GL41Y-E3/96
J14
QPC02SXGN-RC
DNP
2
1µF
1
8
C67
1
VEE2
VEE2
C107
10uF
C
IN+
C192
C191
1µF
A
10
3
DGND
IN-_BRAKE
C62
0.1µF
5
MM3Z12VB
16
IN+_BRAKE
VCC2
C
4.7µF
VCC1
1
C63
15
RB160M-60TR
R218
2
10R
C104
10uF
C190
1µF
U11
3V3
GATE_B_BOT_GND
ISO5852
GATE_BRAKE
R58
NOTE :
3. DNP While testingwith twistedpair
47R
3V3
DNP
2
R117
0R
R118 1
0R
PWM_DRV_BRAKER
IN+_BRAKE
R119 2
DNP
0R
J18
QPC02SXGN-RC
GATE_B_BOT_GND 2
1
R251
DNP
0R
3
IN-_BRAKE
1
R120
0R
PGND
DGND
Figure 121. Brake Drive
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Ready Indication
RST1
Reset Control
RST2
RST3
3V3
3V3
A
C
R64
10K
RDY1
R47
120 Ohm
RDY2
R51
RST4
D7
GREEN
LTST-C170GKT
RST
RST6
RST7
SMPS Power Rails LED indications
RDY3
RDY4
RST
0R
RST5
LTST-C170GKT
RDY
R50
Q3A
BC847BPN,115
20K
RDY5
+15V R
-8V R
1.3K
R108
D27A
620 Ohm
R109
D28C
1.3K
R110
D29A
RDY7
-8V Y
620 Ohm
R111
D30C
-8V B
Fault Indication
+15V R_BOT
-8V R_BOT
+15V Y_BOT
3V3
-8V Y_BOT
3V3
R65
10K
-8V B_BOT
FLT1
FLT3
FLT4
+24V
FLT
R53
Q3B
BC847BPN,115
20K
C
FLT5
FLT6
FLT7
+5V
3V3
A
FLT2
+15V B_BOT
D8
LTST-C170EKT
RED
R52
120 Ohm
+15V
GATE_R_TOP_GND
C
GATE_R_TOP_GND
GATE_Y_TOP_GND
GREEN
A
GATE_Y_TOP_GND
GREEN
DGND
+15V B
A
GREEN
RDY6
+15V Y
C
GREEN
1.3K
R112
D31A
620 Ohm
R113
D32C
C
GATE_B_TOP_GND
GREEN
A
GATE_B_TOP_GND
GREEN
1.3K
R1
D33
A
620 Ohm
R2
D34
C
1.3K
R3
D81
A
C
620 Ohm
R4
D82
C
A
1.3K
R5
D83
A
C
620 Ohm
R6
D84
C
A
C
GATE_R_BOT_GND
GREEN
A
GATE_R_BOT_GND
GREEN
GATE_Y_BOT_GND
GREEN
GATE_Y_BOT_GND
GREEN
GATE_B_BOT_GND
GREEN
GATE_B_BOT_GND
GREEN
2.37K
R152
D35
A
300 Ohm
R153
D36
A
120 Ohm
R154
D37
A
C
LTST-C170
GKT
GREEN
1.3K
R116
D38
A
C
GREEN
C
DGND
GREEN
C
GREEN
GND
DGND
Figure 122. LED Indications
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Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System
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GATE_DRIVER_BUFFER
3V3
3V3
R106
10K
4OE
1Y
4A
2OE
4Y
3
PWM_DRV_R_TOP
R17
4
5
10K
6
7
2A
3OE
2Y
3A
GND
R15
14
VCC
1A
0.01µF
C68
12
4
5
DGND
10
9
6
7
8
3Y
DGND
R14
14
VCC
1A
4OE
1Y
4A
10R
13
12
11
2OE
4Y
2A
3OE
2Y
3A
GND
3Y
10
0.01µF
C34
PWM_R_BOT
PWM_DRV_R_BOT DGND
9
8
SN74ALVC125PW
DGND
SN74ALVC125PW
DGND
3
PWM_DRV_Y_TOP
11
1OE
2
PWM_Y_TOP
10R
13
R20
1OE
2
10K
1
PWM_EN
PWM_R_TOP
3V3
U2
1
PWM_EN
R16
3V3
U3
10K
R12
10K
DGND
DGND
DGND
3V3
R18
10K
5
6
R27
PWM_DRV_BRAKER
7
2OE
4Y
2A
3OE
2Y
3A
GND
SN74ALVC125PW
10K
DGND
4A
3Y
PWM_EN
12
0.01µF
C70
FAN_DRV
11
FAN_DRV_BUFFER
1OE
2
PWM_B_TOP
3
PWM_DRV_B_TOP
4
DGND
5
10
9
PWM_B_BOT
8
6
7
PWM_DRV_B_BOT
VCC
1A
4OE
1Y
4A
2OE
4Y
2A
3OE
2Y
3A
GND
3Y
R21
14
10R
13
12
PWM_Y_BOT
11
10
R24
1Y
10R
13
4OE
R23
4
PWM_EN
BRAKER_ON
VCC
1A
10K
3
R25
2
DGND
R19
10K
3V3
U4
1
PWM_EN
0.01µF
C195
PWM_DRV_Y_BOT DGND
9
8
SN74ALVC125PW
DGND
DGND
R26
10K
DGND
10K
1OE
3V3
R22
14
10K
3V3
U5
1
DGND
DGND
DGND
Figure 123. Gate Driver Buffer
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PWM_R_TOP
PWM_R_TOP
R68
10R
C76
0.01µF
DGND
R69
10R
C77
0.01µF
CN6
DGND
PWM_Y_TOP
PWM_Y_TOP
R70
20
1
19
2
18
3
17
4
16
5
15
6
14
7
13
8
DGND
R71
PWM_Y_BOT
10R
C79
0.01µF
DGND
12
9
11
10
BRAKER_ON
10R
C82
0.01µF
DGND
R9
10R
R10
10R
R11
PPPC102LFBN-RC
R72
PWM_B_TOP
PWM_B_TOP
BYPASS_RELAY
R74
10R
C78
0.01µF
PWM_Y_BOT
DGND
10R
FAN_DRV
HI_PWM
LI_PWM
HI_PWM
LI_PWM
C26
1.5nF
C27
1.5nF
10R
DGND
DGND
C80
0.01µF
DGND
Launch Pad Connector J6 & J2
DGND
PWM_B_BOT
PWM_B_BOT
R73
C24
0.01µF
10R
C81
0.01µF
From Launch Pad
PWM_R_BOT
PWM_R_BOT
DGND
3V3
R8
+5V
R13
0R
CN9
0R
C169
10uF
20
1
19
2
18
3
17
4
16
5
15
6
14
7
C168
10uF
DGND
DGND
PWM_EN
FLT
RDY
RST
13
8
12
9
11
10
3V3
DC_BUS_SENSE_NEG
DC_BUS_SENSE_POS
R75
10K
NTC_1
C196
0.01µF
PPPC102LFBN-RC
Launch Pad Connector J1 & J5
DGND
Figure 124. Board-to-Board Connections
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Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System
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DC BUS VOLTAGE SENSING
+5V_ISO
3V3
C166 4.7µF
C83
0.1µF
0.1µF
C84
U14
GND_ISO
DC_POS
R76
R77
R78
R79
R80
R81
R83
1
1M
1M
1M
1M
1M
1M
10 Ohm
2
R85
1K
C85
0.01µF
R87
3
4
10 Ohm
R88
10K
C86
10pF
C87
10pF
VDD1
VDD2
VINP
VOUTP
VINN
VOUTN
GND1
GND2
DGND
8
7
R84
0R
DC_BUS_SENSE_POS
6
R86
0R
DC_BUS_SENSE_NEG
C197
0.1µF
5
AMC1200SDUBR
DGND
GND_ISO
GND_ISO
+5V
C36
10uF
C37
0.1µF
+5V
D2
T1
3
1
2
2
1
3
D40
6
A
+5V_ISO
MBR0520LT3G
VCC
5
GND
D1
SN6501DBVR
R200
C
5
C41
10µF
D41
4
Wurth Elektronik
750313734
A
47 Ohm
C
GND
C43
0.1µF
DNP
C44
10µF
D63
A
DGND
U19
4
MM3Z5V1B
C
MBR0520LT3G
GND_ISO
DGND
R123
0R
PGND
GND_ISO
Figure 125. DC Bus Voltage Sensing
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C
+15V R_BOT
D68
A
RB160M-60TR
C105
10µF
C108
10µF
C
+15V
C109
0.1µF
C106
47uF
D76
RB160M-60TR
A
R232
0R
GATE_R_BOT_GND
Half Bridge converter : SMPS
D42
C47
10µF
A
C49
0.33 µF
D77
RB160M-60TR
C
+24V
SK310A-LTP
HS
NC
LO
VSS
NC
UCC27211DPRT
-8V R_BOT
1
0.1µF
LI
A
3
HSG
4
HS
10
LSG
R89
0R R90
17.8 ohm
HS
R91
17.8 ohm
D44
A
T2
8
D78
RB160M-60TR
9
13
C114
LS1
4
10µF
C97
3.3uF
CSD88537ND
C116
10µF
5
14
0R
C
3
2
1
6
5
R92
+15V R
U15
SK310A-LTP
9
6
C
C110
HO
5
A
C88
3.3uF
D43
C
HI
C111
47uF
A
8
2
Transformer_SMPS
750313734
C
0R
HB
7
8
R125
C
C113
0.1µF
C126
0.1µF
C115
47uF
D79
RB160M-60TR
A
LI_PWM
7
3
HI_PWM
DGND
0R
VDD
U16
DGND
R124
C112
10µF
GATE_R_TOP_GND
SK310A-LTP
DGND
DGND
C143
10µF
DGND
C
C136
47uF
-8V R
D80
RB160M-60TR
0393570002
Molex
1
2
A
C147
0.1µF
D11
A
+24V
C
S5B-E3/57T
P1
C89
68µF
C90
0.1µF
DGND
DGND
Figure 126. Gate Driver Power Supply (R Phase)
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C
+15V Y_BOT
A
D12
RB160M-60TR
C1
10µF
C
C4
10µF
C5
0.1µF
C2
47uF
D13
A
RB160M-60TR
GATE_Y_BOT_GND
C9
10µF
C10
0.1µF
C8
47uF
D14
C
A
-8V Y_BOT
RB160M-60TR
+24V
+15V Y
3
T3
8
C
HS
D15
RB160M-60TR
C158
3.3uF
A
9
13
C11
LS2
10µF
Transformer_SMPS
750313734
C
14
C14
0.1µF
C12
47uF
D16
RB160M-60TR
A
C165
3.3uF
C13
10µF
5
GATE_Y_TOP_GND
DGND
D17
RB160M-60TR
C
C16
10µF
C17
0.1µF
C15
47uF
A
-8V Y
C
+15V B_BOT
A
D18
RB160M-60TR
10µF
C20
10µF
C
C18
C21
0.1µF
C19
47uF
A
D19
RB160M-60TR
GATE_B_BOT_GND
C23
10µF
D64
C
C92
0.1µF
C22
47uF
A
-8V B_BOT
RB160M-60TR
+15V B
3
LS3
5
C167
3.3uF
T4
8
D65
RB160M-60TR
A
HS
C
+24V
9
13
C93
10µF
Transformer_SMPS
750313734
C99
0.1µF
C95
47uF
D66
RB160M-60TR
A
C170
3.3uF
C96
10µF
C
14
GATE_B_TOP_GND
C102
10µF
DGND
C
C103
0.1µF
C100
47uF
A
-8V B
D67
RB160M-60TR
Figure 127. Gate Driver Power Supply (Y and B Phase)
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Design Files
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Buck Converter 24V to 15V & 5V
+24V
+24V
C117
C118
2
3.3R
0.033µF
3
4.7µF
C
C121
1nF
D21
5
R97
51.1K GND
6
7
R98
10R
A
C127
C123
4.7µF
SK310A-LTP
+15V
DNP
R101
2.87K
4
PVDD2
BOOT1
BOOT2
SW1
SW2
EN1
BP
EN2
SEQ
FB1
GND
15
C30
0.01µF
ILIM2
GND
FB2
10µF
14
13
12
GND
R94
3.3R
C120
11
C122
1nF
R95 0R
DNP
10
9
+5V
C128
8
DNP
C32
0.01µF
+5V
L2
47uH 1.5A
0.033µF
C
R93
PVDD1
PWPD
L1
100uH 0.5A
1
GND
C119
+15V
TPS54286PWP
R100
20K
R96
10R
D20
SK310A-LTP
C124
10µF
C125
4.7µF
A
U17
10µF
R99 4.7µF
0R
DNP
R102
3.83K
GND
GND
GND
GND
GND
3.3V LDO
+5V
3V3
U18
VCC
VOUT
1
C130
10µF
2
GND
3
C129
10µF
LP38691DTX
GND
DGND
GND
Figure 128. Buck Converter 24 V to 15 V and 5 V
70
Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System
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Fan Driver Circuit
Inrush Bypass Relay : Drive Circuit
+24V
C
CN10
PGND
D61
SK310A-LTP
A
1
2
Fan
4
1
INRUSH_BYPASS
RL1
R182
0R
5
6
HE1aN-P-DC24V-Y5
R103
D
+24V
C
10R
A
FAN_DRV_BUFFER
FAN_DRV_BUFFER
R179
Q4
MFG_PN
CSD18531Q5A
G
200 Ohm
DNP
C
R180
10K
S
D22
SK310A-LTP
C131
10µF
R104
Q5
PZT2222A
B
470R
DGND
E
BYPASS_RELAY
DGND
Figure 129. Inrush Relay
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Design Files
8.2
www.ti.com
Bill of Materials
To download the bill of materials (BOM), see the design files at TIDA-00195.
8.3
Layer Plots
To download the layer plots, see the design files at TIDA-00195.
8.4
Altium Project
To download the Altium project files, see the design files at TIDA-00195.
8.5
Gerber Files
To download the Gerber files, see the design files at TIDA-00195.
8.6
Assembly Drawings
To download the assembly drawings, see the design files at TIDA-00195.
72
Isolated IGBT Gate Driver Evaluation Platform for 3-Phase Inverter System
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References
www.ti.com
9
References
1. IEEE, Analytical calculation of the RMS current stress on the DC-link capacitor of voltage-PWM
converter systems, Kolar, J.W.; ETH Zurich, Power Electron. Syst. Lab., Zurich; Round, S.D., July
2006
10
Terminology
PWM— Pulse Width Modulation
LaunchPad— All reference to LaunchPad refers to InstaSPIN-FOC enabled C2000 LaunchPads
CFM— Cubic Feet per Minute
MCU— Microcontroller unit
FETs, MOSFETs— Metal–oxide–semiconductor field-effect transistor
IGBT— Insulated Bipolar Gate Transistor
ESD— Electro Static Discharge
EFT— Electrical Fast Transients
RPM— Rotation per Minute
RMS— Root Mean Square
11
Acknowledgments
The authors would like to thank Kamat Anant and Baranwal Shailendra (Industrial Interface Business unit
at TI) for their technical contributions to this design.
12
About the Authors
KRISTEN MOGENSEN is a system engineer in the Industrial Systems–Motor Drive team at Texas
Instruments, responsible for developing reference designs for industrial drives.
N. NAVANEETH KUMAR is a systems architect at Texas Instruments, where he is responsible for
developing subsystem solutions for motor controls within Industrial Systems. N. Navaneeth brings to this
role his extensive experience in power electronics, EMC, analog, and mixed signal designs. He has
system-level product design experience in drives, solar inverters, UPS, and protection relays. N.
Navaneeth earned his Bachelor of Electronics and Communication Engineering from Bharathiar
University, India and his Master of Science in Electronic Product Development from Bolton University, UK.
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Revision History
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Revision History
Changes from Original (June 2015) to A Revision ......................................................................................................... Page
•
Added Note under Section 7.13
.......................................................................................................
46
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
74
Revision History
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