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International Journal of Electrical, Electronics and Computer Systems (IJEECS) _______________________________________________________________________________________________ An Integrated Circuit for EEG Acquisition System with Programmable Gain Amplifier in 0.18µm Technology 1 Abhishek Goyal, 2Prashant Bansod Electronics and Instrumentation Department SGSITS Indore Email: [email protected], [email protected] Abstract—This work describes a 0.18µm CMOS implementation of an EEG acquisition system with programmable gain amplifier. Gain of the amplifier is digitally programmable from 35.09 dB to 62.55 dB by using 6 bits digital input. EEG input signals are of the range of few micro-voltage. Hence a high gain operational transconductance amplifier with gain of 62.83 dB is designed. Two 22:1 multiplexers with 5 selection lines are used in this design for input selection from electrodes connected to scalp. The proposed amplifier and multiplexer have been tested for the EEG signals and their performance is reported at operating voltage of 1.8 volts. This design can be used in an integrated circuit for EEG front end for monitoring and diagnosis. with programmable gain, which is most important stage in design. Besides low power, the key design points are high CMRR, and low noise [5]. Amplifier stage is comprised of a standard folded cascode OTA and small integrated capacitors the amplification is adjustable among 7 different discrete values for better fitting the neural amplifier output signal to the analog to digital conversion (ADC) stage. The amplifier can provide a gain ranging from 35.09 dB to 62.55 dB [6]. II. PROPOSED DESIGN Index Terms— Multiplexer unit, low power operational trans-conductance amplifier, and programmable gain amplifier. I. INTRODUCTION Electroencephalogram (EEG) waves are commonly monitored bio-potential signals. They have micro voltage level amplitude and low frequency i.e. in the range of 1-150µV and 0.5-150Hz respectively [1], [2]. Electroencephalogram (EEG) records the electrical activity along the scalp as a diagnosis reference of Epilepsy, encephalopathy and brain death. EEG signals are measured by placing several electrodes on head around the brain. Between certain electrodes a potential difference is measured and converted into waveform i.e. EEG signals. Commonly, the long-time monitoring will cause discomforts to patients, because they will be connected to a large instrument which restricts their mobility. It makes the long-time experiments more difficult, and even affects the accuracy of the recorded EEG signal [3], [4]. Thus, a portable EEG signal acquisition system is of great demand for clinical practice and research [3]. Figure 1. Proposed integrated circuit Proposed integrated circuit is shown in figure 1 in which EEG input signal is applied from 21 electrodes and design has two discrete inputs, one is 5 bit electrode selection input to select the required combination of EEG signals; second is 6 bit gate selection input to select desired value of gain. VDD and VSS are power supply input of integrated circuit III. SYSTEM ARCHITECTURE In this paper an EEG acquisition system is presented. The EEG acquisition system as given on figure 1 is proposed system includes two 22:1 multiplexers for selection stage in this paper. It has two components the multiplexer stage to select input from various electrodes and amplifier stage _______________________________________________________________________________________________ ISSN (Online): 2347-2820, Volume -2, Issue-5,6, 2014 65 International Journal of Electrical, Electronics and Computer Systems (IJEECS) _______________________________________________________________________________________________ and amplifier stage. Multiplexers are used for selecting the input from electrodes connected to patient’s head. And amplifier stage amplifies the difference of EEG signals selected from multiplexer stage. Selections lines of multiplexer will be connected to output of an up counter which is used to avoid don’t care condition of selection inputs. Facility to select desired value of gain is also available in this design using discrete inputs. The overall architecture is depicted in figure2. 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 C3 P3 FP2 F4 C4 P4 FP2 F8 T8 P8 FZ CZ P7 T7 FT9 FT10 P3 O1 F4 C4 P4 O2 F8 T8 P8 O2 CZ PZ T7 FT9 FT10 T8 V. AMPLIFIER DESIGN Figure 2. Overall architecture of proposed work IV. MULTIPLEXER UNIT Two 22:1 multiplexers are used to select two different EEG inputs from electrodes. These two selected inputs are applied at the input of the amplifier. Design of multiplexer is based on structural modeling in VHDL. Such modeling is preferred to minimize the number of transistors. Schematic of multiplexer is shown in figure 3 and respective truth table is shown in table 1. TABLE 2: AMPLIFIER SPECFICATION FOR EEG SIGNAL PARAMETERS Technology Supply Voltage Gain CMRR Bandwidth DC offset SPECIFICATION 0.18µm 1.8V ≥40dB ≥80dB 300Hz < ±1mV The overall gain is determined by the amplitude of the EEG signal and the output range The EEG amplifier should achieve high gain; two-stage amplifier will be a good choice. In addition, rejection of the electrode dc offset before amplification is necessary to achieve the required dynamic range [3]. Design specifications for EEG amplifier are described in table 2 and the proposed amplifier schematic is shown in figure 4. Figure 3. 22:1 Schematic of multiplexer TABLE 1: TRUTH TABLE OF MULTIPLEXER SELECTION INPUT 00000 00001 00010 00011 00100 00101 SELECTED ELECTRODE BY MUX1 FP1 F7 T7 P7 FP1 F3 SELECTED ELECTRODE BY MUX2 F7 T7 P7 O1 F3 C3 Figure 4. Schematic of proposed EEG amplifier The amplifier comprised of small integrated capacitors to control gain, which can range approximately from 35.09 _______________________________________________________________________________________________ ISSN (Online): 2347-2820, Volume -2, Issue-5,6, 2014 66 International Journal of Electrical, Electronics and Computer Systems (IJEECS) _______________________________________________________________________________________________ dB to 62.55 dB. Range of variable gain with respective selected digital input and capacitor value is shown in table 3. Integrated capacitors Ca0, Ca1, Ca2, Ca3, Ca4, Ca5, and Ca6 were taken respectively 1.1fF, 1.1fF, 2fF, 4.2fF, 10fF, 55.2fF, and 426.4fF. The variable gain is necessary to best fit the signal to the ADC stage, thus avoiding loss of resolution or signal saturation, while keeping the signal as reliable as possible. It also could mean an ADC of fewer bits, and consequently operating at lower frequencies [6]. TABLE 4: W/L OF OTA TRANSISTORS FOR EEG AMPLIFIER TABLE 3: TRUTH TABLE FOR GAIN SELECTION For creating EEG signal on Cadence, Vpwlf source is used by creating pwl file. Creating arbitrary waveform in cadence is tedious and changes are difficult. Piece wise linear (PWL) files are text files with row of time/value pairs [8]. INPUT BITS 000000 000001 000011 000111 001111 011111 111111 CAPACITOR VALUE 1.1f F 2.2f F 4.2f F 8.4f F 18.4f F 73.6f F 500f F GAIN (in dB) 35.09 40.77 45.80 50.70 55.30 60.35 62.55 VI. LOW POWER OTA DESIGN An ideal OTA has two voltage inputs with infinite impedance (i.e. there is no input current). The common mode input range is also infinite, while the differential signal between these two inputs is used to control an ideal current source (i.e. the output current does not depend on the output voltage) that functions as an output. The proportionality factor between output current and input differential voltage is called Trans-conductance [7].The OTA is similar to a standard operational amplifier in that it has a high impedance differential input stage and that it may be used with negative feedback. DEVICES M1,M2 M3,M4,M5,M6 M7,M8 M9,M10 MCASCN MCASCP W/L (µm) 40.5/0.18 1.8/7.2 1.08/4.5 28.8/14.4 2.16/1.08 1.17/0.72 VII. SIMULATION RESULTS A. Transient analysis The simulated transient analysis of the vin verses time and vout verses time shown in the figure. The simulated waveforms prove that applied input EEG signal in range of microvolts. In this analysis casecode bias voltages are 2.2µV and -2.2µV respectively. And biasing current Ibias is 8µA. Transient response of proposed amplifier has been analyzed by applying EEG input signals. ; EEG signals is applied as input. And simulated input output response is given below in figure 6. Figure 5 shows the schematic of the OTA used for neural signal amplification that can be used in a wide range of applications [6]. The bias current and case code bias voltage were generated by standard circuit. Transistors W/L ratios for OTA are given in table 4. Figure 6. Transient analysis of amplifier with EEG input B. Ac analysis of proposed amplifier After the successful transient analysis, AC analysis has been done for the proposed amplifier circuit. In this case, biasing voltages and current are kept same. And other important parameters such as gain, phase response, CMRR, noise factor are measured. The gain and phase plot is shown in figure 7. Figure 5. Schematic of OTA _______________________________________________________________________________________________ ISSN (Online): 2347-2820, Volume -2, Issue-5,6, 2014 67 International Journal of Electrical, Electronics and Computer Systems (IJEECS) _______________________________________________________________________________________________ D. Input referred noise Figure 7. Gain and phase plot The common mode rejection ratio measures how the output changes in response to a change in the common-mode input level. CMRR plot is shown in figure 11. Ideally, the common mode gain of an amplifier is zero. CMRR can be obtained as …. (1) Figure 10. Input referred noise VIII. CONCLUSION In this paper an EEG acquisition system using on 0.18µm technology is proposed. The result obtained is shown in table 5. The input can vary in the range of microvolts. Therefore the simulation results with 35.09-62.55dB value of programmable gain, 100.10dB value of CMRR, 314Hz bandwidth, -448.7µV value of dc offset, and 2.2µVrms value of input referred noise are obtained. These results demonstrate that the proposed circuit can be used to develop an integrated circuit for EEG acquisition IC. IX. ACKNOWLEDGEMENTS Figure 11. CMRR C. Dc offset Amplifier offset voltage is an important parameter to understand. It is a voltage error that is a consequence of the amplifier’s mismatched input amplifier stage. This work has been carried out in SMDP VLSI laboratory of the Electronics and Instrumentation department of Shri G. S. Institute of Technology and Science, Indore, India. This SMDP VLSI project is funded by Ministry of Information and Communication Technology, Government of India. Authors are thankful to the Ministry for the facilities provided under this project. TABLE 5: RESULTS AND COMPARISION PARAMETERS UNIT [6] [10] µm Volts µA dB SPECIFICATIONS 0.18 1.8 ≥40 Technology Supply voltage Biasing current Gain 1.5 2.5 16 40 0.5 1.8 6 40.22 CMRR Bandwidth dB Hz ≥80 300 42 7.5K DC offset Input referred noise Volts Vrms <±1m - 2.1µ 86.32 1.96 K 2.2µ THIS WORK 0.18 1.8 10 35.09-62.5 5 100.10 314 -448.7µ 2.2µ X. REFERENCES [1]. Figure 9. DC offset H. Zhou, M. Voelker and J. Hauer, “A mixed-signal front end ASIC for EEG acquisition system” IEEE 2012. _______________________________________________________________________________________________ ISSN (Online): 2347-2820, Volume -2, Issue-5,6, 2014 68 International Journal of Electrical, Electronics and Computer Systems (IJEECS) _______________________________________________________________________________________________ [2]. A. El-Kholy, M. Ghoneima, and K. Sharaf, “A 0.8 6.4 µw compact mixed-signal front-end for nueral implants,” ISCAS, 2012, pp 2223-2226. [9]. [3]. Hung Liu, Kea-Tiong Tang, Jo-Yu Wu and Guoxing Wang. “A digitally trimmable low-noise low power analog front end for EEG signal acquisition”. IEEE EMBS pp. Jan. 2012. [10]. R. Harrison and C. Charles, "A low-power low-noise CMOS amplifier for neural recording applications,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 958 - 965, Jun. 2003. [4]. J.M. Corrigan, M.S. Donaldson, L.T. Kohn, T Mckay and K.C. Pike “To err is human : Building a safer health system.” American Institute of Medicine. Tech Rep. Nov. 2000. [11]. Woradorn Wattanapanitch, Michale Fee, and Rahul Sarpeshkar,“ An Energy-Efficient Micropower Neural Recording Amplifier” IEEE transaction on biomedical circuits and systems JUNE 2007. [5]. Rui Martins, Siegfried Selberherr, and Francisco A. Vaz “A CMOS IC for portable EEG Acquisition Systems” IEEE transactions on instrumentation and measurement, vol. 47 no. 5 oct. 1998. [6]. [7]. [8]. Odilon de Oliveira Dutra, Tales C. Pimenta “Low power low noise neural amplifier with adjustable gain” IEEE pp. 2012. Achim Gratz “Operational Transconductance Amplifiers” http://Synth.Stromeko.net/diy/OTA.pdf [12]. Joseph J. Carr, “Introduction to Technology”. John Michael Brown. Biomedical Equipment Dr. Ahmad Khateb, “Step by step cadence manual and examples Schematic”. [13]. R. Jacob Baker “CMOS circuit design, layout and simulation” IEEE series on microelectronics systems. [14]. http://physionet.org/cgi-bin/atm/ATM. [15]. http://www.edaboard.com/thread179536.html. [16]. http://www.cadence.com. Brandon Romberg “cadence tool” West Virginia University. _______________________________________________________________________________________________ ISSN (Online): 2347-2820, Volume -2, Issue-5,6, 2014 69