Download A Detailed Model for a Thyristor Based Static Transfer Switch

1
A Detailed Model for a Thyristor Based Static
Transfer Switch
M.N. Moschakis, N.D. Hatziargyriou, Senior Member, IEEE
Abstract--Industrial customers often suffer from supply voltage
interruptions and sags due to the increase in the utilization of
sensitive equipment in the process automation and control. An
effective way to improve power quality and reliability of sensitive
customers is to use a Static Transfer Switch. This device enables a
very fast change in the supply of the customer to an alternate
feeder providing adequate power conditioning for several power
quality problems, such as voltage sags, swells and interruptions.
In this paper, an analytical model of STS is proposed and its
performance is verified using the ElectroMagnetic Transients for
DC(EMTDC) simulation package. Simulations using this model
are performed in order to handle voltage sags based on real
measurements on an actual industrial customer’s supply voltage.
Different phase angles and magnitudes of the two alternate source
pre-fault voltages and different fault instances are considered.
Index Terms—Bus transfer, power conditioning, power
quality, power system simulation, sensitive loads, static transfer
switch, voltage sags.
T
I. INTRODUCTION
he increasing sensitivity of consumer equipment, have
given rise to growing interest concerning the “quality" of
the electric power. Voltage sags of even low magnitude and
short duration can cause financial losses to industrial
customers due to process down-time, lost production, idle
work forces and other factors[1]. There is a growing need,
therefore, for power conditioning devices that will act very fast
resulting in mild voltage sags of minimum duration
experienced by the load. Many devices based on Power
Electronics Technology have been proposed and applied in
many cases where mitigation of voltage sags is needed. The
Static Transfer Switch(STS), the Dynamic Voltage
Restorer(DVR), the Distribution STAtic COMpensator
(DSTATCOM), the Static Var Compensator(SVC) and the
Solid State Tap Changer(SSTC) are the most used devices.
One of the most effective solutions from the aforementioned
is the Static Transfer Switch(STS). If an alternate feeder exists
or can be provided to the critical load at reasonable cost, STS
can transfer quickly enough the voltage supply to an alternate
source and sensitive load experiences only a shallow sag of
A Detailed Model for a Thyristor Based Static Transfer switch.
M. N. Moschakis is with the Department of Electrical and Computer
Engineering, National Technical University of Athens, Athens, Greece,
(e-mail: [email protected]).
N. D. Hatziargyriou is with the Department of Electrical and Computer
Engineering, National Technical University of Athens, Athens, Greece,
(e-mail: [email protected]).
short duration. Obviously, STS is not effective in the event of
a utility complete outage and cannot provide power
conditioning, if both feeders sag in voltage simultaneously, as
might be the case for a fault near the point where the two
feeders join[2].
The voltage sag magnitude(VSM) and duration(VSD) at the
load terminals, depend directly on the STS control scheme.
Hence, voltage detection and transfer need to be as fast as
possible. Furthermore, transfer and gating logic must assure
that in no case paralleling of the sources will occur, which
would cause severe damage to thyristor switches. Detection
and transfer schemes have already been proposed and
experimentally tested[4] under the assumption of almost zero
difference in phase angle and magnitude between preferred
and alternate source pre-fault voltages. The effect of fault type
and severity, the effect of regenerative loads on the transfer
time(TT), and the maximum transfer time, have also been
discussed[5]-[7], under the same assumptions.
In actual practice, however, two feeders can have a quite
large difference in voltage phase angles and a small difference
in magnitudes. In this paper, a voltage detection method and a
transfer strategy are proposed taking into account these
differences. STS performance at the terminals of an actual
industrial customer in Greece suffering from voltage sags, is
evaluated by simulations in EMTDC[11]. Real measurements
at the load supply voltage terminals are used to verify the
performance of the STS model. In every case studied,
minimum, maximum and average values of detection
time(DT), TT, VSM and VSD, are calculated.
II. STS STRUCTURE
A. Power circuit of the STS
The three-phase model of a STS is shown in Figure 1. It
consists of two thyristor blocks at the P(referred) and
A(lternate) source, which connect the load to the two alternate
sources. Each thyristor block is composed of three thyristor
modules corresponding to the three phases of the system. In
each thyristor module, two sets of thyristor switches are
connected in opposite directions, e.g. PP1/PN1 and AP1/AN1,
to allow the load current to flow in both positive and negative
directions. Mechanical bypass switches Pb and Ab are used in
parallel with the thyristor blocks A and P, respectively to
supply the load, even if the thyristor switches are out of
operation. Isolator switches M1p / M1a and M2p / M2a are
also used to isolate the thyristor blocks from the rest of the
2
system for maintenance of thyristor modules and test
purposes[4].
Fig. 1. Static transfer switch
B. Control circuit of the STS
The control circuit of the proposed STS is shown in Figure
2. It consists of two parts: the voltage detection circuit and the
commutation-gating circuit. The control circuit takes as input
the voltage magnitudes of the two feeders and performs a loadtransfer when needed. When a deviation from the pre-set limits
on the preferred source is detected, a transfer signal is
generated. Index 1shows that transfer to the alternate source is
effected, while index 0 shows transfer to the preferred source.
When the conditions for a safe commutation at each phase
separately are fulfilled, load is completely transferred to the
alternate source, until the voltage on the preferred source is
restored. For the transfer to the preferred source, current zerocrossing is only detected. The outputs of the control circuit are
the pulses for the preferred and alternate source thyristor
switches[4].
B1. Voltage detection strategy
The proposed voltage detection circuit is presented in
Figure 3. It is very simple and easy to implement and has been
proved to be very accurate and fast, even in the case of a
shallow sag.
The instant phase voltages are digitally sampled(sampling
frequency=10 kHz) and the rms value is calculated by squaring
and integrating the produced signal using the circuit shown in
Figure 3a. A second order transfer functions is used to enable a
fast response of the calculated rms voltage to any voltage
fluctuations, as shown in Figure 3b. By taking the minimum of
the three rms phase voltages, the response becomes even
faster. Next, the deviation from the preset reference
voltage(e.g. 1.0 pu) is compared to a tolerance limit(here it has
been set to 10%[11]). When the voltage on the preferred
source is within tolerance, control logic turns on the
corresponding thyristors. Power then can flow from the
preferred source to the load. If voltage deviates from the
tolerance limit, the control logic checks the voltage of the
alternate source. If the alternate source voltage is within
tolerance limits, the load is transferred to the alternate source,
otherwise, it does not issue any changes in the feeding source
of the load. When the voltage on the preferred source returns
to acceptable values, load is transferred back to the preferred
source after a time delay(a few cycles are enough) to ensure
that preferred source phase voltages are perfectly restored.
Fig. 3a. Rms meter
Fig. 3b. Voltage detection circuit configuration
Fig. 2. Control circuit configuration of the STS
3
B.2 Commutation and gating strategy
A fast and safe commutation of the preferred source
thyristor switches for every phase, depends directly on the
relative position and magnitude of three variables when a
voltage sag is detected:
1.
2.
3.
Preferred source instant phase voltage (e.g. Va_p(t) )
Alternate source instant phase voltage (e.g. Va_a(t) )
Preferred source instant line current (e.g. Ia_p(t) )
Subsequently, transfer time is directly related to the
following parameters:
•
•
•
•
•
•
•
The phase angle difference between the pre-fault phase
voltages of the two alternate sources. This may be
between 0 and 400 depending on the line impedance and
the active and reactive power transferred to the load.
The pre-fault voltage magnitude of the alternate source.
The load power factor, which determines the position of
the current with respect to the voltage on the preferred
source[7].
The severity of the fault which determines the value of the
instant voltage on the preferred source when a transfer
signal is initiated[7].
The phase angle jump the fault introduces.
The post-fault phase voltages, thus the type of the fault[7].
The instant at which the fault occurs[7].
Hence, the commutation from one source to another requires
some critical conditions to be fulfilled(Figure 2), in order to
enable fast transferring to alternate source and to avoid false
switching off of thyristor switches. This would lead to a cross
current flowing through an outgoing(incoming) thyristor of
one phase of the alternate source and through an
incoming(outgoing) thyristor of a corresponding phase of the
preferred source, which will feed the fault current[6].
Furthermore, turn-off time of thyristor switches is not constant
but depends on manufacturer’s specifications, voltage level,
natural conditions(e.g. temperature), reapplied dv/dt, reapplied
di/dt and gate bias during the turn-off interval[8]. This means
that a reverse voltage must be kept for a certain amount of time
in order to assure successful commutation of thyristor
switches.
Therefore, a transfer strategy which will take into account
the relative position and magnitude of corresponding instant
phase voltages of the two alternate sources and corresponding
instant line current on the preferred source, is needed.
Transferring does not always occur simultaneously for every
phase. Each phase has to wait for one of the following
conditions to become true in order to initiate transferring:
I. A) The three aforementioned variables are of the same sign
and
B) The instantaneous difference in absolute voltage
magnitude(e.g. |Va_p(t)| - |Va_a(t)|) is larger than a certain
limit ΔV1min, in order to give thyristor switch, which
conducts at that moment, enough time to turn off. An
example where condition A initiates transferring on phase a is depicted in Figure 4a. Fault occurs at t=0.028 s, transfer
signal is generated(voltage sag is detected) at t=0.032 s and
transferring(only for phase - a) is initiated at t=0.0325 s.
Thyristor PP1 is forced to turn off by turning on thyristor
AP1(figure 1). It can be seen that Deblock Signal
(dblk_altsrc_a), which enables firing pulses of alternate
phase –a thyristor switches, is delayed for a short time in
order to assure that voltage difference is within the preset
limit. Furthermore, as expected, the two instant phase
voltages become equal when alternate source phase –a
thyristor AP1 is fired, until thyristor PP1 is completely
turned-off. In this particular case, a smaller difference in
instantaneous voltages ( |Va_p(t)| - |Va_a(t)| ) might have
been able to lead to a safe commutation of thyristor switch.
However, in a different case (Figure 4b), this smaller
difference would lead to a high cross current because
thyristor switch PP1 would not have enough time to turn
off. Fault occurs at t=0.028 s and transfer signal as well as
transferring are initiated at t= 0.0295 s. Thyristor PP1 is
forced to turn off by turning on thyristor AP1(figure 1), but
given time is not enough. Eventually, PP1 does not turn off
and when AN1 is turned on, a large current(about 3 times
larger than in normal operation) flows from the alternate
source through AN1 and PP1 feeding the fault located
upwards the load on the preferred source. Hence, a certain
value in voltage difference needs to be applied in every
case to assure safe transferring.
II. A) If condition I-A is true but I-B is not, transfer logic
delays until line current(e.g. Ia_p(t) ) crosses zero, and
B) If ( |Va_p(t)| - |Va_a(t)| ) > 0 applies, initiates
transferring (Figure 5). Fault occurs at t=0.022 s, transfer
signal is generated at t=0.0277 s and transferring is
initiated at t=0.0296 s.
III. A) If II_B does not apply when line current(e.g. Ia_p(t) )
crosses zero but the three variables are of the same sign
transferring is issued when:
B) ( |Va_p(t)| - |Va_a(t)| ) > 0 for the first time(Figure 6).
Fault occurs at t=0.032 s, transfer signal is generated at
t=0.0337 s and transferring is initiated at t=0.0372 s.
IV. A) Another important case is the one shown in Figure 7.
Va_a(t) and Ia_p(t)) are of the same sign and Va_p(t) of
opposite sign, when a transfer signal is issued. In this case
transferring can be initiated to reduce transfer time, when:
B) |Va_p(t) - Va_a(t)| is larger than a preset value ΔV2min,
to assure successful commutation of thyristor PP1. Fault
occurs at t=0.027 s detected at t=0.0293 s. At that time,
Va_p(t) takes values of opposite sign with respect to
Va_a(t) and Ia_p(t) values. Furthermore, |Va_p(t) - Va_a(t)|
is larger than the preset value ΔV2min , so transferring can
be initiated. Obviously, if transferring was not issued at the
time shown in Figure 7, it could be done to satisfy condition
4
III approximately 3 ms later, as shown by the intersection of
the voltage waveforms at t=0.032 s.
Va_p
Va_p
+10
kV
Va_a
+20
-20 0.015
+0
0.015
0.01
0.02
0.025
0.03
0.035
0.04
Ia_a
0.035
0.04
0.045
0.04
0.045
Ia_a
+0
-0.2
+0.2
-0.4
+0
-0.2
0.015
Fault
0.02
0.015
0.02
0.025
0.015
0.01
0.02
0.025
0.03
0.035
0.035
dblk_altrsrc_a
+1
0.04
+0.5
dblk_altrsrc_a
Transfer Signal
Fault
0.03
Transfer Signal
+1.5
+1.5
+0
+1
-0.5
+0.5
0.025
0.03
0.035
0.04
0.045
Time (sec)
+0
-0.5
0.03
+0.2
kA
+0.4
-0.4
0.025
+0.4
Ia_p
kA
0.02
Ia_p
-10
-20
+0
-10
+10
kV
Va_a
+20
0.015
0.01
0.02
0.025
0.03
0.035
0.04
Time (sec)
Fig. 6. Instant phase voltages and line currents of phase -a for a voltage sag
where condition III initiates transferring.
Fig. 4a. Instant phase voltages and line currents of phase –a (for both
alternate sources), where condition I initiates transferring.
Va_p
V a_ p
+10
kV
+10
kV
+0
-10
+0
-20
-1 0
-2 0
0 .0 1 5Ia_ p
0 .0 2 5
0 .0 3 5 Ia_ a
+0.4
0 .0 5 5
0 .0 4 5
+1
0.02
0.025
0.03
Ia_p
0.035
0.04
0.045
0.04
0.045
Ia_a
+0
-0.2
+0
-0.4
-0 .5
+1.5
-1 0 .0 1 5
+ 1 .5
0 .0 3 5 d b lk_ altrsrc_ a 0 .0 4 5
T ran sfer S ign al 0 .0 2 5
0 .0 5 5
+0
-0.5
0.025
0.03
0.035
dblk_altrsrc_a
Transfer Signal
0.015
0.02
0.025
0.03
0.035
0.04
0.045
Time (sec)
+0
0 .5
0 .0 1 5
0 .0 2 5
0 .0 4 5
0 .0 3 5
T im e (sec )
0 .0 5 5
Fig. 4b. Instant phase voltages and line currents of phase -a where
commutation fails.
Va_p
Va_a
+10
+0
-10
-20 0.015
+0.4
0.02
Fault
+1
+1
+20
0.015
+0.5
+ 0 .5
kV
0.015
+0.2
kA
+ 0 .5
kA
Va_a
+20
V a_ a
+20
0.02
0.025
0.03
Ia_p
0.035
0.04
0.045
Ia_a
Fig. 7. Instant phase voltages and line currents of phase –a for a voltage sag
where condition IV initiates transferring.
When voltage on the preferred source returns to its
acceptable limits, another transfer is needed. To ensure that all
three phase voltages are completely restored, a short delay of
80 ms was introduced. When the transfer signal finally
becomes zero, all thyristors of alternate source side of the STS
are switched off immediately and thyristors of preferred source
side are switched on at the first zero current.
+0.2
kA
III.
+0
STUDY CASE
-0.2
-0.4
+1.5
0.015
0.02
0.025
0.03
0.035
Transfer Signal
Fault
0.04
0.045
dblk_altrsrc_a
+1
+0.5
+0
-0.5
0.015
0.02
0.025
0.03
0.035
0.04
0.045
Time (sec)
Fig. 5. Instant phase voltages and line currents of phase -a for a voltage sag
where condition II initiates transferring.
A. Power system configuration and measured events
To evaluate the performance of the proposed STS, an actual
case of a sensitive load(a papermill) was studied. The
installation of this consumer contains protection systems that
trip immediately after even shallow sags with only a short
duration. To investigate the frequency and characteristics of
voltage sags experienced by this load, measurements of
voltage sags were taken at the load terminals. These
measurements are used to validate in a more realistic way the
proposed model of the STS. Three characteristic sags are
presented in Table I.
5
TABLE I
VOLTAGE SAG MEASUREMENTS AT THE LOAD TERMINALS
(SAG MAGNITUDE : THE REMAINING VOLTAGE MAGNITUDE).
Va
Vb
Vc
+1.2
+1
+0.8
pu +0.6
+0.4
+0.2
+0 0
0.05
0.1
0.15
0.2
0.25
0.3
Time (sec)
Fig. 9b. Simulation results of the rms phase voltages at the load
terminals(Event 2).
Va
Vb
Vc
+1.2
+1
+0.8
A simplified single-phase diagram of the equivalent network
is shown in Figure 8. The critical load is fed by a 150/20 kV
substation. Fault is arbitrarily applied on the 150 kV side and
it is implemented using four switches to short-circuit the three
phases. The duration, in which every fault switch is on, varies
in order to obtain different sag duration per phase.
Furthermore, different values of resistors and inductors are
connected between phases to obtain different sag magnitude
for each phase.
pu +0.6
+0.4
+0.2
+0 0
0.05
0.1
0.15
0.2
Time (sec)
Fig. 9c. Simulation results of the rms phase voltages at the load
terminals(Event 3).
C. STS performance
In the following simulations, ΔV1min (condition I-B) and
ΔV2min (condition IV-B) are set to 0.6 pu and 0.35 pu(Base
phase voltage=11.54 kV), respectively. These values ensure
that no commutation failure occurs, as shown by a large
number of simulations. STS performance on each event taking
arbitrary initial conditions, is described below:
•
Fig. 8. Single-phase diagram of the simplified network.
B. Simulation results of the measured events
Voltage sag measurements shown in Table 1 were simulated
using EMTDC. The results are shown in Figures 9a, 9b and 9c.
+1.1
Va
Vb
Event 1
The simulation results regarding the behaviour of the
proposed model on the event 1, are depicted in Figures 10a, b,
and c. The event occurred at tfault = 13 ms, detected at tdet =
14.6 ms and transfer was completed at ttrnsfr = 24.2 ms. The
resulting sag magnitude was 71.13% and its duration was
18.78 ms. It must be noted that voltage on the alternate feeder
was set to lead voltage on the preferred feeder by 200 just
before the event occurred, and their magnitudes were:
Vpbef = 1.0 pu and Vabef = 0.95 pu .
RMS voltage with STS
Vc
+1.0
+1
+0.9
+0.9
pu +0.8
pu +0.8
+0.7
+0.7
+0.6
+0.5 0
RMS voltage without STS
+1.1
0.1
0.2
0.3
Time (sec)
0.4
0.5
0.6
0.7
Fig. 9a. Simulation results of the rms phase voltages at the load
terminals(Event 1).
+0.6
+0.5 0
0.1
0.2
0.3
Time (sec)
0.4
0.5
0.6
Fig. 10a. Rms voltages with and without STS(Event 1).
0.7
6
V a _p
V a _a
+20
RMS voltage with STS
+1.2
+ 10
kV +0
+1
-1 0
+0.8
-2 0 0
Ia _p
0.01
0.02
Ia _a
0.03
0.0 4
+ 0 .4
RMS voltage without STS
pu +0.6
+ 0 .2
+0.4
kA +0
+0.2
-0 .2
-0 .4
+0
0
+ 20
V b_p
0.01
0.02
V b_a
0.03
0.0 4
0
0.05
Va_p
0
+ 0 .4
Ib_p
0.01
0.02
Ib_a
0.03
+0
-2 0 0 .0 1
-0 .2
0 .0 2
Ia_ p
Ia_ a
0 .0 3
0 .0 4
0 .0 3
0 .0 4
0 .0 3
0 .0 4
0 .0 3
0 .0 4
0 .0 3
0 .0 4
0 .0 3
0 .0 4
+ 0 .4
0
+ 20
V c_p
0.01
0.02
V c_a
0.03
0.0 4
+ 0 .2
kA
+ 10
+0
-0 .2
kV +0
-0 .4
-1 0
0 .0 1
+ 20
0 Ic_p
0.01
0.02
Ic_a
0.03
0 .0 2
V b_ p
V b_ a
+ 10
0.0 4
kV
+ 0 .4
+0
-1 0
+ 0 .2
kA +0
-2 0
0 .0 1
+ 0 .4
-0 .2
-0 .4
Va_a
-1 0
+0
20
0.3
+ 10
kV
kA
-
0.25
+ 20
0.0 4
+ 0 .2
-0 .4
0.2
Fig. 11a. Rms voltages with and without STS(Event 2).
+0
-1 0
-2 0
0.15
Time (sec)
+ 10
kV
0.1
0
0.01
0.02
0 .0 2
Ib_ p
Ib_ a
+ 0 .2
0.03
0.0 4
T im e (se c)
kA
+0
-0 .2
Fig. 10b. Instant phase voltages and line currents in all phases of the two
alternate sources during the commutation(Event 1).
-0 .4 0 .0 1
0 .0 2
V c_ p
V c_ a
+ 20
+ 10
T ra n s fe r S ig n a l
C o m p le te T r a n s f e r to A lt. S o u r c e
kV
+ 1 .5
+0
-1 0
-2 0 0 .0 1
+ 1
0 .0 2
Ic_ p
Ic_ a
+ 0 .4
+ 0 .5
+ 0 .2
kA
+ 0
+0
-0 .2
-0 .5 0
0 .0 1
0 .0 2
T im e (s e c )
0 .0 3
0 .0 4
Fig. 10c. Signals indicating initiation of transfer procedure and completed
transferring to the alternate source(Event 1).
As it can be seen in Figure 10b, it was condition III that was
fulfilled and led to successful commutation in all three phases.
It is the nature of the fault and the phase angle jump it leads to,
together with the angle difference between the two feeders’
voltage, that makes condition III to be the most likely
condition to initiate commutation, no matter what are the
voltage magnitudes of the two feeders just before the fault and
the time at which fault occurred.
•
Event 2
The simulation results for the event 2, are shown on
Figures 11a, b, and c. The event occurred at tfault = 20 ms,
detected at tdet = 22.8 ms and transfer was completed at ttrnsfr =
24 ms. The resulting sag magnitude was 71.52% and its
duration was 12.06 ms. Voltage on the alternate feeder was set
to lag the voltage on the preferred feeder by 400 just before the
event occurred, and their magnitudes were: Vpbef = 1.0 pu and
Vabef = 1.0 pu .
-0 .4 0 .0 1
0 .0 2
T im e (se c)
Fig. 11b. Instant phase voltages and line currents in all phases of the two
alternate sources during the commutation(Event 2).
T r a n s f e r S ig n a l
C o m p le t e T r a n s f e r to A lt . S o u r c e
+ 1 .5
+1
+ 0 .5
+0
-0 .5
0
0 .0 1
0 .0 2
0.03
T im e ( s e c )
0 .0 4
0 .0 5
0 .0 6
Fig. 11c. Signals indicating initiation of transfer procedure and completed
transferring to the alternate source(Event 2).
In these simulations, different conditions initiated
commutation at each phase. On phase –a it was condition III,
on phase –b it was condition I and on phase –c it was
condition IV.
•
Event 3
The simulation results for the event 3, are presented on
Figures 12a, b, and c. The event occurred at tfault = 12 ms,
detected at tdet = 13.96 ms and transfer was completed at ttrnsfr
= 23.26 ms. The resulting sag magnitude was 83.73% and its
duration was 10.48 ms. Voltage on the alternate feeder was set
to lag the voltage on the preferred feeder by 200 just before the
event occurred, and their magnitudes were: Vpbef = 1.0 pu and
Vabef = 1.0 pu .
7
RMS voltage with STS
values (load power factor is considered constant and equal to
0.9) are:
RMS voltage without STS
+1.2
+1
+0.8
pu +0.6
1.
Instant at which fault occurred. The half-period of instant
voltage(preferred source phase –a instant voltage was
used as a reference) was divided into 20 equal intervals of
0.5 ms( 9 degrees), at which the fault was applied.
2.
Pre-fault rms voltage on the alternate feeder Vabef .
+0.4
+0.2
+0
0
0.05
0.1
0.15
0.2
Time (sec)
Fig. 12a. Rms voltages with and without STS(Event 3).
Va_p
+20
Va_a
3.
+10
kV
+0
-10
-200.01
Ia_p
0.015
0.02
0.025
Ia_a
0.03
0.035
0.04
+0.4
+0.2
kA
+0
-0.2
-0.40.01
Vb_p
0.015
0.02
0.025
0.015
0.02
0.025
0.015
0.02
0.025
0.015
0.02
0.025
0.015
0.02
Vb_a
0.03
0.035
0.04
0.03
0.035
0.04
0.03
0.035
0.04
0.03
0.035
0.04
0.03
0.035
0.04
+20
+10
kV
+0
-10
-200.01
Ib_p
Ib_a
+0.4
+0.2
kA
+0
-0.2
-0.40.01
+20
Vc_p
Vc_a
+10
kV
+0
-10
-200.01
Ic_p
Ic_a
+0.4
+0.2
kA
+0
-0.2
-0.40.01
0.025
Time (sec)
Fig. 12b. Instant phase voltages and line currents in all phases of the two
alternate sources during the commutation(Event 3).
T ra n s fe r S ig n a l
Voltage magnitude on preferred source was set to 1.0 pu
for all runs and voltage magnitude on alternate source was
1.0 or 0.95 pu.
Phase angle difference in the two sources voltage. Φp was
set to 00 and Φa was set to take a value between –400 and
400 with a step of 100.
Results based on all the combinations of the above
parameters (378 runs per event) are presented in Table II. The
minimum, maximum and average values are shown. Transfer
Time is the time between the detection time and complete
transferring(all three phases of the preferred source have
turned off and all phases of alternate source have turned on)
while Total-load Transfer Time(TLTT) represents the sum of
the Detection Time and Transfer Time. To assure that
commutation did not fail in any of those runs, maximum value
of the three instant line currents of preferred source is
measured for every run. A comparison between results in
Table II and voltage tolerance limits of various industrial
equipment shown in Table III[10], clearly shows that problems
should not be anticipated by the sag magnitude and duration
experienced by the load, when this STS is used. It should be
noted here that detection time is expected to be a few μs longer
in a real system, so VSM and VSD are expected to be a bit
lower and longer respectively.
TABLE II
SUMMARIZATION OF RESULTS BASED ON 378 RUNS PER EVENT
C o m p le te T r a n s fe r to A lt. S o u rc e
+ 1 .5
+1
+ 0 .5
+0
-0 .5
0 .0 1
0 .0 1 5
0 .0 2
0 .0 2 5
0 .0 3
0 .0 3 5
0 .0 4
T im e (s e c )
Fig. 12c. Signals indicating initiation of transfer procedure and completed
transferring to the alternate source(Event 3).
Figure 12b shows that condition II is responsible for
commutation at each phase. It can be concluded that either one
or a combination of the four conditions is likely to initiate
transferring for a particular event.
IV. INVESTIGATION ON THE STS PERFORMANCE
An investigation regarding the minimum, maximum and
average values of DT, TT, VSM and VSD, for each event, was
conducted by performing multiple runs in the EMTDC. The
parameters which affect STS performance and their possible
TABLE III.
VOLTAGE TOLERANCE LIMITS OF VARIOUS EQUIPMENT
PRESENTLY IN USE ACCORDING TO IEEE STD. 1346.
8
V. CONCLUSION
VIII. BIOGRAPHIES
In this paper, a detailed model of a Static Transfer Switch is
presented. A fast voltage detection strategy and a novel
transfer-gating scheme are proposed. All the conditions that
influence DT and TT and, consequently, VSM and VSD
experienced by the load, are described in detail. It is indicated
that to evaluate STS performance, all possible combinations of
pre-fault conditions, fault type and instant should be studied.
For these combinations, minimum, maximum and average
values of VSM and VSD need to be calculated. In the paper,
measurements of three unbalanced voltage sags at the
terminals of a sensitive load are used to demonstrate the
performance of the proposed STS model. It is shown that the
resulting VSM and VSD for these particular events, cannot
generate any problems to customers’ devices, according to
equipment voltage tolerance limits described at IEEE Std.
1346.
M. N. Moschakis was born in 1974. He received the Diploma in Electrical
Engineering from the National Technical University of Athens (NTUA), Greece,
in 1998. Currently he is a Ph.D student in NTUA. His scientific interests mainly
concern Custom Power Device Modeling and Evaluation, and Voltage Sag
Stochastic Assessment.
VI. REFERENCES
[1]
G. Reed, M. Takeda, I. Iyoda, S. Murakami, T. Aritsuka, K. Tokuhara,
“Improved Power Quality Solutions Using Advanced Solid-State
Switching and Static Compensation Technologies”, in Proc. 1999 IEEE
Power Engineering Society Winter Meeting,, vol. 2, pp. 1132-1137.
[2] J. Burke, D. Griffith, D. Ward, “Power Quality-Two Different
Perspectives”, IEEE Trans. Power Delivery, vol. 5, No.3, July 1990.
[3] J. Jippling, W. Carter, “Application and Experience with a 15 kV Static
Transfer Switch”, ”, IEEE Trans. Power Delivery, vol. 14, pp. 14771481, October 1999.
[4] H. Mokhtari, S. Dewan, M. Iravani., “Performance Evaluation of
Thyristor Based Static Transfer Switch”, IEEE Trans. Power Delivery,
vol. 15, pp. 960-966, July 2000.
[5] H. Mokhtari, S. Dewan, M. Iravani., “Effect of Regenerative Load on a
Static Transfer Switch Performance”, IEEE Trans. Power Delivery, vol.
16, pp. 619-624, October 2001.
[6] H. Mokhtari, S. Dewan, M. Iravani., “Benchmark Systems for Digital
Computer Simulation of a Static Transfer Switch”, IEEE Trans. Power
Delivery, vol. 16, pp. 724-731, October 2001.
[7] H. Mokhtari, S. Dewan, M. Iravani., “Analysis of a Static Transfer
Switch with respect to Transfer Time”, IEEE Trans. Power Delivery,
vol. 17, pp. 190-199, January 2002.
[8] B. Bose, Power Electronics and Ac Drives, Prentice Hall, 1986, p. 6.
[9] M. Bollen, Understanding Power Quality Problems: Voltage Sags and
Interruptions, IEEE Press Series on Power Engineering, P.M. Anderson
Series Editor, 2000, p. 255.
[10] Voltage characteristics of electricity supplied by public electricity
distribution networks, European Standard EN 50160, November 1994.
[11] PSCAD/EMTDC Power Systems Simulation Software Manual,
Manitoba HVDC Research Center, MB, Canada, 1997.
VII. ACKNOWLEDGMENT
This paper presents results from the project “Power Quality
Analysis and Improvement of the Greek Electricity
Distribution Networks”. The authors gratefully acknowledge
the financial support of the Public Power Corporation of
Greece and the contributions of Professors N. Vovos and G.
Giannakopoulos of University of Patras.
N. D. Hatziargyriou is Professor at Power Division of the Electrical
Engineering Department of NTUA. His research interests include Power
System Transient Analysis and Modeling. He is member of CIGRE SC38 and
currently Chairman of the IEEE Greek Power Chapter.