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Bruce Ohme and Mark R. Larson [email protected] Plymouth, MN USA Analog Component Development for 300°C Sensor Interface Applications HiTEC 2012 Geothermal Technologies Program Enhanced Geothermal Systems Acknowledgements This material is based upon work supported by the U.S. Department of Energy under, Golden Field Office, award number DE-EE0002574. Development Partners: Honeywell – Aerospace, Defense & Space – Redmond, WA Honeywell - Microelectronics & Precision Sensors, Plymouth, MN Applied Physics Systems, Mountain View, CA This report was prepared as an account of work sponsored by an agency of the United States Government. Neither the United States Government nor any agency thereof, nor any of their employees, makes any warranty, express or implied, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed, or represents that is use would not infringe privately owned rights. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise does not necessarily constitute or imply its endorsement, recommendation, or favoring by the United States Government or any agency thereof. HiTEC 2012 Page 2 300°C Directional Module Development • Orientation instrument for geothermal directional drilling - Orthogonally mounted sensors for gravity and magnetic vectors w 3 Flux-gate magnetometers + 3 Vibrating Beam Accelerometers (VBA) - 5 High-Temperature Co-fired Ceramic (HTCC) electronic boards w 3 VBA accelerometer hybrids, 1 Magnetometer hybrid, 1 System I/O hybrid - Logic-level frequency mode output for each sensor/axis Magnetometer Hybrid X Accelerometer & System I/O Hybrids Flux-Gate Sensors HiTEC 2012 Z&Y Accelerometer Hybrids Page 3 300°C SOI Electronics for the Directional Module • Active electronics needed for sensor interface, signal conditioning, and I/O • All electronics are high-temperature SOI • Using some 225°C catalog components - These have been verified for use at 300°C - (with de-rated life: 6 months vs. 5 yrs @ 225°C) 5V Linear Regulator, Quad Analog Switch, Dual Precision Operational Amplifier • Additional component requirements met by new design, multi-chip wafer fabrication New 300°C chips developed Stepped Pattern Detail Magnetometer Interface ASIC Dual / Quad Digital Buffer Dual Comparator Diode Bridge + Temp. Sensor Wide-bandwidth OpAmp: 3 ESD protection options HiTEC 2012 Page 4 HTSOI4 Technology (5V, 0.8m) Device characterization completed for 300°C simulation capability Ring Oscillator Del/Stage (ps)) vs. Temperature Extracted Netlist (C+CC) Measured Del/Stage (ps) SPECTRE TT Del/Stage (ps) SPECTRE FFFFF Del/Stage (ps) SPECTRE SSSSS Del/Stage (ps) Process Feature 450 444.58 400 399.58 Delay/Stage (ps) 350 336.31 302.13 300 272.1 271.53 250 Vtn/Vtp 25°C 250°C 300°C 1.2V / -1.3V 0.85V / - 1.0V 0.77V / -0.88V 230.1 220.9 206.72 200 Transistor “Off current” Nch, 250°C Pch, 250°C Simulation verified by ring-oscillator characterization: Nch, 300°C Pch, 300°C Timing error induced by models: <3% at 300°C # of metal layers CrSi Bridge R (Ω)) vs. Temperature Poly-silicon resistors Delta-R, 25°C to 300°C 189.1 186.11 159.39 157.12 150 Typical Characteristics 133.78 114.4 100 -100 -50 0 50 100 150 200 250 300 350 T (°C) 196000 194000 0.8 nA/micron width 0.5 nA/micron width 6.0 nA/micron width 4.5 nA/micron width 3 or 4 90 ohms per square +12% 192000 R (Ω) 190000 CrSiN resistors 2.5K ohms per square Delta-R, 25°C to 300°C -4% 188000 186000 184000 182000 180000 -100 -50 0 50 100 150 200 250 300 T (°C) CrSiN resistor: -55 °C to 300°C HiTEC 2012 350 Linear MOS Capacitor 670 angstroms, <150 ppm/Volt Page 5 Magnetometer Interface Overview • External X,Y,Z, flux-gate coils are driven in series in alternating polarity • External amplifiers/muxes balance flux-gate saturation timing for each polarity. The DC balance voltage is proportional to the external field • Voltage-to-Frequency Converters (VFC’s) convert the quasi-DC signal into a frequency output for transmission on the OM-300 connector/cable • A fourth channel transmits temperature sensed using an on-chip sensor VDDA 2.5V Output Saturation Sense Coils Coils x Reference POR Block 1.5V Output X-demod VDD POR Y-demod VIN_Y z Z-demod VIN_Z RESET Gen TESTCLK_EN OSC PTAT Current Source Output SYSCLK SYSCLK_B OUT_T QSVFC Quad VIN_X y RESET External OUT TESTCLK_IN RESET Synchronous Volt-to-Freq Converter OUT_X OUT_Y OUT_Z GATECLK Optional Resistor GATECLK_B Coil Driver ¸2 ¸2 Coil Oscillator / PLL EN_PLL Saturation detect HiTEC 2012 Page 6 Voltage-to-Frequency Converter Linearity Issue sVFC Input Topology Bias Current Source Test control 51pF Test Mux Vin 960K Vtest + 2.5V Reference Test-mode switch in signal path has a voltage dependent resistance, leading to non-linearity ‘VIN’ line (1.6u M1) Work-around/Correction: Use Focused-Ion-Beam (FIB) to deposit a “jumper” across the test switch HiTEC 2012 Page 7 OM-300 Mag ASIC: Typical SVFC Linearity • Data collected over a sample period defined by 800K SysClocks - 0V to 5V full-scale corresponds to 50K output count range sVFC Linearity with / without Focused Ion Beam Modification 4.0E-03 ENOB: 25C FIB’ed = 14.3 bits 300C FIB’ed = 13.4 bits 25C No FIB = 11.4 bits 300C No FIB = 10.4 bits Residual Non-linearity (Volts) 3.0E-03 2.0E-03 25C without FIB 300C without FIB 25C with FIB 300C with FIB 1.0E-03 0.0E+00 -1.0E-03 -2.0E-03 -3.0E-03 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Input Voltage (Volts) HiTEC 2012 Page 8 Other Magnetometer Interface ASIC Results Parameter (5V supply) Analog Quiescent Supply Current (No load) All required functionality has been verified by wafer-level probe testing at 300°C 2.5200 Buffered 2.5V Output 2.5150 1 2.5100 2 3 2.5050 Ave 4 2.5000 5 2.4950 6 2.4900 0 2.200 100 200 300 400 SYSCLK (MHz) 2.180 2.160 1 2.140 2 2.120 3 Ave 2.100 2.080 2.060 0 HiTEC 2012 50 100 150 200 250 300 350 2.5V Reference Output DC supply rejection DVout: ±15mA load 1.5V Reference Output 2.1MHz SYSCLK Output Frequency Max. Capacitive Load DFout: ±0.5V Vsupply Mag. Demod Clock Free-running Frequency (PLL not engaged) Coil Driver VOL @ 25mA sink VOH@ 25mA source Limit current (Level 1) Limit current (Level 2) Reset Generator Vsupply to Engage Vsupply to Release Hysteresis Synchronous V-to-F Output Linearity 0V to 5V range Temperature Channel Output Non-linearity 25C to 200C 25C to 300C 25°C 300°C 10.7 21.88 mA 2.496 74 .02 2.514 71 .05 Volts dB % 1.499 1.515 Volts 2.08 1.3 2.16 45 0.4 MHz pF % 17.45 26.81 KHz 0.35 4.77 26.6 39.6 0.55 4.73 28.4 42.0 Volts Volts mA mA 3.63 3.39 53 3.61 3.70 94 Volts Volts mV 14 13 Bits ±1 ±4 Units °C °C Page 9 Wide-band Opamp • Multiple instances on Accelerometer Circuit Card Assemblies (CCA’s) • In most instances OpAmp input is AC-coupled and biased near mid-rail - Input range and DC-offset are not critical • Parameters of most importance are: 1. 2. 3. 4. • Bias current generator based on delta-VGS mirror - 0.1x ESD Wide-Band Op Amp 0.1x ESD HiTEC 2012 Unity gain bandwidth Unity gain stability at circuit load conditions Noise density, esp. at 20KHz. Input current / Input current noise Uses N-channel devices biased at “ZeroTemperature-Coefficient” (ZTC) Bias current is » constant with temperature w Necessary to meet input range @ 300C w Band-width goes down at high temp. Page 10 ESD-Protect vs. Input Current / Input Current Noise Current into ESD Protect vs. Input Voltage & Temperature Wide-Band Opamp was designed in 3 versions 1. Standard ESD 2. 0.1x ESD 3. 0.01X ESD (last resort) Net Current Into ESD Protection Diode Network: - Increases with temperature - Minimized by biasing at mid-rail Tj = 175C ESD Protection: Noise Current Density (@20KHz) Tj = 225C Tj = 275C Best / Typical / Worst-case simulation: - Leakage/Noise increases with temperature - But, no benefit derived from mid-rail bias ‘high’ Take-Away: ESD protection comes at the expense of higher input current and higher input current noise HiTEC 2012 ‘typical’ ‘low’ Page 11 Wide-band Opamp DC Results All data @ 5V supplies Quiescent Supply Current (No load) DC Parameters Input Offset Voltage Input Bias Current, input at mid-rail Standard ESD 0.1X ESD 0.01X ESD Open-Loop Gain CMRR VSS Supply Rejection VDD Supply Rejection Common-mode Range Low High Max sourcing current for Vout =VDD-0.1V Max sinking current for Vout =VSS+0.1V HiTEC 2012 25°C 300°C Units 6.7 7.3 mA <1.02 <0.9 mV <5e-4 <5e-4 <5e-4 130 98 102 88 4.6 0.6 0.1 124 107 109 92 nA nA nA dB dB dB dB 0 3.3 69 87 0 4.2 50 49 V V mA mA Page 12 Wide-band Opamp AC Results +5V Gain= -1 Rin=Rout=1K 12pF load 2.5V Input from prior stage R2 Wide-Band Op Amp Output to next stage 100mV pk-pk square wave, Tr=Tf=10nSec. Ta=300C. Yellow=Vin, Green=Vout. 100ns/div C2 R1 AC Parameters: 1KOhm||15pF Load Unity Gain Bandwidth Phase Margin Gain Margin Slew Rate (rising) Slew Rate (falling) Open Loop Gain @20KHz 25°C 300°C Units 26.1 53 4.9 47 43 70.4 15.8 45 7.9 44* 42* 66.6 MHz Degrees dB V/msec V/msec dB *Slew-rate measured @ 275°C C1 (NPO) C1=0 WBOA Large-Signal Response: 300°C, 3 Volt Input Step 600 Input-referred noise voltage density 500 nV/root-Hz 400 25C 300 275C 200 C1=15pF 20KHz Noise Density: 6.4nV/rt-Hz @25C 9.5nV/rt-Hz@275C 100 0 1 HiTEC 2012 10 100 1,000 10,000 Frequency (Hz) 100,000 Page 13 Dual Comparator • Squares VBA frequency outputs to full CMOS logic levels • Built in hysteresis (Enabled/Disable) • Fast response for minimal skew/jitter of freq outputs. Input voltage range High Low Quiescent Supply Current Propagation Delay: Mid-rail input ±50mV 12pF load Hysteresis Enabled Rising Prop. Delay Falling Prop. Delay Hysteresis Disabled Rising Prop. Delay Falling Prop. Delay Hysteresis Magnitude HYS input pin high VOL/VOH VOL, Sinking 1.5mA VOH, Sourcing 1.5mA 25°C 300°C Units 3.6 0 1.21 3.98 0.14 1.35 Volts Volts mA 32 32 65 43 nsec nsec 16 16 29 24 nsec nsec 17 20 mV 0.13 4.81 0.29 4.74 V V HYS HiTEC 2012 Page 14 Diode Bridge and PTAT Current Source • (PTAT) current source : temperature sensor for system calibration • Diode bridge VBA drive limiter AVE 1 2 3 4 5 Linear (AVE) 100 PTAT Current Sourcey =Output vs. 0.174x + 38.711 Temperature Proportional-To Absolute-Temp (PTAT) Current Source 3mA Diode Bridge ~40uA @23C Micro-Amps 90 80 70 60 50 40 25 50 75 100 125 150 175 200 225 250 275 300 Degrees Centigrade HiTEC 2012 Page 15 Configurable Dual/Quad Digital Buffer • Configurable as Quad single ended or Dual Differential output - Configured via “MODE” input • Differential-mode output is 3V (minimum) into 120 Ω termination • Outputs can be tri-stated by control input (EN) Differential Output, 120 ohm load Yellow = IN Green = OUT Purple = OUTB 25°C MODE IN2 OUT2 OUT3/OUT2B IN3 VDD Configurable Digital Buffer: IN1 Quad Single-Ended OUT1/OUT0B or Dual Differential OUT0 120 Ω Line Driver With global output Enable IN0 EN HiTEC 2012 VDD VSS 300°C VSS Page 16 Summary and Conclusion • Simulation capability for an existing High-temperature SOI wafer process has been extended to 300°C • This has enabled successful design and verification of new components for 300°C application - Some of these are ubiquitous functions (such as the WBOA, Dual - Comparator, and Digital buffer) The Magnetometer Interface ASIC (MAGIF) contains sub-blocks that may re-used in other chips Honeywell High Temperature Website www.hightempsolutions.com Bruce Ohme [email protected] Plymouth, Minnesota USA HiTEC 2012 Page 17