Download cmos differential amplifier

CMOS DIFFERENTIAL
AMPLIFIER
INTRODUCTION
Three problems in single-transistor amplifier stages:
 Bias and gain sensitive to device parameters (µCox,VT );
sensitivity can be mitigated but often paying price in
performance or cost (gain, power, device area, etc.)
 Vulnerable to ground and power-supply noise (in dense IC’s
there is cross-talk, 60 Hz coupling, substrate noise, etc.)
 Many signal sources exhibit ”common-mode” drift that gets
amplified.
SOLUTION
Represent signal by difference between
two voltages:
Differential amplifier:
amplifies difference between two voltages
rejects components common to both voltages
DIFFERENTIAL AMPLIFIER definitions
 Common mode rejection ratio (CMRR)
AvD
CMRR 
AvC
 CMRR is a measure of how well the differential amplifier rejects the
common-mode input voltage in favor of the differential-input voltage.
 Input common-mode range (ICMR)
 The input common-mode range is the range of common-mode voltages
over which the differential amplifier continues to sense and amplify the
difference signal with the same gain.
 Typically, the ICMR is defined by the common-mode voltage range over
which all MOSFETs remain in the saturation region.
 Output offset voltage (VOS(out))
 The output offset voltage is the voltage which appears at the output of
the differential amplifier when the input terminals are connected together.
 Input offset voltage (VOS(in) = VOS)
 The input offset voltage is equal to the output offset voltage divided by
the differential voltage gain.
VOS 
VOS (out )
AvD
Why Differential?
 One of the most widely used analog block
High-performance mixed-signal circuits
 Outline:
Review of single-ended and differential operation
Description of basic differential pair
 Large signal and small signal analyses
Common Mode Rejection Ratio (CMRR)
 Concept, formulation
Diff pair with diode-connected and current-source
loads
Gilbert cell
Single-Ended and Differential Operation
 Single-ended
 Signal measured with respect to a fixed potential (e.g. gnd)
 Differential
 Signal measured btwn 2 nodes with equal and opposite
signal excursions around a fixed potential (see figure above)
 Dotted line -> common-mode level
SE & Diff - discussed
 Diff circuit more immune to noise
 e.g. Power Supply Noise
Single-Ended:
 Supply varies by DV  Vout changes by approx. same
amount
Differential (symmetric circuit)
 Noise on supply affects VX and VY, not VX-VY (Vout)
 High-Noise Immunity – rejects common signal (noise)
Advantages of Differential Circuit
 2 adjacent lines
 one carries small, sensitive signal
 one carries large clock waveform
 Capacitive coupling btwn L1 and L2
 Transitions on L2 corrupt signal on L1

Sensitive signal distributed as 2 equal
magnitude and opposite phases
 Clock placed midway, btwn the 2
 Clock transition disturbs differential
phases by equal amounts -> difference
intacts
 Diff output not corrupted -> rejects
common-mode noise
Another advantage of diff amp.
In a single CS amplifier, the maximum
swing is VDD-(VGS-VTH)
In a differential pair it can be shown
that the swing of VX-VY can reach
2[VDD-(VGS-VTH)].
Basic Differential Pair
 Amplify diff signal. Mechanism?
 Concept: incorporate two identical SE
signal paths to process the two phases
 The resulting circuit offers advantages
of diff signaling:
 e.g. High rejection of supply noise, high output swings, etc.
 What if input CM level changes?
 Bias currents of M1 and M2 changes -> vary gm of devices
(hence the gain) -> vary output CM level (lowers maximum
allowable output swings)
 Example: If input CM is excessively low (b):
 Min values of Vin1 and Vin2 may turn off M1 and M2
• Lead to severe clipping at output
 How to solve the problem?
Diff Pair (cont.)
 Add current source ISS
Makes ID1 + ID2 independent of
Vin,CM
ID1=ID2=ISS/2 when Vin1=Vin2,
output CM level = VDD-RDISS/2
 Main function:
suppress effect of input CM
level variations on operation of
M1 and M2, and output level
Diff Pair – Qualitative
Analysis
 Assume - < Vin1–Vin2<
 Case 1: Vin1 more –ve than Vin2
 M1 off, M2 on -> ID2=ISS
 Vout1 = VDD
 Vout2 = VDD – ISSRD2
 Case 2: As Vin1 brought closer to Vin2
 M1 gradually turns on
 Draws a fraction of ISS from RD1 (ISS=ID1+ID2), lowering Vout1
 Eventually, Vin1 more +ve than Vin2
 ISS flows through M1 (on), none through M2 (off)
 Vout2 = VDD
 Vout1 = VDD-ISSRD1
 See diagram above for the complete transition
Cont’d …
 2 important characteristics revealed from prev
analysis
Char 1: output’s maximum and minimum levels well-defined
(VDD and VDD-RDISS), independent of input CM level
Char 2: small-signal gain (slope of Vout1-Vout2 vs. Vin1-Vin2) is
maximum for Vin1=Vin2
 Gradually falling to zero as |Vin1-Vin2| increases
• i.e. circuit becomes more nonlinear as input voltage swing increases
• Circuit is in equilibrium when Vin1=Vin2
SMALL-SIGNAL DIFFERENTIAL
VOLTAGE GAIN
 For |ΔVin|≈0 (sufficiently small) we have:
| AV |
DVout
W
 Gm,max RD   nCox I SS RD  g m RD
DVin
L
where gm is that of a NMOS with a current of ISS/2
Single-ended Differential Voltage
Gain
AV , SE
gm
VX


RD
Vin1  Vin2
2
AV , SE
gm
VY


RD
Vin1  Vin2
2
Example
 What is the required input CM for which
RSS sustains 0.5 V?
 Calculate RD for a differential gain of 5
 What happens at the output if the input
CM level is 50 mV higher than the value
calculated in (a)?
 Let VDD=3V, (W/L)1=(W/L)2=25/0.5
 µnCOX=50µA/V2, VTH=0.6V, λ=0, γ=0, RSS=500Ω
NMOS Differential Amplifiers
Small Signal Analysis

g m  2 K (VGS  Vt )
 2 KI Q
  n C ox
W
(VGS  VT )
L

vod
Ad 
  g m RD
vid

Ac 
voc
 g m RD

vic 1 g m 2 RSS
Ad
CMRR 
Ac
Common-Mode Gains
 We have seen two
types of commonmode gain:
 AV,CM : Single-ended
output due to CM
signal.
 AV,CM-DM : Differential
output due to CM
signal.
AV ,CM
VX
VY


Vin,CM Vin,CM
AV ,CM  DM
VX  VY

Vin,CM
Common-Mode Rejection Ratio (CMRR)
Definitions
CMRR  CMRRSE
ADM
|
|
ACM
CMRR  CMRRdiff |
ADM
ACM  DM
|
In both cases we want CMRR to be as
large as possible, and it translates into
small matching errors and RSS as large as
possible
MOS Loads
(a) Diode-connected load
(b) Current-Source load
MOS Loads: Analysis Method
 Differential Analysis: Use half-circuit method,
with source node at virtual ground.
 Common-Mode Analysis: Again use half-circuit
method, with appropriate accommodation for
parallel transistors, and for RSS.
MOS Loads: Differential Gain Formulas
1
AV ,diff   g mN ( g mP
|| roN || roP )
g mN
 n (W / L) N


g mP
 p (W / L) P
AV ,diff   g mN (roN || roP )
Problems with Diode-connected MOS Loads
 Tradeoff among swing, gain and CM input range:
 In order to achieve high gain, (W/L)P must be
sufficiently low. Therefore PMOS overdrive voltage
must be sufficiently low. As a result CM signal range is
reduced.
Overcoming Diode-connected Load swing problem for
higher gains:
Use PMOS current sources which reduce gm of
diode-connected MOS, instead of lowering (W/L)P of
load. Gain can be increased by factor of 5.
Problems with Current-Source MOS Loads
In sub-micron technologies, it’s hard to
obtain differential gains higher than 1020.
Solution to low-gain problem: Cascoding
AV ,diff  g m1[( g m3ro 3ro1 ) || ( g m5 ro 5 ro 7 )]
Gilbert Cell
 Combine 2 properties of diff pair to
develop a versatile building block
Small-signal gain of diff pair = f(tail current)
2 transistors in a diff pair provides a means of steering tail
current to one of two destinations
 Variable Gain Amplifier (a)
Used in a system where signal amplitude may experience
large variations and requires inverse changes in gain
Vcont defines tail current hence the gain
 Max gain = f(voltage headroom limitations, device
dimensions)
Cont’d…
2 diff pairs that continuously vary gain from
a –ve to +ve value
Amplify inputs by opposite gains
A1=-gmRD, A2=gmRD, A1=f(Vcont1), A2=f(Vcont2)
A1 and A2 follows the changes in I1 and I2
How to combine the outputs into a single final
output?
Cont’d…
 Sum the 2 outputs
Produce Vout = Vout1 + Vout2 = A1Vin + A2Vin
 How to realize with transistors?
Note: Vout1=RDID1-RDID2
Vout2=RDID4-RDID3
\ Vout1+Vout2=RD(ID1+ID4)-RD(ID2+ID3)
 We don’t add voltages, but add currents by shorting the
corresponding drain terminals -> Isum generate output voltage
 e.g. I1=0, Vout=gmRDVin; I2=0 -> Vout=-gmRDVin; I1=I2 -> gain=0
To change amplifier gain monotonically, I1 and I2 must vary
in opposite directions
 HOW to change amplifier gain/vary the currents in opposite
directions?
Cont’d…
 Recall diff pair… yes, a diff pair
Observation:
 For large |Vcont11-Vcont2| all of tail current
steered to one of top diff pair
• Gain -> most positive or most negative value
 Redraw the circuit -> GILBERT CELL
 Note: Vin and Vcont are interchangeable
and still works as a VGA
VOU T  kVinVcont