Download Lecture 12: Gate Sizing

ELEC 7770
Advanced VLSI Design
Spring 2010
Gate Sizing
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10
Spring 2010, Mar 10
ELEC 7770: Advanced VLSI Design (Agrawal)
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Clock Distribution
clock
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Clock Power
Pclk
= CLVDD2f + CLVDD2f / λ + CLVDD2f / λ2 + . . .
stages – 1
= CLVDD2f Σ
n= 0
where CL =
λ =
1
─
λn
total load capacitance
constant fanout at each stage in distribution network
Clock consumes about 40% of total processor power.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Delay of a CMOS Gate
Intrinsic capacitance
Gate capacitance
CMOS
gate
Cint
Cg
CL
Propagation delay through the gate:
tp
= 0.69 Req(Cint + CL)
≈ 0.69 ReqCg(1 + CL /Cg)
= tp0(1 + CL /Cg)
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Req, Cg, Cint, and Width Sizing
 Req: equivalent resistance of “on” transistor,



proportional to L/W; scales as 1/S, S = sizing
factor
Cg: gate capacitance, proportional to CoxWL;
scales as S
Cint: intrinsic output capacitance ≈ Cg, for
submicron processes
tp0: intrinsic delay = 0.69ReqCg; independent of
sizing
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Effective Fan-out, f
 Effective fan-out is defined as the ratio
between the external load capacitance and
the input capacitance:
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f
=
CL/Cg
tp
=
tp0(1 + f )
ELEC 7770: Advanced VLSI Design (Agrawal)
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Sizing an Inverter Chain
1
2
Cg1
N
Cg2
CL
Cg2
= f2Cg1
tp1
= tp0 (1 + Cg2/Cg1)
tp2
= tp0 (1 + Cg3/Cg2)
N
tp
=
Σ tpj
j=1
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N
=
tp0
Σ (1 + Cgj+1/Cgj)
j=1
ELEC 7770: Advanced VLSI Design (Agrawal)
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Minimum Delay Sizing
Equate partial derivatives of tp with respect to Cgj to 0:
1/Cg1 – Cg3/Cg22 = 0, etc.
or Cg22 = Cg1×Cg3, etc. i.e., gate capacitance is geometric
mean of forward and backward gate capacitances.
Also, Cg2/Cg1 = Cg3/Cg2, etc. i.e., all stages are sized up by
the same factor f with respect to the preceding stage:
CL/Cg1 = F = fN, tp = Ntp0(1 + F1/N)
Spring 2010, Mar 10
ELEC 7770: Advanced VLSI Design (Agrawal)
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Minimum Delay Sizing
Equate partial derivatives of tp with respect to N to 0:
dNtp0(1 + F1/N)
───────── = 0
dN
i.e., F1/N – F1/N(ln F)/N = 0
or ln f = 1 → f = e = 2.7 and N = ln F
Spring 2010, Mar 10
ELEC 7770: Advanced VLSI Design (Agrawal)
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Sizing for Energy Minimization
Main idea: For a given circuit, reduce energy
consumption by reducing the supply voltage. This will
increase delay. Compensate the delay increase by
transistor sizing.
Ref: J. M. Rabaey, A. Chandrakasan and B. Nikolić,
Digital Integrated Circuits, Second Edition, Upper
Saddle River, New Jersey: Pearson Education, 2003,
Section 5.4.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Summary
 Device sizing combined with supply voltage



reduction reduces energy consumption.
For large fan-out energy reduction by a factor of
10 is possible.
An exception is F = 1 case, where the minimum
size device is also the most effective one.
Oversizing the devices increases energy
consumption.
Spring 2010, Mar 10
ELEC 7770: Advanced VLSI Design (Agrawal)
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