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The Structure of the CPU
The structure of the CPU
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At the top level, the computer consists of the CPU, memory and I/O
components
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These components are interconnected in some fashion to achieve the
basic function of the computer which is to execute programs
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Virtually all contemporary computers are based on an concepts
developed by John Von Neumann.
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The design is referred to as the Von Neumann Architecture
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It is based on 3 key concepts
1. Data and instructions are stored in a single read-write memory
2. The contents of these memory are addressable by location
3. Execution is in a sequential fashion from one instruction to the next
(unless explicitly specified otherwise)
The structure of the CPU
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The CPU hardware is designed to perform a finite set of
arithmetic and logic functions on input data e.g. add, compare,
store, read, multiply etc.
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The particular function that has to be performed is determined
by control signals.
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Hence control signals tell each component what it has to do
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Hence a program can be seen as a sequence of control
signals
Machine instructions are usually termed as opcodes
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An opcode can be viewed as representing on or more
control signals
The structure of the CPU
Data
Digital Electronic
Circuit
Results
Figure1: Hard Wired Program
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Figure one shows a digital electronic circuit that always does the
same thing on the data
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For instance if it is an addition circuit, the data can be two values
to be added, the output is the results of the addition
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This can also be seen as a program but it is a hardwired program
The structure of the CPU
Opode
Instruction interpreter
Control Signals
Data
Digital Electronic
Circuit
Results
Figure 2: Software Program
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Different opcodes lead to generation of control different signals
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What the Digital electronic circuit does with the data is determined by
the control signals
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The sequence of opcodes can be seen as a software program
The structure of the CPU
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The two components shown in figure 2 constitute the CPU
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The top component can be viewed as the control unit
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The lower component as the arithmetic and logic unit
Several other components are needed to yield a functioning
computer
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I/O Components
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Inputs components are for entering data into the system
and instructions
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Output components are for reporting the results of the
system
Main memory for storage of data and instructions
MAR
0
1
2
Instruction
...
PC
...
Main Memory
CPU
Instruction
IR
MBR
Instruction
I/O BR
I/O Module
Buffers
Data
Data
Data
Data
...
I/O AR
...
ALU
...
Instruction
n-2
n-1
System Bus
Figure 3: Main Computer Components
The structure of the CPU
Registers
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PC – Program counter
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IR – Instruction Register
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MAR – Memory Address Register
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MBR – Memory Buffer Register
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I/O AR – I/O Address register
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I/O BR – I/O Buffer Register
The structure of the CPU
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The CPU exchanges Data with memory
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To do this, it makes use of two internal registers
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MAR and MBR
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MAR specifies the location (Address) in memory from which data is to be
read or written
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MBR contains data to be written to memory or read from memory
To exchange data with I/O devices, the CPU uses two registers:
I/O AR and I/O BR
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I/O AR specifies the I/O device (by specifying an I/O address) of one of
the buffers
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I/O BR contains data to be read from an I/O buffer or to be written into
an I/O buffer specified by I/O BR
The structure of the CPU
•
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The PC (program counter) contains the address of the next instruction.
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This is the instruction that will be executed after the current instruction
is completed (unless the current instruction specifies a jump)
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Note the difference btn an instruction and the address of the instruction
The memory module consists of a set of memory locations
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These locations are identified by sequentially numbered addresses
Each location contains a binary number that can be interpreted as
either an instruction or data
Instruction Fetch and Execute
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The basic function of the computer is execution of a program
which consists of a set of instructions stored in memory
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In its simplest form, instruction processing consists of 2 steps
1. Fetch – The processor reads instructions from memory one
instruction at a time
2. Execution – instruction execution may involve several
operations. This will depend on the nature of the instruction
itself
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The processing required for a single instruction is called
instruction cycle
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The two steps are referred to as the fetch cycle and the execute
cycle
Instruction Fetch and Execute
Fetch Cycle
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At the beginning of each instruction cycle, the processor holds
the address of the next instruction to be fetched.
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This address is loaded into the MAR and the value in the PC is
incremented by 1
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For instance if the PC contains the value 300, the address
loaded in MAR is 300, and the value of PC becomes 301
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Placing of the address in MAR and activation of a read control
signal results in the value in memory address 300 being
transferred to AR via the MBR
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This completes the Fetch cycle.
Instruction Fetch and Execute
Fetch Cycle
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Assuming that instruction occupies a 16 bit word, then some bits
will be reserved for the opcode, and the other bits for the
address of the operand(s)
0
300
3 4
Opcode
15
Address
Figure 4: A memory word containing an instruction. We can have up to 16
unique opcodes and up to 212 unique memory addresses
0 1
+/-
15
Magnitude
Figure 5: A memory word containing an Integer
Instruction Fetch and Execute
Execute Cycle
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The opcode section of the instruction specifies the actions that are to
be performed
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These actions/operations fall in 4 categories
i.
Processor-Memory – data may be transferred from memory to
processor or processor to memory
ii.
Processor-I/I – Data may be transferred from I/O to processor or from
processor to I/O
iii. Data processing – The processor may perform some arithmetic or logic
operations on the data
iv. Control – e.g. a Jump instruction which specifies that the sequence of
execution to be altered
The Arithmetic and Logic Unit (ALU)
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The ALU It is the subsystem where all processing takes place in
the computer
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It has registers which are used for temporally storage of
information
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The information in the registers is worked on by the processing
components e.g. the adder
The Arithmetic and Logic Unit (ALU)
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The registers in the ALU have to hold all the information
processed by the computer
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In particular, they have to
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Accepts and hold the operands for the various arithmetic
and logic instructions that the machine can perform
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Hold and transmit the results of the operations
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The operands will generally be provided by the memory
unit
These will generally have to be sent to the memory unit
Retain intermediate results (from earlier operations) for use
in subsequent operations
The Arithmetic and Logic Unit (ALU)
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The registers will therefore need to be connected to each other;
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Connected to the units in the ALU that perform the
processing
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Connected to units outside the ALU
The following are the main units in the ALU
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MDR – Memory Data Register
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Accumulator Register - A
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Multiplier Quotient Register (MQ)
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The adder
The Arithmetic and Logic Unit (ALU)
MDR
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The only means of communication between the ALU and
memory
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Connected to the MBR
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Used as an intermediate stage in the transfer of data from
memory to any register in the ALU
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Used to hold the second operand for all binary operations
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Augend (the value that is added to) for addition
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Minuend (the value that is subtracted from) for subtraction
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Multiplier for multiplication
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Divisor for division
The Arithmetic and Logic Unit (ALU)
Accumulator
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Used for holding the first operand for binary operations
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Added (the value that is added) for addition
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Subtrahend (the value that is subtracted) for subtraction
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Multiplicand for multiplications
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Dividend for division
It also accepts the results for most arithmetic operations
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Sum for addition
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Difference for subtraction
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Part of the product for multiplication
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Remainder for division
The Arithmetic and Logic Unit (ALU)
Accumulator …
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The accumulator is a double rank register
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Main (lower rank) register
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Buffer (upper rank) register
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The output of the adder is connected to the buffer register
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The main register is connected to adder as one of the source of
inputs to the adder
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Hence the added can be held in the main register, and the
result (sum) stored in the buffer register
The Arithmetic and Logic Unit (ALU)
Accumulator …
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The accumulator is a shift register where numbers can be shifted right
or left, or scaled up or down
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Hence the ith bit is gated to bits: i , i-1 and i+1.
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Shifting involves copying the contents of the main register one bit into
the left or right in the buffer register, then copying the contents of the
buffer register into the main register
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i.e. shifting cannot be accomplished by merely copying bit i in main
register into bit i+1 in the main register because bit i might be replaced
by bit i-1 before it is copied into bit i+1
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In tandem with the MQ, it accumulates the product in multiplication,
and holds the dividend for division
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It retains the remainder at the end of the division operation
The Arithmetic and Logic Unit (ALU)
Multiplier Quotient
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Is also a double rank register
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It has a similar structure as the accumulator except that it is not
connected to the adder
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Independently, or in tandem with the accumulator, it can be
used to shift numbers to the left or to the right
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It is used to hold the multiplier
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Used together with the accumulator to hold the product in
multiplication, and hold the dividend in division
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In case of division, it is used to form the quotient
The Arithmetic and Logic Unit (ALU)
Shift Counter (SC)
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Keeps count of the number of shifts performed in case of shift
left, shift right, multiply and divide operations
Status Flip-flops
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overflow – set when there is an overflow during addition or
subtraction
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Divide fault – set if the divisor is not larger in magnitude than
the dividend
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Sign-compare – if the signs of the two operands in addition,
subtraction, multiplication and division are not the same
The Arithmetic and Logic Unit (ALU)
Adder and Logic Processor
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Used in all arithmetic and logic operations and performs the following
functions
1.
Accepts input from the MDR and the accumulator and supplies its
output (the sum or difference) to the Accumulator buffer
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This is necessary for addition, subtraction, multiplication and division
2.
Used for complementing numbers
3.
It has facilities for transferring carries from the less significant to the
more significant stages
4.
Has facilities for logical operations
Interconnection Structures
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A computer consists of components (Modules) of three basic
types
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Processor
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Memory
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I/O
These components need to communicate with each other
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Hence there must be pathways for connecting the
components
The collection of paths connecting the various components is
called the interconnection structure
Interconnection Structures
Forms of Input and Output for Each Module
1. Memory
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Typically consists of N words of equal length
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Each word is assigned a unique numerical address from 0 to N-1
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A word of data can be read or written into memory
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The nature of the operation is indicated by read and write
control signals
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The location of the operation is specified by an address
Note that there can be several memory modules
Interconnection Structures
Forms of Input and Output for Each Module
2. I/O module
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From an internal (computer) point of view, I/O functions in a similar
way to memory
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There are two operations: read and write
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An I/O module may control more than one external device
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We can refer to each of the interfaces to an external device as a port
and give each a unique address i.e. 0,1, …M-1
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An I/O module may be able to send interrupt signals to the processor
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The I/O module has data paths for communicating with the external
device it controls
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Note that there can be several I/O modules
Interconnection Structures
Forms of Input and Output for Each Module
3. Processor
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Reads in instructions and data
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Writes out data after processing
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Uses control signals to control the operations of the entire
system
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Receives interrupt signals
Interconnection Structures
Types of transfers
1. Memory to processor: the processors reads an instruction or unit of
data from memory
2. Processor to memory: the processor writes a unit of data to memory
3. I/O to processor: the processor reads data from an I/O device via an
I/O module
4. Processor to I/O: the processor sends data to an I/O device via an I/O
module
5. I/O to or From memory: An I/O module is allowed to exchange data
directly with memory without going through the processor using
direct memory access (DMA)
Interconnection Structures
CPU
Data Lines
Memory
I/O
Address Lines
Figure 6: Bus interconnection Scheme
...
I/O
Control Lines
Interconnection Structures
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A bus is a communication pathway connecting two or more
devices
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A key characteristic is that it is a shared transmission medium
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Only one device can transmit at a given time
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A bus typically consists of 50 to hundreds of separate lines
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The lines can be classified into three functional groups
1. Data lines
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Provide a pathway for moving data btn the modules
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collectively called the data bus
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May consist of 8 to hundreds of lines
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The number of lines is called the width of the data bus
Interconnection Structures
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The wider the data bus, the more the number of bits that can be sent
at once.
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For instance a bus with 8 lines will require two clock cycles to transfer
a data word of 16 bits
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Hence it has an effect on performance
2. The Address Lines (Address bus)
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Used to designate the source or destination of the data on the data
bus
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For instance, it the processor wishes to read the data in a given word
in memory, it puts the words address in the address bus
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The greater the width of the address bus, the more the number of
address we can access. Hence the width determines the maximum
possible memory capacity
Interconnection Structures
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The same lines are also used to address the I/O ports
3. The control lines
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Use to control the access to, and the use of the data and address lines
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Because the data and address lines are shared, there must be some form
of control of their use
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Control lines transmit both command and timing information btn the
system modules
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Timing signals indicate the validity of the data and address
information, command signals specify operations to be performed
Interconnection Structures
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Some control signals
i.
Memory write: Causes data on the bus to be written on the addressed
location
ii. Memory read: causes data on the addressed memory location to be
placed on the bus
iii. I/O write: causes data on the bus to be output on the addressed
memory port
iv. I/O read: causes data on the addressed I/O port to be placed on the
bus
v. Bus request: Indicates that a module needs to gain control of the bus
vi. Bus grant: indicates that the requesting module has been granted
control of the bus
Interconnection Structures
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Some control signals
vii. Interrupt request: indicates that an interrupt is pending
viii. Interrupt ACK: acknowledges that the pending interrupt has been
recognized
ix. Clock: used to synchronize operations
x. Reset: initialize all modules
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The operation of the bus is as follows:
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If one module wishes to send data to another, it must do two things
1) Obtain use of the bus
2) Transfer data via the bus
Interconnection Structures
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If one module wishes to request data from another module it must
1) Obtain use of the bus
2) Transfer the request to the other module via the appropriate control and
address lines
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It must then wait for the other module to send the data