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Lecture Notes
Insulated Gate Bipolar Transistors (IGBTs)
Outline
• Construction and I-V characteristics
• Physical operation
• Switching characteristics
• Limitations and safe operating area
• PSPICE simulation models
Copyright © by John Wiley & Sons 2003
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Multi-cell Structure of IGBT
• IGBT = insulated gate bipolar transistor.
Copyright © by John Wiley & Sons 2003
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Cross-section of IGBT Cell
• Cell structure similar to power MOSFET (VDMOS) cell.
• P-region at collector end unique feature of IGBT compared to MOSFET.
• Punch-through (PT) IGBT - N+ buffer layer present.
• Non-punch-through (NPT) IGBT - N+ buffer layer absent.
Copyright © by John Wiley & Sons 2003
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Cross-section of Trench-Gate IGBT Unit Cell
Emitter
boddy-source short
Oxide
N+
P
Parasitic
SCR
N+
Channel
P
length
Gate
conductor
I
N-
D
• Non-punch-thru IGBT
ID
P+
Collector
Emitter
boddy-source short
Oxide
N+
P
Parasitic
SCR
N+
Channel
P
length
Gate
conductor
I
N-
D
• Punch-thru IGBT
ID
N+
P+
Collector
Copyright © by John Wiley & Sons 2003
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IGBT I-V Characteristics and Circuit Symbols
• Transfer curve
• Output characteristics
collector
drain
• N-channel IGBT circuit symbols
gate
gate
source
emitter
Copyright © by John Wiley & Sons 2003
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Blocking (Off) State Operation of IGBT
• Blocking s ta t e ope rati on - V GE < V GE( t h)
• Jun cti on J2 is blocking ju nc t ion - n + drift
regi on ho lds dep let ion l ayer of bl ocking
junct ion.
• Wit hout N+ buf f er layer, IGBT has larg e
reverse blocking c apabil ity - s o-called
symm et ric IGBT
Copyright © by John Wiley & Sons 2003
• Wit h N+ buffer lay er, junct ion J1 has
small breakdownv olt age and t hus IGBT
has lit t le rev erse blocking capabilit y ant i-sy mmet ric IGBT
• Buffer lay er speeds up dev ice t urn-off
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IGBT On-state Operation
• MOSFET sect ion de signed
t o carry most of t he IGBT
collect or c urr ent
•
On-sta t e V CE( on) =
V J1 + V drif t + ICRchannel
•
Hole injec ti on int o drif t
regi on f rom J1 minimi ze s
V drif t .
Copyright © by John Wiley & Sons 2003
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Approximate Equivalent Circuits for IGBTs
drift region
res istance
V
V
gate
J1
drift
I R
C channel
• Approximate equivalent circuit for
IGBT valid for normal operating
conditions.
•
V CE( on) = V J1 + V drif t + I C Rchannel
Copyright © by John Wiley & Sons 2003
• IGBT equivalent circuit showing
transistors comprising the parasitic
thyristor.
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Static Latchup of IGBTs
• Lateral voltage drops, if too large, will forward bias junction J3.
• Parasitic npn BJT will be turned on, thus completing turn-on of parasitic thyristor.
• Large power dissipation in latchup will destroy IGBT unless terminated quickly.
External circuit must terminate latchup - no gate control in latchup.
Copyright © by John Wiley & Sons 2003
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Dynamic Latchup Mechanism in IGBTs
• MOSFET section turns off rapidly and depletion layer of junction J2 expands rapidly into
N- layer, the base region of the pnp BJT.
• Expansion of depletion layer reduces base width of pnp BJT and its a increases.
• More injected holes survive traversal of drift region and become “collected” at junction J2.
• Increased pnp BJT collector current increases lateral voltage drop in p-base of npn BJT and
latchup soon occurs.
• Manufacturers usually specify maximum allowable drain current on basis of dynamic
latchup.
Copyright © by John Wiley & Sons 2003
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Internal Capacitances Vs Spec Sheet Capacitances
C
C gc
G
bridge
C
+V b
Cce
C ge
C gc
E
Bridge balanced (Vb=0) Cbridge = C
G
C
G
gc = C res
C
Cies
E
C oes
Cies = C ge + C gc
E
C oes = C gc + Cce
Copyright © by John Wiley & Sons 2003
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IGBT Turn-on Waveforms
• Tur n-on wav efo rm s f or
IGBT embedded in a
step down converte r.
• Ve ry similar t o t ur n-on
wavef orms o f M OSFETs.
• Contr ibu t ions t o t vf 2 .
• Incr ease in Cge of
MOSFET sect ion a t lo w
collect or- emit t er
volt ages.
• Slo wer t urn -on of p np
BJT sect ion.
Copyright © by John Wiley & Sons 2003
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IGBT Turn-off Waveforms
• Turn-off wav eforms for IGBT
embedded in a st epdown
conv ert er.
• Current “ t ailing” ( t fi2 ) due t o
st ored charge t rapped in drift
region ( base of pnp BJT) by rapid
t urn-off of MOSFET sect ion.
• Short en t ailing int erv al by eit her
reducing carrier lifet ime or by
put t ing N+ buffer lay er adjacent t o
inject ing P+ lay er at drain.
Copyright © by John Wiley & Sons 2003
• Buffer lay er act s as a sink for
excess holes ot herwise t rapped
in drift region becasue lifet ime in
buffer lay er can be made small
wit hout effect ing on-st at e losses buffer lay er t hin compared t o drift
region.
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IGBT Safe Operating Area
• Maximum collector-emitter voltages
set by breakdown voltage of pnp
transistor 2500 v devices
available.
• Maximum collector current set
by latchup considerations - 100
A devices can conduct 1000 A
for 10 µsec and still turn-off via gate
control.
• Maximum junction temp. = 150 C.
• Manufacturer specifies a
maximum rate of increase of
re-applied collector-emitter voltage in
order to avoid latchup.
Copyright © by John Wiley & Sons 2003
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Development of PSpice IGBT Model
• Nonlinear capacitors Cdsj and Ccer due to N-P junction depletion layer.
•
•
•
•
•
• Reference - "An
Experimentally Verified
Nonlinear capacitor Cebj + Cebd due to P+N+ junction
IGBT Model
Implemented in the
MOSFET and PNP BJT are intrinsic (no parasitics) devices
SABER Circuit
Simulator", Allen R.
Nonlinear resistor Rb due to conductivity modulation of N - drain drift region of
Hefner, Jr. and Daniel
MOSFET portion.
M. Diebolt, IEEE Trans.
on Power Electronics,
Nonlinear capacitor Cgdj due to depletion region of drain-body junction (N-P junction). Vol. 9, No. 5, pp. 532542, (Sept., 1994)
Circuit model assumes that latchup does not occur and parasitic thyristor does not turn.
Copyright © by John Wiley & Sons 2003
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Parameter Estimation for PSpice IGBT Model
• Built-in IGBT model requires nine parameter values.
• Parameters described in Help files of Parts utility program.
• Parts utility program guides users through parameter estimation process.
• IGBT specification sheets provided by manufacturer provide sufficient
informaiton for general purpose simulations.
• Detailed accurate simulations, for example device dissipation studies, may
require the user to carefully characterize the selected IGBTs.
• Built-in model does not model
ultrafast IGBTs with buffer
layers (punch-through IGBTs) or
reverse free-wheeling diodes
Copyright © by John Wiley & Sons 2003
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PSpice IGBT - Simulation Vs Experiment
0V
5V
10 V
15 V
20 V
25 V
1
nF
Data from IXGH40N60 spec sheet
Simulated C GCversus V
0.75
nF
CE
for IXGH40N60
V
=0V
GE
0.5
nF
0.25
nF
0
100 V
200 V
300 V
400 V
500 V
Collector - emitter Voltage
Copyright © by John Wiley & Sons 2003
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