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1 Vol.4, Issue.4 Efficient Design of FIR Filter Using Computation Sharing Multiplier 1 A.R.V.P. Santosh Kumar, 2Dr. T.Venkata Ramana M.Tech Student, Dept of ECE, GITAM University, Visakhapatnam, AP-India 2 Associate Professor, Dept of ECE, GITAM University, Visakhapatnam, AP-India 1 disadvantage of using passive filters containing inductors is Abstract-- The of the present work presented inthis paper is to that they tend to be bulky. This is particularly true when they propose the novel idea of designing a programmable digital are designed to pass high currents, because large diameter finite impulse response (FIR) filter for high-performance and low-power applications. The implementation of the architecture wire has to be used for the windings and the core has to have sufficient volume to cope with the magnetic flux. Very uses a novel and efficient technique of computation sharing multiplier (CSHM) which specifically targets computation reuse in vector-scalar products and can be effectively used in the simple analog low pass or high pass filters can be constructed from resistor and capacitor (RC) networks. In the low pass case, a potential divider is formed from a series low complexity programmable FIR filter design. resistor followed by a shunt capacitor, as illustrated in Index Terms-- Computation sharing, dual transition skewed Figure 1. logic, programmable finite impulse response (FIR) filter. I. INTRODUCTION Filter is a frequency selective network. It passes a band of frequencies while attenuating the others. Filters are classified as analog and digital depending on nature of Fig.1: Basic topology of filter circuit inputs and outputs [1-5]. Filters are further classified as finite impulse response and infinite impulse response filters depending on impulse response. Analog filters can be passive or active. Passive filters use only resistors, capacitors, and inductors. Passive designs tend to be used where there is a requirement to pass significant direct current (about 1mA) through low pass or band stop filters. They are also used more in specialized applications, such as in high-frequency filters or where a large dynamic range is needed [3,4]. (Dynamic range is the difference between the background noise floor and the maximum signal level.) Also, passive filters do not consume any power, which is an advantage in some low-power systems. The main The filter input is at one end of the resistor and the output is at the point where the resistor and capacitor join. The RC filter works because the capacitor reactance reduces as the frequency increases. It should be remembered that the reactance is 90" out of phase with resistance. At low frequencies the reactance of the capacitor is very high and the output voltage is almost equal to the input, with virtually no phase difference [6-10]. At the cutoff frequency, the resistance and the capacitive reactance are equal and the filter's output is l / f i of the input voltage, or -3 dB. At this frequency the output will not be in phase with the input: it will lag by 45" due to the influence of the capacitive reactance. At frequencies above the 3 dB attenuation point, the output voltage will reduce further. The rate of attenuation will be 6 dB per doubling of frequency (per 2 Vol.4, Issue.4 octave). As the frequency rises, the capacitive reactance falls SELECT UNIT: The select unit is composed of SHIFTER, and the phase shift lag approaches 90". MUX, ISHIFTER, and AND gates. Since SHIFTER is directly connected to the coefficients, it does not lie on the II. COMPUTATION SHARING PROGRAMMABLE critical path. Static CMOS design with minimum size is used FIR FILTER for SHIFTER implementation. ISHIFTER lies on the critical CSHM is composed of a precomputer, select units and final path and the maximal shift width is 3 bits. A barrel shifter is adders (S&As) [11-16]. The precomputer performs the used since the signal has to pass through at most one multiplication of alphabets with input. Since alphabets are transmission gate in the barrel shifter. The MUX using pass- small bit sequences, the multiplication with input and transistor logic was implemented to achieve a compact and alphabets can be done without seriously compromising the high-speed design. performance. Once the multiplications of alphabets with input are calculated by the pre-computer, the outputs are shared by the entire S&As, which is the main advantage of CSHM. In order to cover every possible coefficient and perform general multiplication operation, we used eight alphabets in the pre-computer. PRE-COMPUTER: The multiplications performed by the pre-computer are simply implemented using the new carrySelect adder, which is proposed. S&As perform appropriate select/shift and add operations required to obtain the multiplication output. The select unit is composed of SHIFTER, MUX (8:1), ISHIFTER, and AND gate. To find the correct alphabet, SHIFTERs perform the right shift operation until they encounter 1 and send an appropriate select signal to MUXes (8:1). SHIFTERs also send the exact shifted values (shift signal) to ISHIFTERs. The MUXes Fig.2: Block diagram description of the model (8:1) select the correct answer among the eight precomputer outputs, ISHIFTERs simply inverse the operation performed FINAL ADDER: The final adder is the largest component by SHIFTERs (barrel shifter). When the coefficient input is in the S&A, which sums the outputs of four select units. The 0000, we cannot obtain a zero output with shifted value of carry-save array and the new carry-select adder presented the precomputer outputs. Simple AND gates are used to deal are used for high performance. As mentioned before, the with the zero (0000) coefficient input. The final adder adds input data is in two’s complement format, the coefficient in the outputs of the select units to obtain the final sign and magnitude, and the final adder output in two’s multiplication output. complement. 3 Vol.4, Issue.4 to various standard forms of inputs. FDA tool from The SELECT AND SHIFT SIGNAL FOR DIFFERENT COEFFICIENT INPUTS: MathWorks can generate a behavioral model and coefficient tables. Once a correct filter response has been determined The list representing the select and shift signal for different and coefficient inputs is given in the table 1 as follows. implementation can be carried out. Three choices of hardware architecture has been defined, the technology exist for the implementation of filter algorithms. Table 1.: Select and shift signal description These are: Programmable DSP chips ASICs FPGAs. At the heart of the filter algorithm is the multiplyaccumulate operation; Programmable DSP chips typically have only one MAC unit that can perform one MAC in less than a clock cycle. DSP processors are flexible, but they might not be fast enough. The reason is that the DSP processor is general purpose and has architecture that constantly requires instructions to be fetched, decoded and executed. ASICs can have multiple dedicated MACs that perform DSP functions in parallel. But, they have high cost for low volume production and the inability to make design modifications after production makes them less attractive. FPGAs have been praised for their ability to implement filters since the introduction of DSP savvy architectures, III. FIR IMPLEMENTATION USING which can be efficiently realized using dedicated DSP COMPUTATION SHARING MULTIPLIER Firstly we have to consider that one way to reach the solution of FIR filter design, proper choice of the implementation tools and techniques can save the designer a lot of work and time. MATLAB combines the high-level, mathematical language with an extensive set of pre-defined functions to assist in the creation and analysis of filter data. Toolbox are available for designing filter response and generating coefficient tables, each with varying levels of sophistication. Graphical filter design tools resources on these devices. More than 500 dedicated multiply-accumulate blocks are now available, making them exceptionally well suited for high-performance, high-order filtering applications that benefit from a parallel, nonresource shared hardware architecture. In this particular project, FPGA has been chosen as the implementation tool. To program FPGA, hardware description language is needed. VHDL synthesis offers an easy way to target a model towards different implementation. provide selections for specifying pass band, filter order, and design methods, as well as provide plots of the response of the filter Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI 4 Vol.4, Issue.4 digital signal processing (DSP) systems. One of the most computations are identified and those are shared without widely used operations in DSP is finite-impulse response additional memory area. This sharing property enables the (FIR) filtering. In the existing method FIR filter is designed computation sharing multiplier approach that achieves high using array multiplier, which is having higher delay and performance and low power in FIR filter implementation. power dissipation. The proposed method presents a On the other hand, Carry Look-ahead Adders (CLAs) are the programmable digital finite impulse response (FIR) filter for fastest adders (O (log (n) time), but they are the worst from high-performance applications. The architecture is based on the area point of view (O (log (n)) area). Carry Select a computation sharing multiplier (CSHM) which specifically Adders (CSAs) have been considered as a compromise doing add and shift operation and also targets computation solution between RCAs and CLAs (O (n) time and O (2n) re-use in vector-scalar products. CSHM multiplier can be area) because they offer a good tradeoff between the implemented by Carry Select Adder which is a high speed compact area of RCAs and the short delay of CLAs. As a adder. A Carry-Select Adder (CSA) can be implemented by result, some effort has been done to improve the efficiency using single ripple carry adder and add-one circuits using of this kind of adder. Due to the rapidly growing mobile the fast all-one finding circuit and low-delay multiplexers to industry, not only faster units but also smaller area and reduce the area and accelerate the speed of CSA. become major concerns for designing digitial circuits. The proposed method presents a programmable digital finite Adders are critical components of the ALU’s (Arithmetic impulse response (FIR) filter for high performance Logic Unit) or DSP (Digital Signal Processing) chips. applications. The FIR filter performs the weighted Therefore, high performance adders with low power summations of input sequences and is widely used in video consumption convolution functions, signal preconditioning, and various performance processing units. Several different types of high communication applications. Recently, due to the high- performance adder algorithms are available in literature. performance requirement and increasing complexity of DSP Among them Carry Select Adder (CSA) IS widely used for and multimedia communication applications, FIR filters with high speed operations. are essential for the design of high large filter taps are required to operate with high sampling rate, which makes the filtering operation very IV. RESULTS computationally intensive. The FIR filtering operation can be simplified to add and shift operations. Common sub Results pertaining to the model proposed in the previous expressions elimination and differential coefficients method section are presented in this section as follows. also explore low-complexity design of FIR filters by minimizing the number of additions in filtering operations. In the proposed FIR filter architecture, the Computation sharing multiplier (CSHM) is efficiently used for the lowcomplexity design of the FIR filter. The main idea of CSHM is to represent the multiplications in the FIR Filtering operations as a combination of add and shift operations over the common computation results. The common 5 Vol.4, Issue.4 VII. CONCLUSION The proposed model is verified and validated. the design of the proposed filter using the technique of computation sharing multiplier. The schematic representation presented in Fig.4 and Fig.5 are usefully describe the implementation of the FIR and RTL logics. The corresponding output waveforms are mentioned in the Fig.5. IX. REFERENCES [1] J. Park, H. Choo, K. Muhammad, and K. Roy, “Non-adaptive and adaptive filter implementation based on sharing multiplication,” in Proc. Fig 3.: Schematic description of FIR filter IEEE Int. Conf. Acoustics, Speech, and Signal Processing, June 2000, pp. 460–463. [2] J. M. Rabaey, Digital Integrated Circuits: A Design Perspective. Englewood Cliffs, NJ: Prentice-Hall, 1996. [3] H. Samueli, “An improved search algorithm for the design of multiplierless FIR filter with powers-of-two coefficients,” IEEE Trans. Circuits Syst., vol. 36, pp. 1044–1047, July 1989. [4] Y. C. Lim and S. R. Parker, “FIR filter design over a discrete powersof-two coefficient space,” IEEE Trans. Acoust., Speech Signal Processing, vol. ASSP-31, pp. 583–591, June 1983. [5]I.Hartley, “Subexpression sharing in filters using canonic signed digit multipliers,” IEEE Trans. Circuits Syst. II, vol. 43, pp. 677–688, Oct. 1996. [6] M. Potkonjak, M. Srivastava, and A. P. Chandrakasan, “Multiple constant multiplications: Efficient and versatile framework and algorithms Fig.4: Schematic of RTL for exploring common subexpression elimination,” IEEE Trans. ComputerAided Design, vol. 15, pp. 151–165, Feb. 1996. [7] N.Sankarayya, K.Roy, and D.Bhattacharya, “Algorithms for low power high speed FIR filter realization using differential coefficients,” IEEE Trans. Circuits Syst. II, vol. 44, pp. 488–497, June 1997. [8] K. Muhammad and K. Roy, “A graph theoretic approach for synthesizing very low-complexity high-speed digital filters,” IEEE Trans. Computer-Aided Design, vol. 21, pp. 204–216, Feb. 2002. [9] A. Solomatmikov, D. Somasekhar, N. Sirisantana, and K. Roy, “Skewed CMOS: Noise-tolerant high-performance low-power static circuit family,” IEEE Trans. VLSI Syst., vol. 10, pp. 469–476, Aug. 2002. [10] W. Jeong, K. Roy, and C. Koh, “High-performance low-power carryselect adder using dual transition skewed logic,” in Proc. ESSCIRC, 2001, pp. 172–175. Fig.5: Output waveforms 6 Vol.4, Issue.4 [11] G. Gerosa et al., “A 2.2-W 80-MHz superscalar RISC microprocessor,” IEEE J. Solid-State Circuits, vol. 29, pp. 1440–1452, Dec. 1994. [12] H.Partovietal., “Flow-through latch and edge-triggered flip-flop hybrid elements,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1996, pp. 138–139. [13] F. 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