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LTspice World Tour 2011 Apr 19 Orlando Jun 9 Los Angeles Apr 20 Atlanta Jun 10 San Diego Apr 21 Huntsville Jul 11 Shenzhen Apr 22 Dallas Jul 13 Wuhan May 10 Minnesota Jul 15 Beijing May 11 Chicago Jul 19 Pune May 12 Toronto Jul 20 Hyderabad May 13 Montreal Sep 26 Hanover May 17 Westford Sep 27 Düsseldorf May 18 Gaithersburg Sep 28 Stüttgart May 19 Mt. Laurel Sep 29 Vienna May 20 Melville Oct 3 Oslo Jun 7 Santa Barbara Oct 4 Copenhagen Jun 8 Irvine Oct 6 Helsinki Copyright © 2011 Linear Technology Corporation Oct 7 Stockholm Oct 10 Lyon Oct 11 Reading Oct 12 Cambridge Oct 13 Manchester Oct 17 Bologna Oct 18 Milano Oct 19 Zürich Oct 24 Tel Aviv Oct 25 Haifa Nov 15 Vancouver Nov 16 Seattle Nov 17 Boise Nov 18 Salt Lake City Nov 22 San Jose Time Line of SPICE Copyright © 2011 Linear Technology Corporation What Can LTspice Do for Me? • Simulate SMPS designs • General analog circuit simulation with an unlimited, high-performance SPICE Copyright © 2011 Linear Technology Corporation How to use LTspice IV Push the Run button. Click on what you want to plot. Copyright © 2011 Linear Technology Corporation Drafting Your Own Circuits • General Purpose Schematic Capture - Unlimited schematic size - Unlimited depth of hierarchy - Symbol editor - Complete documentation • Macromodels of over 1600 Linear Technology Products • Integrated with Industry Superlative SPICE Simulator - Unlimited, professional-quality SPICE proven for IC design - Unmatched combination of robustness, accuracy, speed and compatibility - Advanced analysis/simulation options, parameter sweeps, FFT’s, etc. - Run 3rd party models - Active independent users’ group Copyright © 2011 Linear Technology Corporation Installation Directory Structure Examples using LTspice as a general purpose SPICE program Model Test Jigs – one for each macromodeled Linear device Copyright © 2011 Linear Technology Corporation Additional Resources for Example Files • http://www.linear.com - Some products now feature an example LTspice schematic • http://groups.yahoo.com/group/LTspice • http://LTspice.linear.com/LTspiceWorldTour.zip Copyright © 2011 Linear Technology Corporation Waveform Display Features • Plot expressions of data assisted with cross probing - Cross probe voltages, device and port currents - Differential crossprobing - Dissipation expression composed by the schematic - Current in a “wire” - Dimensional analysis - Horizontal panning with the mouse tilt • Waveform average and RMS calculator • Fourier analysis (both .four statements and FFT's) • Dynamic waveform data compression • Multiple plot planes - Attached cursors ganged across plot panes • Eye diagrams • Complex data: Bode, Nyquist, and Cartesian • Parametric plotting (X-Y plotting) Copyright © 2011 Linear Technology Corporation What Usually Is Modeled? • Typical performance at room temperature • Error amp - Gm - Source/Sink Current • Oscillator - Frequency - Duty Cycle Limits • Switch logic • Switch current limit • Switch beta • Peak current vs error voltage • Slope compensation • Burst Mode • Switch minimum on time • Pulse skipping • PLL capture & phase lock Copyright © 2011 Linear Technology Corporation What Usually Is Not Modeled? • Production scatter • Behavior over temperature • Catastrophic failure modes • Oscillator SYNC pin(unless the device has a PLL) Copyright © 2011 Linear Technology Corporation What Can’t Be Counted on to Be Modeled or Not? • Iq in all modes • Misc features in shutdown Copyright © 2011 Linear Technology Corporation LT1533 Case Study • Voltage and current slew rate limiting • Complex control logic • External timing capacitor • Timing-cap current look-up table • Demo board available • Difficult to get efficiency analytically Copyright © 2011 Linear Technology Corporation Demo Board Schematic Copyright © 2011 Linear Technology Corporation Demo Board Copyright © 2011 Linear Technology Corporation The Bench Copyright © 2011 Linear Technology Corporation Minimum Slew Limits Vin = 5V Vout = +/-5V Iout = 28mA Copyright © 2011 Linear Technology Corporation With Voltage Slew Limit Vin = 5V Vout = ±5V Iout = 28mA Copyright © 2011 Linear Technology Corporation LT1533 Efficiency Comparison LTspice Demo Board Min. Slew Rate Limit 73.0% 73.0% With Current Slew Limit 66.0% 65.4% With Voltage Slew Limit 63.0% 62.0% Copyright © 2011 Linear Technology Corporation SMPS Stability or Open Loop Response From the Closed Loop System Copyright © 2011 Linear Technology Corporation LTspice IV Core Simulator • Floating point Math Is Random Access Memory Limited - 3GHz+ 300ps CPU cycle(Integer math at S-band frequencies) - 3 Latent clocks per double precision floating point addition, subtraction, or multiplication(19 digit math just above NATO Cband microwave frequencies). Division is slower and lands in the middle of the FM dial. - Cache offers random access to its contents. - RAM, as in the transistors plugged in as DIMMs/SIMMs on the motherboard, is not temporally random access. Access it with similar algorithms as you would a mechanical hard disk. • Rewrite Berkeley SPICE 3F4/5 for machines with faster CPU’s than RAM - Reduced address calculation and function calling overhead - Improved timestep control and numerical methods - Enhanced integration methods and convergence improvements Copyright © 2011 Linear Technology Corporation Benchmarking SPICE LTspice hspice¹ PSpice² ab_ac ab_integ ab_opamp arom astabl b330 bias bjtff bjtinv counter cram e1480 g1310 gm1 gm17 gm19 gm2 gm3 gm6 hussamp jge latch 4.750 0.109 5.454 3.656 1.046 2.172 3.234 2.453 7.594 7.234 0.625 0.188 3.969 5.562 2.703 11.968 1.125 3.453 5.109 0.781 33.875 0.969 14.63 0.17 7.72 3.34 5.21 1.90 8.63 2.94 14.28 7.40 0.74 0.09 5.45 11.14 2.92 9.37 3.21 8.13 11.84 1.42 9.08 2.42 7.59 .23 6.44 6.94 4.52 3.16 5.19 4.17 13.03 15.16 .91 (fails) 10.91 12.39 4.47 (fails) 4.91 8.66 13.45 (fails) (fails) 2.30 LTspice hspice PSpice loc 9.046 mike2 5.797 mosrect 9.734 mux8 6.531 nagle 0.672 nand 1.953 opampal 5.109 optrans 7.500 pump 0.016 rca 1.719 reg0 4.406 rich3 33.453 ring 5.562 ring11 2.360 schmitecl 0.015 schmitfast 8.297 schmitslow 10.781 slowlatch 0.156 todd3 0.156 toronto 5.031 vreg 0.735 WINS: 30 1] hspice is a Synopsis Trademark 2] PSpice is a Cadence Trademark Copyright © 2011 Linear Technology Corporation 10.64 21.39 29.14 11.91 1.53 2.45 4.50 3.14 0.49 1.45 28.78 4.67 19.36 4.72 0.06 29.09 37.28 0.11 0.06 11.72 2.86 10 8.86 37.83 17.22 12.00 1.28 1.08 1.41 6.17 .23 1.53 37.22 (fails) 10.33 3.11 .16 21.16 23.84 .22 .22 11.74 2.16 3 LTspice IV Core Simulator(Cont.) • Alternate solver/SPARSE matrix package optionally 1000x more accurate • Multi-threaded solver • Runtime Matrix compiler: - Macro assembler code generation(pseudo code) - Assemble pseudo code to native Intel object code - Dynamic link and execution of object code Copyright © 2011 Linear Technology Corporation LTspice IV Core Simulator(Cont.) • Added/Enhanced/Fixed every semiconductor device: - Fixed discontinuities and errors in the device Jacobians - Diode recombination current - JFET impact ionization current - BJT quasi-saturation - BJT Vcbo breakdown - Yang-Chatterjee charge model even for the archaic MOS levels 1, 2, and 3 - Binned MOSFET - VBIC - BSIM3v3.3.0 - BSIM4.6.1 - VDMOS(a new vertical double-diffused MOSFET for power MOS) - EKV 2.6 - BSIMSOI3.2 - Fowler-Nordheim diodes(EEPROMS) • Advanced Analog Behavioral Modeling Technology - Traditional ABM, specialized behavioral devices, HDL, co-simulation • Leadership in the SPICE community - Subcircuit port current monitoring - Unlimited output file size, i.e., >> 2GB Copyright © 2011 Linear Technology Corporation LTspice's Special Enhancements for SMPS Simulation • Automatic Steady State Detection and Efficiency Computation • VDMOS MOSFET Model • Node Reduction • Mixed-Mode Simulator with intrinsic SMPS controller functions • Nonlinear magnetics with gapped magnetic circuit solver(US Patent 7,502,723) Copyright © 2011 Linear Technology Corporation VDMOS MOSFET Normal Monolithic MOSFET (Used in IC’s) VDMOS (Discrete Power MOSFET) Source Source Gate Gate Drain Bulk(Substrate) Drain Drain-Source Current Path Copyright © 2011 Linear Technology Corporation LTC Proprietary VDMOS Model Replace a problematic subcircuit with a single new intrinsic SPICE device Copyright © 2011 Linear Technology Corporation VDMOS Gate Charge Behavior Copyright © 2011 Linear Technology Corporation And That’s Often Not Even the Worst of It! To get the charge correct: The I-V curve got botched: Copyright © 2011 Linear Technology Corporation SPICE Solver Overview Circuit to Simulate I D 1mA SPICE Solver Initial Solution Guess Newton-Raphson Iteration V[0] = 0V V[n] V[n+1] D I D I D I Linearize 1mA [G][V]=[I] 1mA G[n] I[n] Solve Matrix for Voltages 1mA Linearize About New Voltage Solution G[n] G[n+1] I[n] Copyright © 2011 Linear Technology Corporation I[n+1] G[n] I[n] Circuit Matrix Nodal analysis: [G][V] = [I] G: Conductivity matrix V: Unknown voltage vector I: Known current vector Modified Nodal analysis: [ G “1”] [v] = [I] [“1” R ] [i] = [V] G: Conductivity matrix v: Unknown voltage vector i: Unknown current vector V: Known voltage vector I: Known current vector • Node count is more important than part count. • It’s best to avoid floating voltage sources Copyright © 2011 Linear Technology Corporation Capacitor Companion Model Copyright © 2011 Linear Technology Corporation Inductor Companion Model Copyright © 2011 Linear Technology Corporation LTspice Behavioral Simulator • PSPICE style behavioral modeling - Legacy POLY() statements - Arbitrary expressions - Laplace - Look-up tables. • Arbitrary capacitance: write an expression for the charge. • Arbitrary inductor: write an expression for the flux. • An original mixed-mode simulator -- not xspice based. • Co-simulation for very complex models Copyright © 2011 Linear Technology Corporation Example Mixed-Mode Simulation Copyright © 2011 Linear Technology Corporation Mixed-Mode Simulator • Computationally lightweight • Tight feedback between analog and digital circuitry - Implemented as a mix of intrinsic SPICE devices and ~30 optimizing HDL compilers. - Predictors aid timestep control. • Easy to program so that models for new products are usually quick to be generated. Copyright © 2011 Linear Technology Corporation Two-Phase SMPS & PLL Capture Total elapsed time: 9.766 seconds. Copyright © 2011 Linear Technology Corporation Chan et al. Nonlinear Magnetics Extended per US Patent 7,502,723 A computationally lightweight model that uses only three parameters to specify the core’s major hysteresis loop: Hc: Coercive force [Amp-turns/meter] Br: Remnant Flux Density [Tesla] Bs: Saturation Flux Density [Tesla] Copyright © 2011 Linear Technology Corporation Gapped Core Magnetic Solver • Core physical dimensions specified with four parameters: Lm: Lg : A: N: Magnetic Length(excl. gap)[meter] Length of gap [meter] cross sectional area [meter**2] number of turns Copyright © 2011 Linear Technology Corporation SMPS Inductor Saturation Copyright © 2011 Linear Technology Corporation Core Saturation Considerations • • • • Saturation flux density goes down monotonically with temperature Maximum service temperature plus self-heating Controller peak current production scatter Startup/transient/short circuit conditions If you use the worst inductor that works in simulation, you will have failures over service temperature and production scatter. Copyright © 2011 Linear Technology Corporation Simulating Transformers Mutual coupling K-statement placed as a SPICE directive on the schematic Copyright © 2011 Linear Technology Corporation Multiple Windings = For N windings, the number of mutual couplings is Copyright © 2011 Linear Technology Corporation Misc. Advanced Features • Waveform plot annotations • Hierarchy - automatic symbol generation • BUS’s • Fast Access file format • .measure statements • Optional double precision data files • Read/Write .wav files • URL's in a .lib and .inc statements • Color Preference Editor • Programmable Keyboard Shortcuts Copyright © 2011 Linear Technology Corporation Misc. Advanced Techniques • User-defined parameters & functions • .step’ing a user-defined parameter - Overlay simulation runs - Parameter sweeps - Monte Carlo - Optimization - .step’ed .meas data can be plotted • Open loop response from closed loop system • Using the Universal Opamp Model • Adding 3rd party models Copyright © 2011 Linear Technology Corporation How Do I Add rd 3 Party Models? • .model Statements - supply parameters for the built-in device equations of native internal devices. - Common for diodes, bipolar’s, JFET’s and some MOSFET’s • .subckt Statements: Random Libraried Circuitry - define on schematic - explicitly .inc the model - program symbol to automatically include the required library - Automatic symbol generation! Copyright © 2011 Linear Technology Corporation Beware of OpAmp Models • Boyle Model • Noise Copyright © 2011 Linear Technology Corporation Common Pitfalls • Mirror & Rotate buttons greyed out • Hidden filename extensions/UAC • Start-up overshoot • Dissipation: RMS or Average? • Finding steady state Copyright © 2011 Linear Technology Corporation Manual Detection of Steady State 1) Execute Simulation=>Find Steady State 2) Immediately Execute Efficiency Calculation=>Mark Start 3) Repeat Efficiency Calculation=>Mark Start whenever you want to clear waveform history. 4) Execute Efficiency Calculation=>Mark Start again when Steady-State is reached. 5) Efficiency Calculation=>Mark End Copyright © 2011 Linear Technology Corporation Complete Help Documentation Copyright © 2011 Linear Technology Corporation Updates With Field Sync • Incrementally updates your installation off the web • Automatically merges databases of devices • Free Lifetime Updates Copyright © 2011 Linear Technology Corporation Thanks for Listening! Copyright © 2011 Linear Technology Corporation