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Lecture № 9
Addressing modes.
1. Structure of machinery instruction.
2. Definition of addressing mode. Operands in the
assembly.
3. Register addressing mode and list of registers,
used in this mode.
4. Direct addressing mode.
5. Direct memory addressing, types of prefixes and
their using.
6. Register indirect (base and index) addressing
mode.
7. Register indirect addressing mode with an offset
(base and index).
8. Base-index addressing mode. Base-index
addressing mode with an offset.
Literature.
1. Jurov V. Assembler, – SPb.: Piter, 2001. – 624 p.
2. Pustovarov V. I. Assembler. Programming and
analysis of machinery programs correctness, Kiev: “Irina”, 2000. - 476
3. Tanenbaum,
A.S.
Structured
Computer
th
Organization, 4 ed. - Upper Saddle River, NJ :
Prentice Hall, 2002.
Structure of machinery instruction.
Machinery instruction is a coded according certain rules
order (indication) to the microprocessor for executing
some operation or action.
Each instruction includes elements, which determine:
 what is to be done? (an answer to this question gives
an element, which is called Operation Code (OC) );
 objects, which are to be processed ( operands );
 how must be done? (these elements are types of
operands, which are usually given indirectly).
One byte
prefixes
7 6 5 4 3 2 1 0
Number of bytes
ss
index
base
Repetition
Size of address
Size of operand
Substitution of
segment
1 or 2
0 or 1
0 or 1
Operation
Code
Byte of
Addressing
Mode
(modr/m)
byte
sib
(OC)
Bus blocking
OC
7
6
5
4
2
1
0
7
6
5
w
4
3
2
OC
7
6
5
3
6
5
3
2
OC
7
6
5
6
5
mod
7
6
0
w
1
0
reg
4
OC
7
1
s
4
0
direct
operand
w
2
OC
7
1
d
4
0,1,2 or 4
offset
in the
instruction
OC
3
0,1,2 or 4
3
2
w
4
3
1
0
reg
2
1
0
Format of Machinery Instruction
reg/OC
5
4
r/m
3
2
1
0
The given format is general. Maximal length of
machinery instruction may be 15 bytes, but in reality
instructions are rather short, and they may include
only one field (Operation Code field) .
Let’s consider predestination of some of these
fields.
Prefixes are not compulsory elements of
machinery instruction, the length of each prefix is 1
byte. In the memory prefixes precede the
instruction. Predestination of prefixes consists in
modification of operations, executed by the
instruction. There are following types of prefixes:
 Prefix
of
segment
substitution
(exchange). In the direct form it points, which
register is used by the given instruction for
addressing: the stack or data. It undoes
(отменяет) the choice of segment register on
default. These prefixes have the following
meanings: 2eh – substitution of the segment
CS; 36h – substitution of segment SS; 3eh
substitution DS; 26h – substitution ES.
 Prefix of address capacity. It specifies the
capacity of address (16 or 32 width; in the real
address mode it is always 16 width ).
 Prefix of operand capacity. It is analogous
to the previous one but concerns an operand
width.
 Prefix of repetition. It is used for strings
processing.
Let’s consider a predestination of some fields:
 Operation Code. This is a compulsory element
for the operation description. There are many
instructions, to which several codes of operation
correspond; each of codes reflects specifications of
operation execution. Let’s consider one of variants:
Variant I. It is used for the majority of two-addresses instructions
Bits
7
6
5
4
3
2
OC
1
d
s
v
0
w
w
w
z
Bit 0
may be interpreted in two ways:
 Length (size) of operands: if w=1, then a word is processed; if w=0,
then a byte is processed.
 The meaning of flag ZF (when the repetition prefix is used).
Bit 1 may have three interpretations:
 To set a bit of the direction of information transfer (in this case the byte
of addressing mode must be present); if d=1, then r/m ===> reg, if
d=0, then r/m <===reg; the meaning of reg is determined from the next
table:
Reg
000
001
010
011
100
101
110
111
w=0
AL
CL
DL
BL
AH
CH
DH
BH
w=1
AX
CX
DX
BX
SP
BP
SI
DI
 Bit of the direct operand size: if s=1, then the size of operand is 8 bits;
if s=0, then size of operand is 16 bits.
 Bit, which determines a meaning of the counter in cycle (loop)
instructions: if v=1, then the meaning of the counter is in CL, if v=0, then
the meaning of the counter is equal to 1.
For example, in the listing of example program
Turbo Assembler
1
p0.asm
1
2
3
0000
0000
Version 4.1
B8 0000s
04/01/80 13:51:02
assume CS:CODE, DS:DATA
CODE segment
BEGIN:
mov AX,DATA
Page
4
5
6
0003
0005
0007
8E D8
0010
2E: 8B 16
mov
prfx dw 16
7
000C
8B DA
8
9
MSG
10
11
12
13
000E
0010
B4 09
BA 0000r
mov
0013
0015
0018
001A
CD 21
B8 4C00
CD 21
int
0005r
DS,AX
mov dx,prfx
mov bx,dx
CODE
int
ends
AH,
mov
09h
DX,
offset
21h
mov
21h
AX,
4C00h
let’s consider the 7-th string:
7
000C
8B
DA
mov bx,dx
OC
Byte of
Addressing Mode
It is clear, that we deal with two-addresses instruction. OC(Operation
Code)=8B, in binary scale of notation 8B = 1000 1011; w = 1 (a word is
processed); d = 1 (the register BX is a destination)
Bits
7
1
Operation Code
5
4
3
0
0
1
OC
6
0
2
0
1
1
d
0
1
w
Variant II. It is used for loading direct data in a register.
Bits
7
6
5
4
OC
3
w
2
1
reg
0
Example:
11
0015
B8
4C00
OC
Direct
operand
mov
AX,
4C00h
We deal with a direct addressing mode (the constant 4C00h
directly mounted in the machinery instruction);
OC = B8 = 1011 1000; w=1; reg = 000 =AX.
Bits
7
1
6
0
5
1
OC
4
1
3
1
w
2
0
1
0
reg
0
0
So, in this case we have all(full) information, concerned operands
addressing; in the variant I the second operand is a register(it must
be concretized), and it should be noted, that in the byte of OC
there is an information which is not sufficient for the operands
addressing.
When OC hasn’t got sufficient information for operands
addressing, the Byte of Addressing Mode must be present in the
instruction.
 Byte of Addressing Mode (modr/m). The
meaning of this byte determines the used form of
operands addresses. Operands may be located in
the memory, or in registers, if they are located in the
memory, then this byte determines components
(offset, base and index registers), which are used
for calculation of the effective (efficient) address.
The byte sib (Scale-Index-Base) is used in the
protected mode.
There are tree types of the Byte of Addressing
Mode:
1. For usual two-addresses instructions:
7
6
5
4
3
2
1
0
Bits
mod
reg
r/m
2. For instructions, which work with segment
registers:
7
6
5
4
3
2
1
0
Bits
mod
0
rs
r/m
3. For instructions, which work with the
secondary Operation Codes:
7
6
5
4
3
2
1
0
Bits
mod
Secondary OC
r/m
 The field mod (6-7 bits) determines the
addressing mode. This field is used jointly with
the field r/m: subject to the meaning of mod the
microprocessor discerns meanings of bits 0-2 .
For example, if mod = 00, it means that the field
offset in the instruction is absent, and in this
case the address of operand is determined by
content of base or (and) index register. If mod =
11, it means that there are no operands in the
memory, and they are stored in registers. The
field Secondary OC determines either register,
which is in the instruction on the place of the
second operand, or possible extension of OC.
As an example let’s consider the 7-th string once more:
7
000C
8B
OC
DA
mov bx,dx
Byte of
Addressing Mode (BAM)
DA =1101 1010
Bits
7
6
5
4
3
2
1
0
1
1
o
1
1
0
1
0
mod
reg
r/m
From the analysis of BAM it follows, that mod = 11
(register addressing), r/m = reg = 010 = DX, and
reg = BX = 011.
 The field index is used for storing a number of
the index register, which is necessary for
calculation of efficient address.
 The field base is used for storing the base
register, which is also necessary, as you know,
for calculation of efficient address of operand.
 The field of offset in the instruction is 8-th, 16th or 32-nd signed integer, which represents
partially or as a whole the meaning of the
operand’s efficient address.
 The field of direct operand, it represents 8-th,
16-th, or 32-nd direct operand.
Definition of addressing mode. Operands
in the assembly.
Def.1 The mode of addressing is a procedure of
searching operand(s) for the program execution.
If an instruction has got two operands, then for
each of operands must be given a mode of
addressing (these modes may be different).
Operands may be located in different places:
directly in the instruction’s code, in some of the
registers, in the memory cell (in the last situation
there are several possibilities of pointing out
operand’s address).
Strictly speaking, modes of addressing are
elements of microprocessor’s architecture, from one
point of view, so, as they reflect installed in it
possibilities of searching operands. But from the
other side, the modes of addressing are designated
by special manners in the Assembly language, and
from this point of view they may be considered as a
part of the language.
It should be noted, that the term “operand” is not
unique applying to programs, written in Assembly:
for the machinery instruction operands are those
data (binary digits) which it processes ( these data
may be in the registers or in the memory); for the
translator operands (but better to say parameters)
are those designations, which help it to find places
of location of the machinery operands. For example,
in the Assembly instruction
mov mem, Ax
operands (parameters) for the translator are
designations mem (designation of certain memory
cell) and AX (designation of concrete register); for
machinery instruction operands are contents of the
memory cell with a name mem and the register AX,
correspondingly.
Problems.
1. Describe the general structure of machinery
instruction.
2. Give a definition of addressing mode and
operands in the assembly.
3. What’s the register addressing mode. List
registers, used in this mode?
4. What’s the direct addressing mode?
5. What’s the direct memory addressing? List types
of prefixes and their using.
6. What’s the register indirect (base and index)
addressing mode?