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SUBJECT: ‘DIGITAL ELECTRONICS’ (B.Sc.-IT-2)
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Note:
This question-bank contains three sections.
Section-A contains 1 mark Multiple Choice Objective type questions.
Section-B contains 5 marks subjective questions.
Section-A contains 10 marks subjective questions.
SECTION-A
(1 MARK QUESTION)
OBJECTIVE TYPE QUESTION
Q1.
Draw the logic expression from the following diagram
1) C(A+B)DE
2) C+(AB)+DE
3) C+(A+B)DE
4) A+BCDE
Q2.
Applying De-Morgan's theorem to the expression
, we get ________.
1)
2)
3)
4)
Q3.
An AND gate with schematic "bubbles" on its inputs performs the same function as a(n)________ gate.
1) NOT
2) NOR
3) NOT
4) AND
Q4.
For the SOP expression
, how many 1s are in the truth table's output column?
1) 1
2) 2
3) 5
4) 3
Q5.
A truth table for the SOP expression
has how many input combinations?
1) 1
2) 2
3) 4
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SUBJECT: ‘DIGITAL ELECTRONICS’ (B.Sc.-IT-2)
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4) 8
Q6.
Determine the values of A, B, C, and D that make the product term
equal to 1.
1) A = 0, B = 1, C = 0, D = 1
2) A = 0, B = 0, C = 0, D = 1
3) A = 1, B = 1, C = 1, D = 1
4) A = 0, B = 0, C = 1, D = 0
Q7.
AC + ABC = AC
1) TRUE
2) FALSE
Q8.
The NAND or NOR gates are referred to as "universal" gates because either:
1) can be found in almost all digital circuits
2) can be used to build all the other types of gates
3) are used in all countries of the world
4) were the first gates to be integrated
Q9.
Applying the distributive law to the expression
, we get ________.
1)
2)
3)
4)
Q10.
Applying DeMorgan's theorem to the expression
, we get ________.
1)
2)
3)
4)
Q11.
Any number with an exponent of zero is equal to:
1) Zero
2) One
3) That number
4) ten
Q12.
In the decimal numbering system, what is the MSD?
1) The middle digit of a stream of numbers.
2) The digit to the right of the decimal point
3) The last digit on the right.
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SUBJECT: ‘DIGITAL ELECTRONICS’ (B.Sc.-IT-2)
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4) The digit with the most weight.
Q13.
Which of the following logical operations is represented by the + sign in Boolean algebra?
1) Inversion
2) AND
3) OR
4) complementation
Q14.
Output will be a LOW for any case when one or more inputs are zero for a(n):
1) OR gate
2) NOT gate
3) AND gate
4) NOR gate
Q15.
The output of a NOR gate is HIGH if ________.
1) All inputs are HIGH.
2) Any input is HIGH.
3) Any input is LOW.
4) All inputs are LOW.
Q16.
The Boolean expression for a 3-input AND gate is ________.
1) X = AB
2) X = ABC
3) X = A + B + C
4) X = AB + C
Q17.
The output of a NOT gate is HIGH when ________.
1) the input is LOW
2) the input is HIGH
3) power is applied to the gate's IC
4) power is removed from the gate's IC
Q18.
If the input to a NOT gate is A and the output is X, then ________.
1) X = A
2)
3) X = 0
4) none of the above
Q19.
What is the Boolean expression for a three-input AND gate?
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Ph. 0175-2205100, 2215100
SUBJECT: ‘DIGITAL ELECTRONICS’ (B.Sc.-IT-2)
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1) X = A + B + C
2) X = A BC
3) A – B – C
4) A $ B $ C
Q20.
Which of the following gates has the exact inverse output of the OR gate for all possible input
combinations?
1) NOR
2) NOT
3) NAND
4) AND
Q21.
The output of an exclusive-OR gate is HIGH if ________.
1) all inputs are LOW
2) all inputs are HIGH
3) the inputs are unequal
4) none of the above
Q22.
A 2-input NOR gate is equivalent to a ________.
1) negative-OR gate
2) negative-AND gate
3) negative-NAND gate
4) none of the above
Q23.
What is the Boolean expression for a four-input OR gate?
1) Y = A + B + C + D
2) Y = A B  C  D
3) Y = A – B – C – D
4) Y = A $ B $ C $ D
Q24.
Which of the following is not a basic Boolean operation?
1) OR
2) NOT
3) AND
4) FOR
Q25.
The basic logic gate whose output is the complement of the input is the:
1) OR gate
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SUBJECT: ‘DIGITAL ELECTRONICS’ (B.Sc.-IT-2)
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2) AND gate
3) Inverter
4) comparator
Q26.
How many entries would a truth table for a four-input NAND gate have?
1) 2
2) 8
3) 16
4) 32
Q27.
The logic gate that will have a LOW output when any one of its inputs is HIGH is the:
1) NAND gate
2) AND gate
3) NOR gate
4) OR gate
Q28.
The output of a NAND gate is LOW if ________.
1) all inputs are LOW
2) all inputs are HIGH
3) any input is LOW
4) any input is HIGH
Q29.
The Boolean expression for a 3-input OR gate is ________.
1) X = A + B
2) X = A + B + C
3) X = ABC
4) X = A + BC
Q30.
From the truth table for a three-input NOR gate, what is the only condition of inputs A, B, and C that
will make the output X high?
1) A = 1, B = 1, C = 1
2) A = 1, B = 0, C = 0
3) A = 0, B = 0, C = 1
4) A = 0, B = 0, C = 0
Q31.
A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is a(n):
1) Ex-NOR gate
2) OR gate
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Ph. 0175-2205100, 2215100
SUBJECT: ‘DIGITAL ELECTRONICS’ (B.Sc.-IT-2)
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3) Ex-OR gate
4) NAND gate
Q32.
Identify the type of gate below from the equation
1) Ex-NOR gate
2) OR gate
3) Ex-OR gate
4) NAND gate
Q33.
Which type of gate can be used to add two bits?
1) Ex-OR
2) Ex-NOR
3) Ex-NAND
4) NOR
Q34.
Why is an exclusive-NOR gate also called an equality gate?
1) The output is false if the inputs are equal.
2) The output is true if the inputs are opposite.
3) The output is true if the inputs are equal.
Q35.
The Ex-NOR is sometimes called the ________.
1) parity gate
2) equality gate
3) inverted OR
4) parity gate or the equality gate
Q36.
A logic circuit that provides a HIGH output if one input or the other input, but not both, is HIGH, is
a(n):
1) Ex-NOR gate
2) OR gate
3) Ex-OR gate
4) NAND gate
Q37.
Which of the figures (a to d) is the De-Morgan equivalent of Figure
(e)?
1) a
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2) b
3) c
4) d
Q38.
Which of the examples below expresses the distributive law?
1) (A + B) + C = A + (B + C)
2) A(B + C) = AB + AC
3) A + (B + C) = AB + AC
4) A(BC) = (AB) + C
Q39.
Which of the examples below expresses the associative law of addition:
1) A + (B + C) = (A + B) + C
2) A + (B + C) = A + (BC)
3) A(BC) = (AB) + C
4) ABC = A + B + C
Q40.
Which logic gate does this truth table describe?
1) AND
2) OR
3) NAND
4) NOR
Q41.
Which of the figures given below represents a NAND gate?
1) a
2) b
3) c
4) d
Q42.
A NAND gate has:
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1) active-LOW inputs and an active-HIGH output.
2) active-LOW inputs and an active-LOW output.
3) active-HIGH inputs and an active-HIGH output.
4) active-HIGH inputs and an active-LOW output.
Q43.
Which of the following is a form of DeMorgan's theorem?
1)
2)
3)
4)
Q44.
The Boolean equation for a NOR function is:
1)
2)
3)
4)
Q45.
Which step in this reduction process is using DeMorgan's theorem?
1) STEP 1
2) STEP 2
3) STEP 3
4) STEP 4
Q46.
Simplify the expression
using DeMorgan's theorems.
1)
2)
3)
4)
Q47.
How many 3-line-to-8-line decoders are required for a 1-of-32 decoder?
1) 1
2) 2
3) 4
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Ph. 0175-2205100, 2215100
SUBJECT: ‘DIGITAL ELECTRONICS’ (B.Sc.-IT-2)
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4) 8
Q48.
Which of the figures shown below represents the exclusive-NOR
gate
1) a
2) b
3) c
4) d
Q49.
Convert BCD 0001 0010 0110 to binary.
1) 1111110
2) 1111101
3) 1111000
4) 1111111
Q50.
Convert BCD 0001 0111 to binary.
1) 10101
2) 10010
3) 10001
4) 11000
Q51.
How many data select lines are required for selecting eight inputs?
1) 1
2) 2
3) 3
4) 4
Q52.
The simplest equation which implements the K-map shown below is:
1)
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SUBJECT: ‘DIGITAL ELECTRONICS’ (B.Sc.-IT-2)
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2)
3)
4)
Q53.
How many 1-of-16 decoders are required for decoding a 7-bit binary number?
1) 5
2) 6
3) 7
4) 8
Q54.
Which of the following logic expressions represents the logic diagram shown?
1)
2)
3)
4)
Q55.
Which of the following combinations cannot be combined into K-map groups?
1) Corners in the same row
2) Corners in the same row
3) Diagonal corners
4) Overlapping combinations
Q56.
Which gate is best used as a basic comparator?
1) NOR
2) OR
3) Exclusive-OR
4) AND
Q57.
The device shown here is most likely a ________.
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Ph. 0175-2205100, 2215100
SUBJECT: ‘DIGITAL ELECTRONICS’ (B.Sc.-IT-2)
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1) Comparator
2) Multiplexer
3) Demultiplexer
4) parity generator
Q58.
A decoder can be used as a demultiplexer by ________.
1) tying all enable pins LOW
2) tying all data-select lines LOW
3) tying all data-select lines HIGH
4) using the input lines for data selection and an enable line for data input
Q59.
Solve the network in the figure given below for X.
1) A + BC + D
2) ((A + B)C) + D
3) D(A + B + C)
4) (AC + BC)D
Q60.
What type of logic circuit is represented by the figure shown below?
1) XOR
2) XNOR
3) XAND
4) XNAND
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Ph. 0175-2205100, 2215100
SUBJECT: ‘DIGITAL ELECTRONICS’ (B.Sc.-IT-2)
Q61.
Page 12 of 55
The device shown here is most likely a ________.
1) Comparator
2) Multiplexer
3) Demultiplexer
4) parity generator
Q62.
Solve this BCD problem: 0100 + 0110 =
1) 00010000BCD
2) 00010111BCD
3) 00001011BCD
4) 00010011BCD
Q63.
Add the following hexadecimal numbers.
3C
+25
Q65.
14
+28
3B
+DC
1) 60
3C
116
2) 62
3C
118
3) 61
3C
117
4) 61
3D
117
The most commonly used system for representing signed binary numbers is the:
1) 2's-complement system.
2) 1's-complement system.
3) 10's-complement system.
4) Sign-magnitude system.
Q66.
The decimal value for E16 is:
1) 1210
2) 1310
3) 1410
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4) 1510
Q67.
Add the following hex numbers: 011016 + 1001016
1) 1012016
2) 1002016
3) 1112016
4) 0012016
Q68.
The binary subtraction 0 – 0 =
1) difference = 0
borrow = 0
2) difference = 1
borrow = 0
3) difference = 1
borrow = 1
4) difference = 0
borrow = 1
Q69.
Convert each of the decimal numbers to 8-bit two's-complement form and then perform subtraction
by taking the two's-complement and adding.
1) 0001 0011
2) 0000 1110
3) 0010 1110
4) 1110 0000
Q70.
Adding in binary, a decimal 26 + 27 will produce a sum of:
1) 111010
2) 110110
3) 110101
4) 101011
Q71.
How many inputs must a full-adder have?
1) 4
2) 2
3) 5
4) 3
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Ph. 0175-2205100, 2215100
SUBJECT: ‘DIGITAL ELECTRONICS’ (B.Sc.-IT-2)
Q72.
Page 14 of 55
Solve this binary problem: 01110010 – 01001000 =
1) 00011010
2) 00101010
3) 01110010
4) 00111100
Q73.
Solve this binary problem:
1) 1001
2) 0110
3) 0111
4) 0101
Q74.
A full-adder adds ________.
1) two single bits and one carry bit
2) two 2-bit binary numbers
3) two 4-bit binary numbers
4) two 2-bit numbers and one carry bit
Q75.
How many outputs must a full-adder have?
1) 2
2) 3
3) 4
4) 5
Q76.
Convert each of the decimal numbers to two's-complement form and perform the addition in binary.
+13
add –7
Q78.
–10
add +15
1) 0001 0100
0000 0101
2) 0000 0110
0001 1001
3) 0000 0110
0000 0101
4) 1111 0110
1111 0101
What is the difference between a full-adder and a half-adder?
1) Half-adder has a carry-in.
2) Full-adder has a carry-in.
3) Half-adder does not have a carry-out.
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4) Full-adder does not have a carry-out.
Q79.
The summing outputs of a half- or full-adder are designated by which Greek symbol?
1) Omega
2) Theta
3) Lambda
4) sigma
Q80.
Subtract the following hexadecimal numbers.
47
–25
Q82.
34
–1C
FA
–2F
1) 22
18
CB
2) 22
17
CB
3) 22
19
CB
4) 22
18
CC
Solve this binary problem:
1) 11001001
2) 10010000
3) 01101110
4) 01110110
Q83.
Find the 2's complement of –1101102.
1) 1101002
2) 1010102
3) 0010012
4) 0010102
Q84.
Which of the examples below expresses the associative law of addition:
1) A + (B + C) = (A + B) + C
2) A + (B + C) = A + (BC)
3) A(BC) = (AB) + C
4) ABC = A + B + C
Q85.
Which logic gate does this truth table describe?
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1) AND
2) OR
3) NOT
4) NAND
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SECTION-B
(5 MARKS QUESTIONS)
Q1) Explain the difference between the following memories:
(a) Volatile and Non-volatile.
(b) Static and dynamic.
(c) Sequential and Random access.
(d) Magnetic and semiconductor.
Ans.
1. Volatile memory: In this type of memory, if the electrical power is removed, then all information
stored in the memory will be lost. Many semiconductor memories are volatile.
2. Non-volatile memory: Memory units that retain the stored information even when power is turned
off are said to be non-volatile.
3. Random Access Memory (RAM): The RAM is a random access memory that has both read and
writes capability. RAM stores information that can be recalled, or “remembered”.
4. Sequential Access Memory (SAM): A memory device in which the access time is not constant but
varies depending on the address location. A particular stored word is found by sequencing through
all address location until the desired address is reached.
5. Static Memory devices: Semiconductor memories in which the stored data will remain
permanently stored as long as power is applied, without the need for periodically rewriting the data
into a memory.
6. Dynamic Memory devices: Semiconductor memories in which the stored data will not remain
permanently stored even with power applied, unless the data are periodically rewritten into memory.
7. Magnetic Memory: A system of storing information through the alignment of small grains in a
magnetic material. Once the grains have been aligned by an external magnetic field, the information
remains stored for long periods of time. This is the technique used in the hard drives of
computers as well as in magnetic tape.
8. Semiconductor Memory: A device for storing digital information that is fabricated by using
integrated circuit technology. Also known as integrated circuit memory; large-scale integrated
memory; memory chip; semiconductor storage; transistor memory
Q2.
Ans.
Explain positional number systems.
Number systems where the weight of a digit depends on its relative position within the number are
known as positional number systems. Note that in the decimal number system, the weight of each
position is some power of 10. This 10 is known as the base of the system.
A number system is comprised of:
1. A set of symbols for forming numbers;
2. A set of rules which may be used to form numbers from these symbols and assign values to them;
3. A set of rules for performing common arithmetic operations in this number system.
In the familiar decimal number system, there are ten distinct symbols that may be used to form
numbers. These are 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9. These symbols are known as digits. Any
combination of these ten digits together with a plus or minus sign appended at the left is a valid
integer in this number system. The weight of each digit in a number depends on its relative position
in the number.
Characteristics of some positional number systems:
Number system
Base
Symbols' used for forming numbers (written in
order of increasing value)
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SUBJECT: ‘DIGITAL ELECTRONICS’ (B.Sc.-IT-2)
Binary
Ternary
Balanced ternary octal
Octal
Decimal
Hexadecimal
Q3.
Ans.
2
3
3
8
10
16
Page 18 of 55
0,1
0,1,2
-1,0,1
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7,8,9
0,1,2,3,4,5,6,7,8,9, A, B,C,D,E,F
Convert (17.35)10 to binary number.
Integer part = 17
2
2
2
2
2
17
8
4
2
1
0
1
0
0
0
1
(17)10=(10001)2
Fraction part= .35. Radix = 2
F
i
.35  2 =
0.70
0
.70  2 =
1.40
1
.40  2 =
0.80
0
.80  2 =
1.60
1
.60  2 =
1.20
1
.20  2 =
0.40
0
.3510 = 011010…2
17.3510 = (1001.011012….)2
Q4.
Ans.
Convert 220 to binary number.
2
2
2
2
220
110
55
27
0
0
1
2
2
2
2
13
6
3
1
0
1
1
0
1
1
While writing the binary equivalent the digits are taken from bottom to top (as indicated by arrow).
The binary equivalent in the above example is (11011100)
Q5.
Ans.
Converting (0.40) to binary form.
Radix = 2
Fraction
integer
0.40 x 2
= 0.80
0.80 x 2
= 1.60
0.60 x 2
= 1.20
0
1
1
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Ph. 0175-2205100, 2215100
SUBJECT: ‘DIGITAL ELECTRONICS’ (B.Sc.-IT-2)
0.20 x 2
= 0.40
0.40 x 2
= 0.80
Thus binary equivalent of 0.40= (0.01100…)
Q6.
Ans.
Q7.
Ans.
Page 19 of 55
0
0
Convert (1011.11011) 2 to decimal no?
part first
1
x
23
=
8
0
x
22
=
0
1
1
x
2
=
2
1
x
20
=
1
=
11
Fraction part
Fraction = (0.11011)2
= 1 x 2–1+1x2–2+0x2-3+1x2-4x1x2-5
= ½ +¼+0+1/16+1/32
= (0.84375)10
Decimal equivalent of (1011.11011)2 is (11.84375)10
Explain the representation of integer in memory with example and what is the maximum
integer store in different word lengths?
In an 8085 -based system an integer can be represented in 1 byte. The left most bit is used as the
sign bit, and the remaining bits are used to represent the magnitude of the integer. The storage
format in a typical 8 bit per word microcomputer is given in fig.
7
6
5
4
3
2
1
0
Sign bit
Bit pattern representing the integer
0-positive
1-negative
Binary storage of 44 in 8 bits is 00101100
Example
For eq, the decimal number 25 is represented in the memory as follows:
The binary equivalent of 25 is
(25) 10 = (11001)2.
The bit pattern for 25 has only 5 bits. In order to store this in 8 bits, we have to expand this bit
pattern to an equivalent 8-bit pattern. We can do this by adding as many zeroes as are necessary
towards the left of the bit pattern 11001. Thus we have (25)10 = 00011001.
In this 8-bit pattern, the leftmost bit is the sign bit which we have kept 0 because 25 is a positive
integer
Maximum Integer: Most computers have a fixed number of bytes for storing integers. The
maximum permissible integer in a computer with n bits per word and one word per integer is equal
to (2 n-1 -1).
Q8.
Word length (in bits)
Maximum binary number
Decimal
equivalent
Expressed in 2"
form
2
01
1
21-1
3
011
3
22-1
4
0111
7
23-1
8
01111111
127
27-1
16
0111111111111111
32767
215-1
Explain Negative Number Representation in detail.
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Ans.
Page 20 of 55
There are three commonly employed schemes for representing the negative integers in binary form.
These are
1. The signed magnitude scheme
2. The one's complement scheme
3. The two's complement scheme
1. The Signed Magnitude Scheme: In this kind of representation, the sign bit is treated as
separate from the magnitude bits.
7
6
5
4
3
2
1
0
Sign bit
Bit pattern representing the integer
0-positive
1-negative
2. The one's complement: In 1’s compliment representation the number is obtained by replacing
every 1 by 0 and every 0 by 1. For example, the one's complement of 1100 is 0011. Note that the
one's complement of a binary number can be obtained simply by flipping each bit that is, changing
a 1 to a 0 and a 0 to a 1. The two's complement of a binary number is equal to its one's
complement plus 1. In order to find how a negative number is represented, we first find the
representation for the magnitude of this number and then take its one's complement. While taking
the one's complement, all the bits including the sign bit, are treated as representing the number.
This causes no problems since any positive number has sign bit 0 and one's complement will flip
this 0 to 1, signifying a negative number.
Example
Let us see how -9 will be represented in 1 byte per word memory using the one's complement
scheme. The representation of 9 is 00001001, in 8 bits.
- 9 = 11110110
3. Two's Complement Scheme: Two's complement of a binary number can be found by adding 1
to its one's complement. To represent the negative number in 2s complement, we first find the
representation of its magnitude and then take the two's complement. As with one's complement, the
sign bit must be included while taking the two's complement.
Example
Let us find a 1 byte representation of-9 using the two's complement scheme. The representation for
+9 is:
000010011
Two's complement of this = 11110111
Q9.
Ans.
Explain representation of real numbers.
The floating point representation of a number consists of two parts: the first part represents a
signed, fixed point number called the mantissa. The second part designates the position of decimal
point and is called the exponent.
In 32 bit representation, the mantissa occupies 24 bits in which the leftmost bit is used to indicate
the sign of mantissa and exponent occupies 8 bits in which the leftmost bit is used to indicate the
sign of exponent.
The bit 0 represents a positive number and 1 represents a negative number.
Floating point is always interpreted to represent a number in the following form:
M * re
Only the mantissa ‘m’ and exponent ‘e’ are physically represented in the register. The radix ‘r’ is
always assumed.
Mantissa
Q10.
Ans.
Exponent
sign bit
Explain addition in Binary Systems.
All the arithmetic operations (addition, subtraction, multiplication and division) in binary system are
performed in the same way as in decimal number system.
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Rules for carrying out addition of binary numbers are as follows:
0+0=0
0+1=1
1+0=1
1 + 1 = 0 with one 1 carry over.
Examples: - (i) for adding 110101 and 101111
Binary
Decimal
110101
53
101111
47
1100100
100
1100100 is equivalent to 100 in decimal system.
(ii)
For adding 10110 and 1101
10110
1101
100011
Q11.
Ans.
Explain subtraction in Binary Systems.
Subtraction:-Rules for subtraction of binary numbers are as follows:
0–0=0
1- 0=1
1–1=0
0 – 1 = 1 with one borrow
Examples
(i) Subtracting 101111
from 110101
Binary Decimal
110101 53
101111 47
000110 6
1102 is equivalent to 6 in decimal system.
(ii) Subtracting 1 101 from 101 10
10110
-1101
1001
Q12.
Ans.
Explain multiplication in Binary Systems.
Multiplication: Rules for multiplication of binary numbers are as follows:
0*0
=0
0* 1 =0
1* 1= 1
Examples
(i) Multiplying 10110 with 1 101
10110
1101
------10110
00000x
10110xx
10110xxx
100011110
In order to check, let us see the decimal equivalents of these binary numbers.
22 * 13 = 286 which is 10001 1110
(ii) Multiplying 111 with 101
111
101
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111
000x
111xx
100011
Q13.
Ans.
Explain Division in Binary Systems?
Division for binary numbers can be carried out by following the same rules as those applicable to
decimal system.
Examples
(i) Dividing 100011 by 101
101 100011
111
101
111
101
101
101
0
Q14. Convert 41.125 to binary no.
Ans.
We first convert the integer part 41 into binary by using remainder method. It is shown as follows:
41 divide by 2 remainder 1 (Quotient 20)
20 divide by 2 remainder 0 (Quotient 10)
10 divide by 2 remainder 0 (Quotient 5)
5 divide by 2 remainder 1 (Quotient 2)
2 divide by 2 remainder 0 (Quotient 1)
1 divide by 2 remainder 1 (Quotient 0)
Now fraction part 0.125 can be converted as follows:
Fraction
Fraction
Fraction
0.125
2
0.250
0.250
2
0.500
0.500
Integer part=0
Integer part=0
2
Integer part=1
1.000
Fraction 0.001.
Hence binary equivalent of .125 is 001. Therefore, the binary equivalent of (41.125) 10 is
(101001.001)2
Q15. Convert decimal number 755.9375 to its hexadecimal equivalent.
Ans. The integer part 755 can be converted as follows:
755 divide by 16 remainder 3 (Quotient 47)
47 divide by 16 remainder 15 (i.e.F) (Quotient 2)
2 divide by 16 remainder 2 (Quotient 0)
hence (755)10 = (2F3)16
Now we convert the fraction part .9375
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0.9375
Fraction
 16
Integer part=15 i.e. F
15.0000
Fraction 0.0000 Hence (0.9375)10 = (F)16
therefore (755.9375)10 = (2F3.F)16
Explain 1’s compliment arithmetic.
Case a) Subtrahend is smaller than the minuend
1. Complement the subtrahend by converting all 1’s to 0’s and all 0’s to 1’s
2. Add this to minuend.
3. Disregard the carry and add 1 to the total (end-around-carry)
Example:
Perform the subtraction using 1’s complement addition of the following binary numbers
110010
101101
Solution:
110010

110010
-101101
+010010
-----------1000100 end-around-carry
1
---------000101
Q16.
Ans.
Case b) Subtrahend is larger than the minuend
1. Complement the subtrahend
2. Add this to minuend
3. Complement the result and place a negative sign in front of the result
Example:
Perform the subtraction using 1’s complement of the following binary numbers:
1011010 
1011010
-1101010
+0010101
1’s complement of 1101010
-------------1101111
Q17.
Ans.
Explain 2’s Complement Subtraction.
(a) Subtrahend is smaller than the minuend
1. Determine the 2’s complement of the smaller number.
2. Add this to the larger number.
3. Disregard the carry.
Ex subtract (1011)2 from (1100)2
1100
+0101
Carry— >10001
The carry is disregarded. Thus, the Answer is (0001)2.
(b) Subtrahend is larger than the minuend.
1. Determine the 2’s complement of the subtrahend.
2. Add this to the minuend.
3. Take the 2’s complement of the result and place a negative sign in front of the result.
Subtract (1011)2 from (1101)2,
1001
+0101
Nocarry 1110
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No carry is obtained. Thus, the difference is negative and the true answer is 2’s complement of
(1110)2 i.e., (0010)2.
Q18.
Ans
Explain Minterms and Maxterms.
Minterm: A minterm is a special case product (AND) term. A minterm is a product term that
contains all of the input variables that make up a Boolean expression. A 2-variable function has four
possible combinations viz., AB, A’B, AB’ and A’B’. An input variable is complemented when it has a
value of 0.
Maxterm: A maxterm is a special case sum (OR) term. A maxterm is a sum (OR) term that contains
all of the input variables that make up a Boolean expression. A 2-variable function has four possible
combinations, viz. A + B, A’ + B, A + B’ and A’ + B’. An input variable is complemented when it has
a value of 1.
Table: Minterms and Maxterms for three binary variables
Minterms
Q19.
Ans.
Maxterms
x y z
Term
Designation
Term
Designation
0 0 0
x’y’z’
m0
x+y+z
M0
0 0 1
x’y’z
m1
x + y + z’
M1
0 1 0
x’y z’
m2
x + y’+ z
M2
0 1 1
x’y z
m3
x + y’+ z’
M3
1 0 0
xyz
m4
x’+ y+ z
M4
1 0 1
x y’z
m5
x’+ y + z’
M5
1 1 0
x y z’
m6
x’+ y’+ z
M6
1 1 1
xyz
m7
x’+ y’+ z’
M7
Explain Sum of Minterms. Give example.
For n binary variables, one can obtain 2 n distinct minterms, and that any Boolean function could be
expressed as a sum of minterms. The logical sum of two or more logical minterms is called a sum
of minterms expression. Sum of minterms are those that give the 1’s of the function in the truth
table. Each term must contain all the variables. If it misses one or more variables, it is ANDed with
an expression such as (x+x’) where x is one of the missing variables.
Example
Express the Boolean function F = A + B’C in a sum of minterm form. The function has three
variables A, B and C. The first A is missing two variables therefore:
A = A(B + B’) = AB + AB’
This is still missing one variable in both the terms, so
AB(C + C’) +AB’(C + C’)
= ABC +ABC’+ AB’C + AB’C’
The second term B’C is missing one variable:
B’C = B’C(A + A’) = AB’C + A’B’C
Combining all terms, we have:
F = A + B’C
= ABC + ABC’ + AB’C + AB’C’ + AB’C + A’B’C
But, AB’C appears twice and according to property( x + x = x), it is possible to remove one of them.
Rearranging the minterms in ascending order, we finally obtain:
F = A’B’C + AB’C’ + AB’C + ABC’ + ABC
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= m1 + m4 + m5 + m6 + m7
The aboce expression can also be represented as:
F(A,B,C) = (1, 4, 5, 6, 7)
Q20.
Ans.
Explain Product of Maxterms.
The functions of n binary variables can also be expressed as a product of maxterms. To express
the Boolean function as a product of maxterms, it must first be brought into a form of OR terms.
This may be done by using distributive law x + yz = (x+y)(x+z). Then any missing variable x in each
term is ORed with xx’. This procedure is clarified by the following example:
Example
Express the Boolean function F = xy + x’z in a product of maxterm form. First convert the function
into OR terms using the distributive law:
F = xy + x’z + (xy +x’)(xy + z)
= (x +x’) (y +x’) (x + z) (y + z)
= (x’ + y) (x + z) (y + z)------[x+x’=1]
The function has three variables: x,y, and z. Each OR term is missing one variables ; therefore:
x’ +y = x’ +y +zz’ =( x’ +y +z)( x’ +y +z’)
x + z = x + z +yy’ =( x + y +z)( x + y’ +z)
y +z = y +z +xx’ = (x + y +z)(x’ +y +z)
Combining all the terms and removing those that appear more than once, we finally obtain:
F = (x + y + z)( x + y’+ z)(x’ + y + z)(x’+ y + z’)
=M0 M2 M4 M5
This function can be represented as follows;
F(x, y ,z) =  (0, 2, 4, 5)
Q21.
Ans.
Write different laws of Boolean Algebra.
Identity
Name
(x’)`=x
Law of the double complement
x+x=x
Idempotent law
x.x=x
x+1=1
Dominance Law
x.0=0
x+0=x
Identity Law
x . 1=x
x+y=y+x
Commutative Laws
x. y = y. x
x+(y+z)=(x+y)+z
Associative Law
x. (y . z) = (x . y). z
x+ (y. z) = (x + y) . (x+ z)
Distributive Law
x. (y + z) = (x . y) + (x . z)
(x . y)’ = x’ +y’, (x+y)’ = x’ . y’
Q22.
De-Morg an’s Law
Explain and prove De Morgan’s Law.
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Ans.
De morgans theorms are extremely useful in simplifying expression in which product of a sum of
variables is complemented. The two theorms are:
(a)
(x + y+z+……)’= x’.y’.z’……
(b)
(x.y.z……)’= x’+ y’+z’+……
The complement of an OR sum equals the AND product of the complements.
The complement of an AND product equals the OR sum of the complements.
Proof
To prove part (a), we must prove that x’. y’ is the complement of x + y. If m = x + y and we assume
that m’ = x’. y’, then we must prove that m.m’= 0 and m + m’=1.
Now,
m+m’ = x + y + x’ y’
=( x + y + x’)( x + y + y’)
=(x + x’ + y)(x + y + y’)
=(1 + y)(x + 1)
=1
Also, m.m’= (x + y) x’. y’
= x.x’.y’ + y.x’.y’
= 0.y’+ x’.y.y’
= 0.y’+ x’.0
=0
Q23.
Ans.
What is Combinational Logic?
Combinational logic deals with the techniques of “combining” the basic gates into circuits that
perform some desired function In combinational logic circuits, at any time, the logic level at the
output depends on the combination of logic levels present at the inputs. Combinational circuit has
no memory characteristic, so its output depends only on the current value of its inputs. A
combinational logic digital function can be completely specified by a truth table. Truth table shows
output of the function corresponding to each and every possible combination of input variables.
An arbitrary logic function can be expressed in the following terms:
(I)
Sum of products (SOP) (II) Product of Sums (POS)
Q24.
Ans.
Define SOP, POS, MINTERM and MAXTERM.
Sum of Products (SOP):
The logical sum of two or more logical product terms is called a sum of products expression. It is
logical OR of multiple product terms. Each product term is the AND of binary literals.
Y=AB+BC+AC,
Y=A’B+BC+AC’
Product of Sums (POS)
The logical product of two or more logical sum terms is called a product of sums expression. A
product of sums is the logical AND of multiple OR terms. Each sum term is the OR of binary literals.
Y=(A +B)(B+C)(A+C)
Minterm: A minterm is a special case product (AND) term. A minterm is a product term “that
contains all of the input variables that make up a Boolean expression. A 2-variable function has four
possible combinations viz., AB, A’B, AB’ and A’B’.). The input variables are complemented when
they have a value of 0.
Maxterm: A maxterm is a special case sum (OR) term. A maxterm is a sum (OR) term that contains
all of the input variables that make up a Boolean expression. A 2-variable function has four possible
combinations, viz. A + B, A’ + B, A + B’ and A’ + B’. The input variables are complemented when
they have a value of 1.
Q25.
Ans.
What are Canonical Forms?
The rule of Canonical form is that each term which is used in an equation must contain all of the
available input variables. Two formats generally exist for expressing equations in a canonical form
(i)sums of minterms, and (ii) products of maxterms.
To place a SOP equation into canonical form using Boolean algebra, we do the following:
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1. Identify the missing variable(s) in each AND term.
2. AND the missing term(s) and its complement with the original AND term AB(C + C). Because C
+ C’ = 1.
3. Expand the term by application of the property of the distribution, ABC+ ABC’
To place a POS equation into canonical form using Boolean algebra, we do the following:
1. Identify the missing variable(s) in each OR term.
2. OR the missing term(s) and its complement with the original OR term, A + B + CC’. Because
CC’ = 0.
3. Expand the term by application of distributive property, (A + B + C) (A + B +C’)
Example
Convert A + B to minterms.
Solution: A + B = A. 1 + B. 1 ------------------- (A. 1= A)
= A(B+B’)+B(A+A’)
= AB + AB’ + BA + BA’ =AB +AB’+A’B
Q26.
Ans.
Express the function Y= A + B’C in canonical SOP and POS forms.
(a) Sum of Products (SOP)
Y=A+B’C=A.(B+B’)+B’.C(A+A’)
= AB+AB’+ABC+ A’B’C
= AB(C+C’)+AB’(C+C’)+AB’C+A’B’C’
= ABC+ABC’ +AB’C+AB’C’ +AB’C+A’B’C’
= ABC+ABC’ +AB’C+AB’C’+A’BC
(b) Product of Sums (POS)
Y=A+B’C=(A+B’)(A+C)
=(A+B’+C)(A+B’+C’)(A+B+C)(A+B’+C)
=(A+B’+C)(A+B’+C’)(A+B+C)
Q27.
Simplify the following Boolean Function in Product of Sums (POS) form:
F (A, B, C, D) =  (0, 1, 2,4 5,6 8, 9, 10).
The k-map for the function F is shown below:
Ans.
AB CD 00
00
01
01
1
11
1
1
1
10
0
1
0
1
0
0
0
1
11
0
10
0
1
1
The 1’s marked in the map represent the minterms that produce a 1 for the function. The squares marked
with 0’s represent the minterms not included in F and therefore, denotes the complement of F.
The terms obtained by two loops are ANDed together to obtain the final expression in POS form:
F = (A’ + B’) (C’ + D’)
Q28.
Verify that A
Ans.
A
B
C=ABC+AB’C’+A’B’C+A’BC’.
B= A’B + B’A
A B C=(A’B+B’A)’C+(A’B+B’A)C’
[(A’B)’.(B’A)’]C+A’BC’+B’AC’
( (A+B’)(B+A’))C +A’BC’+B’AC’
(AB+AA’+BB’+B’A’)C+A’BC’+B’AC’
ABC+A’B’C+A’BC’+AB’C’
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Q29.
Ans.
Page 28 of 55
Make OR, AND gate using NAND gate.
A
NAN
D
NAN
D
A.B
B
AB
A'
NAN
D
A
This is AND
gate
A'. B' = A'' + B''
= A + B  which
is
OR Gate
NAN
D
B'
NAN
D
B
In case 1:
Output of first NAND gate is=(AB)’
Output of second NAND gate is=((AB)’ .(AB)’)’ =(AB)’’ =AB
In case 2:
Output of first NAND gate is=(AA)’=A’
Output of second NAND gate is=(BB)’=B’
Output of third NAND gate is=(A’B’)’ = A’’+B’’=A+B
Q30.
Ans.
Design 3*8 decoder.
Input
Outputs
x
y
z
D7
D6 D5 D 4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
The logic diagram can be drawn as follow:
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Decoder
Q31.
Define Decoder Expansion, with example.
Ans. Decoders expansion means that a larger decoder can be made by two or more small decoders.
There are occasions when a certain-size decoder is needed but only smaller sizes are available. When this
occurs it is possible to combine two or more decoders with enable inputs to form a larger decoder. Thus if a
6-to-64-Iine decoder is needed, it is possible to construct it with four 4-to-16-line decoders. Figure shows
how small decoders with enable inputs can be connected to form a larger decoder. Two 2-to-4-line
decoders are combined to achieve a 3-to-8-line decoder. The two least significant bits of the input are
connected to both decoders. The most significant bit is connected to the enable input of one decoder and
through an inverter to the enable input of the other decoder. It is assumed that each decoder is enabled
when its input is equal to 1. When E is equal to 0, the decoder is disabled and all its outputs are in the 0
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level. When A2 = 0, the upper decoder is enabled and the lower is disabled. The lower decoder outputs
become inactive with all outputs at 0. The outputs of the upper decoder generate outputs Do through Da,
depending on the values of A1 and Ao (while A2 = 0). When A2 = 1, the lower decoder is enabled and the
upper is disabled. The lower decoder output generates the binary equivalent D0 through D7 since these
binary numbers have a 1 in the A2 position. Here using A2 bit as a chip select.
Q32.
Ans.
Q33.
Ans.
Explain Encoders.
Encoders: An encoder is a digital circuit
Inputs
Outputs
that performs the inverse operation of a
decoder. An encoder has n input lines and
D0 D1 D2 D3 D4 D5 D6 D7
x
y x
n output lines. The output lines generate
1 0 0 0 0 0 0 0
0 0 0
the binary code corresponding to the input
value. An example of an encoder is the
0 1 0 0 0 0 0 0
0 0 1
octal-to-binary encoder; it has eight
0 0 1 0 0 0 0 0
0 1 0
inputs, one for each of the octal digits, and
three
outputs
that
generate
the
0 0 0 1 0 0 0 0
0 1 1
corresponding binary number. It is
0 0 0 0 1 0 0 0
1 0 0
assumed that only one input has a value
0 0 0 0 0 1 0 0
1 0 1
of 1 at any given time; otherwise, the
FIGURE A 3X8 decoder constructed with two 2X4
circuit has no meaning.
0 0 0 0 0 0 1 0
0 0 0
decoders
0 0 0 0 0 0 0 1
1 1 1
Draw & explain (4to1) MULTIPLEXER.
Write applications of MULTIPLEXER.
A digital multiplexer (MUX) is a circuit with one output, 2 n input lines and n selection lines. The
selection of a particular input line is controlled by the selection lines. It accepts several digital data
input lines and selects one of them and transmits information on a single output line. A multiplexer
with 2n input lines and n selection line is said to be a 2 n x 1 MUX. For example an 8 x 1 line MUX
has 3 selection lines 8 input lines and one output line. Device having 4-Inputs & 1-output called 4 x
1MUX. as shown in figure. As 4 – Input (22) device we need two select lines So & S1.
I0
I1
4X1
MUX
y
I2
I3
S0 S1
TRUTHTABLE For 4 to 1 mux
S1 S0
0 0
0 1
1 0
1 1
Y
I0
I1
I2
I3
APPLICATION:
1.
To convert signal from time Domain to frequency domain.
2.
To transmit telephone signals on a same channel, time multiplexing is used.
3.
For analog information, frequency division multiplexing is used i.e. Telephone.
4.
For digital information i.e. (Audio signal video signal) we use time Division multiplexing.
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Q34.
Ans.
Page 31 of 55
Define Half Adder.
A Half adder is a combinational circuit that can add two binary numbers of single bit. It accepts two
input single bit binary numbers and produces two outputs, one for sum and the other for carry of
two input variables. Truth table for half adder may be given as follows:
Input
A
Output
B
0
0
0
1
1
0
1
1
From the truth table it is obvious that
Sum (s)
Carry (c)
0
1
1
0
0
0
0
1
S = A’B + AB’ and C = AB
Hence the logic diagram for half adder is as follows:
A
S
B
C
The block diagram of half adder is
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Q35.
Ans.
Z
Design of full adder circuit.
X
Y
Z
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
XY
0
2
6
1
1
1
SUM
0
1
1
0
1
0
0
1
CARRY
0
O
0
1
0
1
1
1
Z
XY
4
1
1
3
1
1
7
5
SUM = X'Y'Z + X'YZ' + XY'Z' + XYZ
x
y
Page 32 of 55
1
1
CARRY = XY + XZ + YZ
S
X
z
S
Y
C
FA
C
Z
BLOCK DIAGRAM
Q35.
Ans.
Design Demultiplexer.
A demultiplexer is a circuit that receives information on a single line and transmits this information
to one of 2n possible output lines. The selection of a specific line is controlled by the selection lines.
A decoder with an enable input can function as a demultiplexer. The following decoder can function
as a demultiplexer if the E line is taken as data input line and n input lines are taken as selection
lines.
Q36.
Draw circuit diagrams of AND, OR, NOT, gates. Also draw symbols of all gates with truth
tables.
AND Gate:
Circuit diagram:
Ans.
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Symbol:
Truth Table:
0
0
1
1
0
1
0
1
0
0
0
1
OR Gate:
Circuit diagram:
Symbol:
Truth Table:
0
0
1
1
0
1
0
1
0
1
1
1
NOT Gate
Circuit diagram:
Symbol:
Truth Table:
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0000000
1
Page 34 of 55
1
0
Q37.
Ans.
Show that NAND gate act as a universal gate.
Q38.
Draw figure of Decimal to BCD Encoders (74147).
OR
Explain Decimal to Binary Encoder.
A decimal to binary encoder converts the Decimal number to its equivalent binary Number:
The truth table is as follows:D0 D1 D2 D3 D4 D5 D6 D7 D 8 D9
B4 B3 B 2 B 1
Ans.
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
So to get a binary code of a decimal number an encoder is used. A Basic encoder converts a
decimal Digit from 0 to 9 into a 4 digit binary number for example 5 will be converted into 0101.
An Encoder has 10 inputs, a single input for each decimal number to get a Binary code of a decimal
number set to high the desired input for example to get binary code of 5 then set the D5 input high
all the other I/P’s will remain Low. The O/P B0 B1 B2 B3 will give 4- bit binary code.
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In the block diagram the connection are done using OR gate. When an Input is set to high. For e.g.
the D3 input is set to high the B1 and B2 will become high because both the B1 and B2 OR gates
are connected to D3 input. B1 and B2 OR gates will remain low so the O/P is 0011 this is the code
of Decimal no. 3.
Q39
Ans:
Explain the shift operation in binary multiplication and division.
Binary multiplication and division require a shift operation as well as addition and subtraction, the
same as in base 10 arithmetic.
Binary Multiplication: Let us take an example of binary multiplication:
Binary 13 x 10
1101
x 1010
0000
1101x
11010
0000xx
011010
1101xxx
10000010
When two numbers are multiplied in binary, the shift to the left occurs as in case of decimal
multiplication. To see this in the above example, small "x"'s have been used to indicate the shifts.
Addition takes place through the solution unlike in decimal. This is because it is easier to add two
binary numbers as the carry bits are difficult to track when more than two numbers are added. It is
also the way that a computer carries out the operation.
In the example, decimal 13 is 1101 in binary and decimal 10 is 1010. Since the first bit (the right
most bit) in 1010 is a 0, the result of the multiplication is 0's, the first line of the solution.
Multiplication by 1 (the second bit from the right in 1010) takes place after a shift to the left. Since
1101 is multiplied by 1, the result is 1101 with a 0 to the right as a result of the shift. The first two
lines of the solution are then added to get the third line of the solution. The fourth line of the solution
is all 0's since multiplication by 0 (the third bit of 1010 from the right) has occurred. The extra zero's
indicate the shifts. The fifth line of the solution is the addition of the third and forth lines. The sixth
line is 1101 since a multiplication by 1 has occurred (the left most bit of 1010). Three 0's to the right
of the 1101 represent the shifts to the left. The final line of the solution, the answer, is the addition
of the fifth and sixth lines. This line is 10000010 in binary and this is 130 in decimal.
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Binary division: Shifting occurs in binary division also. To understand it, let us take an example:
Divide 10110 by 11
Q40.
Ans.
Explain Full Adder.
FULL ADDER: An electronics device which performs the arithmetic addition is called adder the half
adder only performs addition on 2-bits but a full adder performs addition of 3- bits. Full adder takes
carry as 3rd input and add this with two other inputs A and B.
Full adder
A 0
B 0
1
Sum 1 carry = 1 ( From previous calculation )
Carry we are talking is a coming from lost calculation to understand more clearly lets take an
example.
Add 010 with 011
This calculation will be performed like this
010
A
B
Sum
A
Half adder
0
1
+
B
011
101
But if we does not consider carry i.e. only add A and B and ignore the carry then the output will be
010
011
001
Since half adder uses only two inputs the incoming carry will not be considered and the answer will
be wrong, as we have seen in above example. So to get correct output we must consider the carry
also and we must use the full adder which performs 3- bit addition.
A
B
Carry in
Sum
Full
adder
Carry out
BLOCK DIAGRAM
In the above Diagram A, B and C are three inputs. S and Carry out are two outputs.
The third input C is carry signal (bit) Coming From last calculation.
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A
B
C
Sum
Half
Adder
A
Half
Adder
B
S
Page 37 of 55
Circuit Diagram of Full adder
In the above Circuit Diagram two half adders are used. In the first Step the input A and B are
added and the Sum of A and B is added with C using 2 nd Half adder. The Final value of Sum
is taken from the 2nd half adder. The Carry of both the half adders is given to an X-OR gate to
produce the carry output.
TRUTH TABLE
A
0
0
0
0
1
1
1
1
Q41.
Ans.
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
S
0
1
1
0
1
0
0
1
C
0
0
0
1
0
1
1
1
Explain R-S Flip Flop.
It consists of two NAND gates. We can also construct by using two NOR gates
NAND based RS flip flop:
INPUTS
R
0
0
1
1
S
0
1
0
1
OUTPUTS
Q
Q’
1
1
1
0
0
1
0/1
1/0
STATE
Race condition
Set
Reset
No Change
NOR based flip flop:
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The input and the output possibilities for NOR gate R-S Flip Flop is shown in the truth table:
INPUTS
OUTPUTS
STATE
R
S
Q
Q’
0
0
1
0
No Change
0
1
0
1
1
0
Set
1
0
0
1
Reset
1
1
0
1
Forbidden
Q42.
Ans.
Explain Clocked SR flip flop.
A SR Flip-Flop has three inputs, which are labeled S (for Set), R (for Reset) and C (for Clock). The
graphic symbol of the SR flip-flop is shown in the figure below. It has two outputs Q and Q’ which is
the complemented output, and it is indicated with a small circle at the output terminal. The arrowhead in front of C is dynamic input which means that the flip-flop responds to a positive transition,
i.e., from 0 to 1 of the input clock signal.
Figure :SR Flip-Flop
R
Q
CP
S
Q
1
If there is no signal at the clock input C, the output of the circuit cannot change irrespective of the
values at inputs S and R. Only when the clock signal changes from 0 to 1, the output will be
affected according to the values in inputs S and R. The S and R columns give the binary values at
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the two inputs. Q is the output at a given time (referred to as present state). Q(t+1) is the output
after the occurrence of a clock transition (referred to as next state). The SR flip-flop should not be
pulsed when S=R=1 since it produces an indeterminate next state. This indeterminate condition
makes the SR flip-flop difficult to manage and therefore, it is not in practice.
Q43.
Ans.
Explain D Flip-Flop.
The D (Data) flip-flop is a modified version of the SR flip-flop. We can convert an SR flip-flop to a D
flip-flop by inserting an inverter between S and R and then assign the symbol D to the single input.
The D input is sampled during the occurrence of a clock transition from 0 to 1. If D=1, the output of
the flip-flop goes to 1 state, but if D=0, the output of the flip-flop goes to the 0 state.
The graphic symbol and characteristic table of the D flip-flop are shown below. From the
characteristic table we note that the next state Q(t+1) is determined from the D input. The Q output
of the flip-flop receives it’s value from the D input, every time when the clock signal changes from 0
to 1. No input condition exists that will leave the state of the D flip-flop unchanged. It has the
disadvantage that it does not have a no change condition Q (t+1) = Q (t). The no change condition
can be achieved by disabling the clock signal or feeding the output back into the input to keep the
state of flip-flop unchanged.
Figuer : D Flip Flop
Figure (b): Logic diagram D-flip flop
Q44.
Ans.
Explain JK Flip-Flop.
The output of an SR flip-flop is undefined when SR is 11, a flip-flop (JK) is designed to overcome
this problem. A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate condition of
the SR type becomes defined in the JK type. Inputs J and K behave like inputs S and R to set and
clear the flip-flop, respectively. But when inputs are J =1 and K =1, a clock transition switches the
outputs of the flip-flop to their complement state. The graphical and tabular representation is as
follows.
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JK Flip Flop
Logic diagram of JK flip-flop
Here J and K are equivalent to S and R respectively. Instead of indeterminate condition, the JK flipflop has a complement condition
Q(t+1) = Q’(t) when J = K = 1
Q45.
Ans..
Explain T Flip-Flop.
T flip flop is obtained from a JK type when inputs J and K are connected to provide a single input
designed by T. Obviously a T flip-flop has only two conditions: when T=0 (i.e. when both J and K
equals to 0) a clock transition does not change the state of the flip-flop, (i.e. when both J and K
equals to 0) a clock transition complements the state of the flip-flop.
T Flip-Flop
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T
Page 41 of 55
Q
CP
Q1
Logic diagram of T-flip flop
Q46.
Ans.
Explain Edge-triggered Flip-Flops.
The flip-flops like JK,SR,T,D do not change state during the change of clock pulse. In applications
we need flip flops that change their output during the clock pulse change. The most common type of
flip-flop used to synchronize the state change during a clock pulse transition is the edge-triggered
flip-flop. In this type of flip-flop, output transitions occur at a specific level at the clock pulse. When
the pulse input level exceeds this threshold level, the inputs are locked out so that the flip-flop is
unresponsive to further changes in inputs until the clock pulse returns to 0 and another pulse
occurs. Some edge-triggered flip-flops cause a transition on the rising edge of the clock signal
(positive-edge transition) and others cause a transition on the falling edge (negative-edge
transition). This is shown in the figure given below. The value in the D input is transferred to the Q
output when the clock makes a positive transition. The output cannot change when the clock is in
the 1 level, in the 0 level, or in a transition from the 1 level to the 0 level. The effective positive clock
transition includes a minimum time called the setup time in which the D input must remain at a
constant value before the transition and a definite time called the hold time in which the D input
must not change after the positive transition.
Edged Triggered Flip Flop
Q47.
Ans.
Explain Master Slave Flip-Flop.
The flip-flops that change their state during clock pulse change are master slave flip-flop in some
systems. This type of circuit has two flip-flops. The first is called the master, which responds to the
positive level of the clock and the second is known as the slave, which responds to the negative
level of the clock. The result is that the output changes during the 1 to 0 transition of the two clock
signals.
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We can construct a master-slave flip-flop by using two J-K flip-flops. (or D flip-flops or RS flip flops).
A master slave flip-flop using 2 JK flip-flops is shown below:
Master slave Flip-flop
When the clock pulse is 0 master is disabled but the slave becomes active and its output becomes
equal to Y and Y’ respectively. Why? Well the possible combination of the value of Y and Y’ are
either Y=1 which mean Y’ = 0 or Y = 0 which implies Y’ = 1. The slave flip flop thus can have values
either J=1 and K=0 which will set the flip-flop, that is Q=1 and Q’ = 0 or J=0, K=1, which will clear
the flip-flop. Therefore Q is same as Y.
Q48.
Ans.
Show different types of signals in memory chip.
Input and output signals common to most memory chips. Fig shows different signal categories
found in memory chips.
M
Address
Read
Write
Chip enable/
Select
Q49.
Ans.
E
M
O
R
Y
C
H
I
P
Data
Output disable
Power
supply
Other control
input/output
(a) What is the memory system reliability and how we measure it?
(b) Difference between static and dynamic RAM.
(a)
The reliability of a system is generally measured in the units of MTBF (mean time between
failure)the higher the MTBF, the more reliable the system.
MTBF Computation
A memory system consists of several chips. It is considered to fail if any of these chips fail. Thus, if
the MTBF of one memory chip is 800,000 hrs, and nine such chips are used, then the MTBF of the
complete memory system is 800,000/9 = 88,888 hrs. Note that one year has 8760 hrs. Thus, this
MTBF corresponds to approximately one failure every 10 year .
(b) Static and dynamic RAMs
There are two types of RAMs used in a Microprocessor -based system. These are: static RAM (also
known as SRAM) and dynamic RAM (also known as DRAM). A static RAM chip is characterized by
the fact that once a bit of information is written into a cell, the cell retains this information until it is
overwritten or electrical power is taken off the chip. The cell itself is a flip-flop and may consist of
four to six transistors.
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Q50.
Ans.
Page 43 of 55
A dynamic RAM chip has a much smaller cell than a static RAM. One bit of information is stored as
the charge on a capacitor. Typically, a dynamic RAM can store about four times as much
information as a static RAM in the same area due to the smaller cell structure. This also leads to
lower cost per bit for dynamic rams.
However, because the information is stored as charge on a capacitor, the dynamic RAM requires
refresh once every few milliseconds in order to retain the stored information. This refreshing needs
extra circuitry and makes the interfacing of dynamic rams to Microprocessor more complex than
the interfacing of static rams. Generally, systems that require large memory capacity, use dynamic
rams to lower the memory cost.
A) What is ROM and Explain different types of ROMS?
B) Explain Refreshing Dynamic RAM.
(A) A ROM, an abbreviation for Read Only Memory, is a preprogrammed chip and can only
be read by the Microprocessor. Thus, once the information has been recorded in the ROM,
generally by the manufacturer, the chip can either be used with whatever it contains or has to be
discarded.
A user programmable ROM, also known as PROM, or one time programmable ROM, can be
programmed by the user just once. After being programmed, the PROM behaves just like the ROM.
A PROM that can be erased by ultraviolet light and then reprogrammed, is known as an EPROM. In
order to erase the EPROM, it has to be taken out of its normal circuit and placed in front of a special
ultraviolet eraser for a several minutes.
The inconvenience and other technical problems associated with the removal of the EPROM from
its normal circuit of operation, are taken care of in Electrically Erasable and Programmable ROMs,
more popularly known as EEPROMs. The EEPROM can be erased, and programmed, while under
normal operation.
(B) The data in each cell of a dynamic RAM is held only for a short period of time after it is written
there. This time varies typically from 2-8 ns. In order to retain data in the cells, the cells need to be
refreshed once every few mille-seconds. It may, however, be more reliable to design a refresh
circuit that performs refresh every 6 or 7ms
Q51.
Ans.
What is the need of re-programmable ROMs and how we can erase data from ROMs?
The static and dynamic memories are volatile memories. Thus, when electrical power is removed
from these chips, they lose the stored information. In many applications, this is certainly not a
desirable feature. Non-volatile memories are very useful in situations where we would not like the
information to be destroyed when the power to the memory is removed. Disks and tapes are nonvolatile memories too. However, these are too slow to serve as primary memories in a
Microprocessor based system.
Read Only Memories that are erasable, have been the most popular non-volatile semiconductor
memories amongst designers. This is because data stored in these chips can be easily and
inexpensively altered. Chips that permit erasure of data by exposure to ultraviolet light and can then
be reprogrammed, are known as UVEPROMS.
Q52.
Ans.
Explain Programming the EPROM and write common steps for programming?
A system designer is generally required to program the EPROM with data before placing it in its
socket on the circuit board. The programming itself is carried out by a device commonly known as
an EPROM Programmer. The reason why data cannot be written into an EPROM, while it is in its
normal operating circuit, is that it requires the application of a high voltage to the chip for
programming it. This voltage varies from as high as 21 V for smaller size chips (less than 64 K
bytes) to as low as 12 V for larger size chips (over 32 K bytes). Though it is possible to generate
this voltage in the normal circuit, it makes the circuit design much more complex. Hence, EPROM's
are generally programmed using the EPROM programmer.
The following steps are used by an EPROM programmer while programming an EPROM:
1. Check if the pins are in proper contact with the socket.
2. Check if the EPROM has been inserted in the correct orientation and has not been reversed.
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3. Check if the EPROM has been erased or is blank. A blank EPROM will have all bits set to logical
1.
4. If the above checks succeed, then program the chip, which implies
That data is written into the chip.
5. Verify that the data written into the chip has been stored correctly
Q53. Convert decimal number 755.9375 to its hexadecimal equivalent.
Ans. The integer part 755 can be converted as follows:
755 divide by 16 remainder 3 (Quotient 47)
47 divide by 16 remainder 15 (i.e.F) (Quotient 2)
2 divide by 16 remainder 2 (Quotient 0)
hence (755)10 = (2F3)16
Now we convert the fraction part .9375
0.9375
Fraction
 16
Integer part=15 i.e. F
15.0000
Fraction 0.0000 Hence (0.9375)10 = (F)16
therefore (755.9375)10 = (2F3.F)16
Express the Boolean function F = xy + x’z in a product of maxterm form. First convert the function
into OR terms using the distributive law:
F = xy + x’z + (xy +x’)(xy + z)
= (x +x’) (y +x’) (x + z) (y + z)
= (x’ + y) (x + z) (y + z)------[x+x’=1]
The function has three variables: x,y, and z. Each OR term is missing one variables ; therefore:
x’ +y = x’ +y +zz’ =( x’ +y +z)( x’ +y +z’)
x + z = x + z +yy’ =( x + y +z)( x + y’ +z)
y +z = y +z +xx’ = (x + y +z)(x’ +y +z)
Combining all the terms and removing those that appear more than once, we finally obtain:
F = (x + y + z)( x + y’+ z)(x’ + y + z)(x’+ y + z’)
=M0 M2 M4 M5
This function can be represented as follows;
F(x, y ,z) =  (0, 2, 4, 5)
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Q54.
Ans.
Page 45 of 55
Explain Truth table of D Flip flop.
D flip flop:
J
D
D
Flip flop
K
Q
Q’
CLK
Block Diagram of D flip flop
D Flip-Flop is termed as Data or Delayed as in D flip Flop the input is delayed one clock pulse for
going to the output.
D
CLK
Q
0
0
No change
0
1
0
1
0
No change
1
1
1
Truth Table of D Flip Flop
In the above Truth Table if clock Pulse is 0 then the Output will not change i.e. it will remain as the
previous output, But if the clock Pulse is ‘1’ (High) the output will change according to the value of D
input i.e. if D input is ‘0’ (Low) the output will be ‘0’ (Low). And if the D input is ‘1’ (High) the output
will also be’1’ (High). The D Flip Flop works according to J-K Flip Flop. The J-K has following four
conditions:Q’
No Change
J
0
K
0
Q
0
1
0
1
1
0
1
0
1
1
Q’
Q
A1
A2
A3
A4
Not available in D
Flip Flop
Available in D Flip
Flop
Available in D Flip
Flop
Not available in D
Flip Flop
Truth Table of J-K Flip Flop
In D flip flop the input given to d is directly provided to J and its compliment is give to K through the
NOT gate.
A1) This Condition is not used because in this condition J=K=0.
A2) This Condition is used because J=0,K=1.
A3) This Condition is used because J=1,K=0.
A4) This Condition is not available because in this condition J=K=1.
Q55.
Explain S-R Flip Flop.
OR
Explain Basic Memory Cell using a Flip-flop.
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Ans.
Page 46 of 55
S-R Flip-Flop:- S-R Flip-Flop is Set Reset Flip Flop. This flip flop is used as a basic memory cell.
This unit stores 1-bit of binary data. It stores 1 when it is in set state & stores ‘0’ when it is in
RESET state.
S
Q’
R
Q
Circuit Diagram of S-R Flip Flop
RS
Q
Q’
Status
Invalid State
0
SET
1
1
0
RESET
0
0
1
No Change
1
0
0
1
1
Truth Table of S-R Flip Flop
A
0
0
1
B
0
1
0
Y
1
1
1
1
1
Truth Table of NAND Gate
0
To understand the truth table of S-R, first check the O/P of Nand gate.
In Nand gate if any of the I/P is ‘0’ the O/P will be ‘1’, So in S-R Flip-Flop
1) When R=S=0, Then both the O/Ps will be ‘1’.
2) When S=0 and R=1 the Q’ will Become 0 and Q will be 1.
3) When S=1 and R=0 then Q will become 1 and Q’ will become 0.
4) When S=R=1 the O/P will remain same as in Previous State.
4a) If the previous output is zero (Q=0), then the current output will also be zero as shown in figure
4(a).
1
R
1
S
0
1
2
0
Q
Q’
1
1
Figure 4(a)
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Page 47 of 55
When Q=0 and S=1 then the Nand gate O/P Q’=1. This O/P will go as 2 nd I/P to the 1st Nand gate ,
R=1 and Q’=1 the O/P Q will be ‘0’ this is same as the Previous or the Q we have assumed. In the
Figure 4(b) we can observe that Q remains at the same state (1) which we have assumed.
4b) If the previous output is one ( Q = 1) then the current output will also be one as shown in figure
4(b).
1
1
R
S
2
1
Q
Q’
0
1
Figure 4(b)
Then Q=1 and 2nd Nand gate Output Q’= ‘0’ this is applied to the 1st Nand gate i.e. R=1 and Q’=0
the Q will be. ‘1’, that means the O/P Q will not Change. In the above Figure 4(b) we can observe
that Q remains at the same as state (1) which we have assumed.
Q56.
Ans.
Sketch and explain J – K flip flop.
J-K flip flop
J-K flip-flop is constructed using S-R flip-flop; in S-R flip-flop an INVALID state is obtained. To
overcome this invalid state J-K is used. In J-K flip-flop TWO inputs J and K are given along with a
clock signal. The clock signal works as an enabler or as a switch. The output only change if the
clock is on i.e. it is set to 1. If clock is off i.e. reset to 0 the input combination does not affect the
output. Block diagram of J-K flip flop.
J
J-K
Flip-flop
CP
K
Q
Q’
BLOCK DIAGRAM OF J-K FLIP FLOP
Now let us look at the output of the J-K flip flop depending on the input combinations. We will use
the Truth table.
J
K
A
0
0
B
0
1
Q
Q
N / C [No Change]
0
1
0
C
1
0
1
D
1
1
Q’
Q [ Toggle]
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Ph. 0175-2205100, 2215100
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Page 48 of 55
The above-mentioned truth table is a simple representation of J-K FF’s working. In J-K clock pulse
(CP) plays a significant role. J-K flip flop only works when the CP is high. To show the working of JK with CP lets go through the following Truth table.
J
K
CP
Q
Q
0
0
0
N/C
0
0
1
N/C
N/C
A
0
1
0
N/C
1
1
0
[NO CHANGE]
if we observe the Truth table the O/P
only changes if the CP is high i.e. 1.
If the Clock Pulse is low then output
remains at same state i.e. no change
B
0
1
0
1
0
N/C
1
1
C
1 0
1
1
0
1 1
1
0
N/C
D
Q’
4 possible set of Input combination are available in J-K flip-flop. They are labeled as A, B, C, D. The
first Truth table is without Clock-pulse and the 2nd Truth table is with CP. So the 4 rows of first Truth
Table become 8 rows of 2nd Truth Table. Every row of first Truth Table is repeated twice in the 2 nd
Truth Table. For example:
i) In first truth table in 2nd row J=0 and K=1 the O/P is Q=0 is Q’=1. The same condition is repeated
twice in the 2nd truth table
a) J=0, K=1, CP=0 and
b) J=0, K=1, CP=1
In the (b) condition output will be Q=0 and Q’=1. So in the (b) condition O/P will change according
to the I/P because Clock pulse is set to 1 (high).
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SECTION-C
(10 MARK QUESTIONS)
Ques1. Explain:
(a) K-map with examples.
(b) Don’t care condition in K-map.
Ans: (a) Karnaugh Map: K map is a graphical method used to simplify a logic equation or to convert a
truth table to its corresponding logic circuit in a simple, orderly process. The map method gives us
a systematic approach for simplifying a Boolean expression.
K map contain cells. Each cell is represented by one particular combination of variables in
product form or sum form. Cells are assembled in a n orderly arrangement such that adjacent cell
represents minterms which differ by only one variable. A 0 denotes a complemented variable and
a 1 an uncomplemented form.
Number of cells in K map depends upon the number of variables of Boolean expression. K
map can be used for any number of variables.
For 2 variable: It contains 4 cells.
For 3 variable: It contains 8 cells
For example: Represent the following Boolean Expression by K-Map
Y=(A+B)(B+C’)(A’+B’+C’)
Solution:
Y=(A+B)(B+C’)(A’+B’+C’)
=(A+B+CC’)(AA’+B+C’)(A’+B’+C’)
=(A+B+C)(A+B+C’)(A+B+C’)(A’+B+C’)(A’+B’+C’)
= M0
M1
M1
M5
M7
Now, Boolean Expression can be written as:
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Page 50 of 55
Y(ABC)= (0,1,5,7)
K-Map representation of the given expression is shown below:
(b) Don’t Care Conditions in K-map: When an output value is not known for every combination of
input variables usually because all combinations cannot occur, then that function is incompletely
specified function. This means that the truth table does not generate an output value for every
possible combination of input variables. The minterms or maxterms which are not used as part of
the output function are called don’t care terms.Some times the function behaves the same even if
some terms have values 0 or 1, i.e., it does not matter if the function produces 0 or 1 for a given
term. Then we can say that we don’t care about the output of the function for this term. terms that
may produce either 0 or 1 for the function are said to be don’t care conditions and are marked with
an x in the map. These don’t care conditions can be used to provide simplification of the algebraic
expression.
When we choose adjacent squares to group for the function in the map, the x’s may be assumed to
be either 0 or 1, which ever gives the simplest expression. We need not use an x at all if it does not
contribute to the simplification of the function.
Consider the following Boolean function together with the don’t care minterms.
F (A, B, C) =  (0, 2, 3, 6)
d =  (1, 5)
The minterms listed with F produce a 1 for the function. The don’t care minterms listed with d may
produce either a 0 or 1 for the function. The map is shown in the following figure:
00
01
11
10
1
x
1
1
0
x
0
1
BC
A
0
1
The minterms of F are marked with 1’s , those of d are marked with x’s and the remaining squares
are marked with 0’s. The 1’s and x’s are combined in any convenient manner so as to enclose the
maximum number of adjacent squares.
Hence the simplified expression is
F = A’ + BC’.
Q2.
Ans.
Write common terms that are used in most memories.
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1. Memory cell: A device or an electrical circuit used to store a single bit (0 or I) is known as
memory cell Example : A flip-flop
2. Memory word: A group of bits (cells) in a memory that represents information or data of some
type is known as memory word. Examples: A register containing 8 FFs.
3. Byte: A group of 8-bits (0’s and l’s) is called a byte. Word sizes can be expressed in bytes
4. Capacity: The capacity of a memory unit is usually stated as the total number of bytes (or bits)
that can store.
5. Address: A number that identifies the location of a word in memory is known as address for
selection of a cell in a memory array for a read or a write operation.
6. Read operation: The operation whereby the binary word stored in a specific memory location
(address) is sensed and transferred to another location is known as read operation.
7. Write operation: The operation whereby a new word is placed into a particular memory location
is known as write operation or store operation.
8. Access time: The time required to locate and read a word from memory is called the access
time.
9. Cycle time: The time required for the memory to perform a read or write operation and then
return to its original state known as cycle time.
10. Volatile memory: In this type of memory, if the electrical power is removed, then all information
stored in the memory will be lost. Many semiconductor memories are volatile.
11. Non-volatile memory: Memory units that retain the stored information even when power is
turned off are said to be non-volatile.
12. Random Access Memory (RAM): The RAM is a random access memory that has both read
and writes capability. RAM stores information that can be recalled, or “remembered”.
13. Sequential Access Memory (SAM): A memory device in which the access time is not constant
but varies depending on the address location. A particular stored word is found by sequencing
through all address location until the desired address is reached.
14. Read/Write Memory (RWM): Any memory that can be read from or written into equal case.
15. Read-only Memory (ROM): A memory device in which the data are permanently stored is
called read only memory (ROM). The ROM is programmed by the manufacturer to the user’s
specifications.
16. Static Memory devices: Semiconductor memories in which the stored data will remain
permanently stored as long as power is applied, without the need for periodically rewriting the data
into a memory.
17. Dynamic Memory devices: Semiconductor memories in which the stored data will not remain
permanently stored even with power applied, unless the data are periodically rewritten into memory.
18. Storage Capacity: It is the amount of data that can be stored in the storage unit
Q3:
Ans.
What do you mean by logic gates? Draw truth table and symbol of 8 logic gates.
A logic gate is an electronic circuit which makes logic decisions. Logic gates have only one output
and two or more inputs except for the Not gate which has only one input. The output signal appears
only for certain combinations of input signals, gates do the manipulation of binary information.
Gates are the blocks of hardware that produces signals of binary 1 or 0 when logic input
requirements are satisfied. Each agte has a distinct symbol and an algebraic function. The names,
graphic symbols, algebraic functions, and truth tables of some logic "gates" are shown in Fig
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Q4:
Ans.
Page 52 of 55
Explain different types of memory in computer.
Registers:- The CPU uses a number of memory units called registers. Since, there is a movement
of the information between the various units of the computer system, so in order to handle the
process and to speed up the rate of information transfer, the computer uses registers. Registers in
CPU are used to store data temporarily during arithmetic and logical operations. They have very
low access time.
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Primary Memory: Registers require space on the Microprocessor chip and hence only a limited
number of them can be provided. A program and any data used by the program reside in the
primary memory while the computer is working on that program. It is in the constant communication
with the CPU as a program of instruction is being executed.
Mass Storage:-In most systems, we need several programs and data to be resident within the
system so that they can be loaded for execution into the primary memory without much delay.
Examples of these programs include compilers, assemblers, text editors, and other utility programs.
As the storage of main memory is inadequate, then secondary memory is used to enhance storage
capabilities. The secondary memory generally operates at a slower speed than the registers and
main memory. They are used to store large quantities of data. Hard disks, floppy disks, and optical
disks are some of the devices used for mass storage.
Cache:-In certain systems, the primary memory may be much slower than the CPU for cost or
other reasons. This would imply that the CPU waits for the primary memory to send or receive data.
This waiting time eventually results in decreased performance of the CPU. In order to avoid the
CPU operating at lower than its rated speed, designers use cache memory. The cache is very small
as compared to primary memory, but much faster. However, as the cache consists of faster
memory chips, it is expensive too.
Off-line Backup:-What does one do when all the mass storage available in a system gets used
up? It may be cost effective to have a removable storage device in the system such as a removable
hard disk or a tape drive. Once such a device is available, the user can perform periodic backup
operations. A backup operation removes some of the very infrequently used data and programs and
saves them on a backup tape or a hard disk cartridge.
Q5: Explain the need of JK-FF
Or
Why JK is used in place of SR-FF?
Ans:
the basic gated SR NAND flip-flop suffers from two basic problems: number one, the S = 0 and
R = 0 condition or S = R = 0 must always be avoided, and number two, if S or R change state while the
enable input is high the correct latching action may not occur. Then to overcome these two fundamental
design problems with the SR flip-flop, the JK flip-Flop was developed.
This simple JK flip-Flop is the most widely used of all the flip-flop designs and is considered to be a
universal flip-flop circuit. The sequential operation of the JK flip-flop is exactly the same as for the previous
SR flip-flop with the same "set" and "reset" inputs. The difference this time is that the JK flip-flop has no
invalid or forbidden input states of the SR Latch (when S and R are both 1).
The JK flip-flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents the
illegal or invalid output condition that can occur when both inputs S and R are equal to logic level "1". Due to
this additional clocked input, a JK flip-flop has four possible input combinations, "logic 1", "logic 0", "no
change" and "toggle". The symbol for a JK flip-flop is similar to that of an SR Bistable Latch as seen in the
previous tutorial except for the addition of a clock input.
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The Basic JK Flip-flop
Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs called the J
and K inputs, respectively after its inventor Jack Kilby. Then this equates to: J = S and K = R.
The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-input NAND gates
with the third input of each gate connected to the outputs at Q and Q. This cross coupling of the SR flip-flop
allows the previously invalid condition of S = "1" and R = "1" state to be used to produce a "toggle action" as
the two inputs are now interlocked. If the circuit is "SET" the J input is inhibited by the "0" status of Q
through the lower NAND gate. If the circuit is "RESET" the K input is inhibited by the "0" status of Q through
the upper NAND gate. As Q and Q are always different we can use them to control the input. When both
inputs J and K are equal to logic "1", the JK flip-flop toggles as shown in the following truth table.
The Truth Table for the JK Function
Input
same as
for the
SR Latch
toggle
action
Output
J
K
Q
Q
0
0
0
0
0
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
0
Description
Memory
no change
Reset Q » 0
Set Q » 1
Toggle
Then the JK flip-flop is basically an SR flip-flop with feedback which enables only one of its two input
terminals, either SET or RESET to be active at any one time thereby eliminating the invalid condition seen
previously in the SR flip-flop circuit. Also when both the J and the K inputs are at logic level "1" at the same
time, and the clock input is pulsed either "HIGH", the circuit will "toggle" from its SET state to a RESET
state, or visa-versa. This results in the JK flip-flop acting more like a T-type toggle flip-flop when both
terminals are "HIGH".
Q6: Explain Master-Slave JK-FF.
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Ans: JK FF was developed because although JK-Flipflop circuit is an improvement on the clocked SR
flip-flop it still suffers from timing problems called "race" if the output Q changes state before the timing
pulse of the clock input has time to go "OFF". To avoid this the timing pulse period (T) must be kept as short
as possible (high frequency). To achieve this the JK Master-Slave FF was developed. This eliminates all the
timing problems by using two SR flip-flops connected together in series, one for the "Master" circuit, which
triggers on the leading edge of the clock pulse and the other, the "Slave" circuit, which triggers on the falling
edge of the clock pulse. This results in the two sections, the master section and the slave section being
enabled during opposite half-cycles of the clock signal.
The Master-Slave JK Flip-flop
The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series configuration
with the slave having an inverted clock pulse. The outputs from Q and Q from the "Slave" flip-flop are fed
back to the inputs of the "Master" with the outputs of the "Master" flip-flop being connected to the two inputs
of the "Slave" flip-flop. This feedback configuration from the slave's output to the master's input gives the
characteristic toggle of the JK flip-flop as shown below.
The Master-Slave JK Flip-Flop
The input signals J and K are connected to the gated "master" SR flip-flop which "locks" the input condition
while the clock (Clk) input is "HIGH" at logic level "1". As the clock input of the "slave" flip-flop is the inverse
(complement) of the "master" clock input, the "slave" SR flip-flop does not toggle. The outputs from the
"master" flip-flop are only "seen" by the gated "slave" flip-flop when the clock input goes "LOW" to logic level
"0". When the clock is "LOW", the outputs from the "master" flip-flop are latched and any additional changes
to its inputs are ignored. The gated "slave" flip-flop now responds to the state of its inputs passed over by
the "master" section. Then on the "Low-to-High" transition of the clock pulse the inputs of the "master" flipflop are fed through to the gated inputs of the "slave" flip-flop and on the "High-to-Low" transition the same
inputs are reflected on the output of the "slave" making this type of flip-flop edge or pulse-triggered.
Then, the circuit accepts input data when the clock signal is "HIGH", and passes the data to the output on
the falling-edge of the clock signal. In other words, the Master-Slave JK Flip-flop is a "Synchronous"
device as it only passes data with the timing of the clock signal.
Prepared By: - Vaishnoo Maa Computers, SCO 145, Chotti Baradari, Patiala.
Ph. 0175-2205100, 2215100