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CSCI206 - Computer Organization &
Programming
Machine Language
zyBook: 5.4
Lab 2 & Prelab 3 are due tomorrow!
Positional Number Systems
n-th digit
base
Example: in base 10 (decimal)
Common bases
Decimal: b=10, digits={0,1,2,3,4,5,6,7,8,9}
Binary: b=2, digits={0,1}
Octal: b=8, digits={0,1,2,3,4,5,6,7}
Hexadecimal: b=16, digits={0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F}
Conversion Shortcuts from binary
Binary to octal: each group of three binary digits
gives a complete octal digit
e.g., 111 010 1012 -> 7258
e.g., 3678-> 011 110 1112
Binary to hexadecimal: each group of four binary
digits gives a complete hex digit e.g., 1 1101 0101 -> 1D5
2
16
e.g., 3A416-> 0011 1010 01002
Endianness
The order in which bytes are stored
in a multibyte word
big-endian: stored with the most
significant bits first (natural order
when read from left to right)
little-endian: stored with the least
significant bits first (looks weird)
Endian Examples
The hexadecimal value 0x01020304
Big endian
address
01
02
03
04
101
102
103
04
03
02
01
100
101
102
103
100
100
byte address
Little endian
address
100
byte address
MIPS Endianness
ISA Supports either
As a result we’ll use both
the MIPS simulator we will use uses the host
endianness, in our case LITTLE
our mips machine uses BIG endian
MIPS Summary
design principle 2:
smaller is faster
32-bit architecture
load-store memory system (RISC)
optimized for the common case
64 possible instructions
32 registers
arithmetic operations have 3 operands
3 registers
or 2 registers and one immediate value
32 bit word size
32-bit Architecture
What does it mean to be 32-bit?
This typically means the CPU
operates on 32-bit sized chunks of
data (words)
Addresses(Pointers) are 32-bits long
start of memory 0
end of memory 2^32-1 = 0xFFFFFFFF
0xFFFFFFFF
RAM
0
von Neumann
code is data
but how do we represent
instructions?
c = text file
assembly = text file
Need a simple
representation to keep
the CPU simple
Assembly vs Machine Language
00000000
0:
4:
8:
c:
10:
14:
18:
1c:
20:
Machine (byte) code
<main>:
27bdffe0
afbf001c
afbe0018
03a0f021
3c020000
24440000
24050201
240601e0
0c000000
addiu
sw
sw
move
lui
addiu
li
li
jal
sp,sp,-32
ra,28(sp)
s8,24(sp)
s8,sp
v0,0x0
a0,v0,0
a1,513
a2,480
0 <main>
Assembly language
code (text)
Assembly Language
Symbolic representation of machine code
easier for humans to write
simple translation to machine code (assembler)
assembly language also provides pseudo
instructions
Instructions that don’t actually exist in the ISA but
are useful
move $t0, $s0 is a pseudo instruction
translated to: ____________________?
Concept
Data and instructions are both
stored as binary data (numbers)
in memory.
Machine Language
Each (non-pseudo) assembly instruction is
given an operation code (opcode)
MIPS supports 64 opcodes, how many bits are
needed?
A single MIPS instruction is 32-bits long
classic RISC design
CISC processors allow variable length instructions
increases decode complexity
MIPS Machine Language
a machine instruction always begins with the
opcode
opcode [31:26]
.. 26 bits remain
32-bit instruction
Registers Come next
Most instructions operate on registers
the JUMP instructions do not!
Others access 2 or 3 registers
There are 32 registers in MIPS
how many bits are needed to specify a register?
MIPS Machine Language
Design Principle 3: Good
design demands good
compromises.
Three different types of instructions (depending
on opcode)
opcode [31:26]
reg1 [25:21]
reg2 [20:16]
opcode [31:26]
reg1 [25:21]
reg2 [20:16]
opcode [31:26]
reg3 [15:11]
1. Arithmetic (R-type) instructions
32 bits
opcode
rs
rt
rd
shift amount
function
opcode = basic operation (arithmetic = 0)
rs = first source register
rt = second source register
rd = destination register
shift amount = used for binary shift instruction
function = which arithmetic operation to perform (sent to
the ALU) (e.g., add = 0x20, addu = 0x21...
R-type example
6 bits
opcode
5 bits
rs (source1)
5 bits
rt (source2)
add $v0, $v0, $a0
5 bits
rd (dest)
5 bits
shift amount
6 bits
function
R-type example
opcode
rs
rt
add $v0, $v0, $a0
not used for add, set to 0
rd
shift amount
function
R-type example
0
rs
rt
add $v0, $v0, $a0
not used for add, set to 0
rd
0
0x20
R-type example
0
2
add $v0, $v0, $a0
4
2
0
0x20
R-type example
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
0
2
4
2
0
0x20
000000
00010
00100
00010
00000
100000
add $v0, $v0, $a0
R-type example
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
0
2
4
2
0
0x20
000000
00010
00100
00010
00000
100000
add $v0, $v0, $a0
?? (hex value)
R-type example
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
0
2
4
2
0
0x20
000000
00010
00100
00010
00000
100000
add $v0, $v0, $a0
0x00441020
2. Immediate (I-Type) Instruction
R-type is used when there are three
operands.
Many times we have a constant or
immediate operand.
In this case that immediate value is
included in the instruction.
Immediate (I-Type) Instruction
6 bits
opcode
5 bits
rs
5 bits
rt
16 bits
immediate value
Small constants are used frequently by
programs
I-type instructions encode a 16-bit signed
value to be used by the instruction
I-Type example
6 bits
opcode
5 bits
rs
5 bits
rt
addi $s0, $s1, 40
16 bits
immediate value
I-Type example
6 bits
opcode
8
5 bits
rs
5 bits
rt
16 bits
immediate value
40
addi $s0, $s1, 40
I-Type example
6 bits
5 bits
8
rs
16
5 bits
rt
17
addi $s0, $s1, 40
16 bits
40
I-Type example
6 bits
5 bits
5 bits
16 bits
8
17
16
40
001000
10001
10000
0000000000101000
addi $s0, $s1, 40
?? (hex value)
I-Type example
6 bits
5 bits
5 bits
16 bits
8
17
16
40
001000
10001
10000
0000000000101000
addi $s0, $s1, 40
0x22300028
3. Jump (J-type) instruction
This instruction just tells the CPU to fetch the
next instruction from a different location.
That location is encoded as an unsigned
immediate value in the instruction.
6 bits
26 bits
opcode
instruction address
J-type Example
6 bits
26 bits
opcode
instruction address
5
j MAIN ; assume MAIN = 0x400010
J-type Example
6 bits
26 bits
opcode
instruction address
2
j MAIN ; assume MAIN = 0x0400010
0x0400010 is a byte address, but in MIPS
instructions must be word aligned. So the lower
2 bits of the byte address must be 00. Therefore
we omit them to save space! (making the 26-bit
instruction effectively 28-bits!)
J-type Example
2
6 bits
26 bits
opcode
instruction address
0x0100004
j MAIN ; assume MAIN = 0x0400010
removing the lower 2 bits of 0x0400010 is the
same as dividing by 4 (shift right by 2), so the
encoded value is 0x0100004.
J-type Example
6 bits
26 bits
000010
0x0100004
j MAIN ; assume MAIN == 0x400010
?? (hex value)
J-type Example
6 bits
26 bits
000010
0x0100004
j MAIN ; assume MAIN == 0x400010
0x08100004