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Lecture Notes
Diodes for Power Electronic Applications
OUTLINE
• PN junction power diode construction
• Breakdown voltage considerations
• On-state losses
• Switching characteristics
• Schottky diodes
• Modeling diode behavior with PSPICE
Copyright © by John Wiley & Sons 2003
Diodes - 1
Basic Structure of Power Semiconductor Diodes
Anode
i
P+
v
N- epi
N+ substrate
19
N = 10 cm
A
10
microns
-3
breakdown
voltage
dependent
14
-3
N = 10 cm
D
19
N = 10 cm
D
-3
250
microns
Cathode
i
anode
1
i
v
v
R on
BVBD
 1V
v
cathode
Copyright © by John Wiley & Sons 2003
Diodes - 2
Breakdown Voltage Estimate - Step Junction

•
Non- punch- t hr ough di ode. Dr i f t
r egi on l engt h Wd > W( BV BD) =
W(V)
l engt h of space char ge r egi on at
br eak down.
•
•
•
•
•
•
W( V ) = Wo
Wo =
1+V / c
x
c
 +
V
c
2c ( Na+Nd )
qNaNd
2 c
Em ax =
1 + V / c
Wo
Po we r d i o d e at r e v e r se b r e ak d o wn:
Na >> Nd ; E = EBD ; V = BV BD >> c
W2 ( BV BD) =
Wo 2 BV BD
2 c
2 =
;
W
o
c
q Nd
Co ncl usi o ns
4 c
BV BD
Wo 2
•
( Em ax ) 2 = ( EBD) 2 =
•
So l v e f o r W( BV BD) and BV BD
t o ob t ai n ( p ut i n Si v al ue s)
 EBD2
1 .3x 1 0 17
BV BD =
=
; [V ]
2 q Nd
Nd
2 BV BD
W( BV BD) =
= 1 0 - 5 BV BD ; [µ m ]
EBD
1 . Lar g e BV BD ( 1 0 3 V ) r e q ui r e s Nd < 1 0 1 5 cm - 3
2 . Lar g e BV BD ( 1 0 3 V ) r e q ui r e s N- d r i f t r e g i o n > 1 0 0 µ m
Copyright © by John Wiley & Sons 2003
Diodes - 3
Breakdown Voltage - Punch-Through Step Junction
• Punch-t hrough st ep junct ion - W(BV BD) > Wd
- V +
+
P
N-
• V 1 + V 2 = BV BD
• E1 + E2 = EBD
+
N
qNd Wd 2
• BV BD = EBD Wd 2
W
d
Electric
field
E + E2
1
E
2
( EBD) 2
V
1
• If Nd < <
( required
2 q( BV BD)
V2
x
• E1 =
•
qNd Wd

• At breakdown:
qNd Wd 2
; V1 =
2
V 2 = E2 Wd
Copyright © by John Wiley & Sons 2003
v alue of Nd for non-punch-t hru
diode) , t hen
•
•
BV BD - EBD Wd and
Wd ( Punch-t hru)
- 0 .5 Wd ( non-punch-t hru)
Diodes - 4
Effect of Space Charge Layer Curvature
diffusing
acceptor
impurities
incident acceptor impurities
SiO 2
• If radius of curvature is comparable
to depletion layer thickness, electric
field becomes spatially nonuniform.
P
+
R
depletion
layer
NN
• Spatially nonuniform electric field
reduces breakdown voltage.
+
• Impurities diffuse as fast laterally as vertically
• Curvature develops in junction boundary and in
depletion layer.
Copyright © by John Wiley & Sons 2003
• R > 6 W(BVBD) in order to limit
breakdown voltage reduction to 10%
or less.
• Not feasible to keep R large if
BVBD is to be large ( > 1000 V).
Diodes - 5
Control of Space Charge Layer Boundary Contour
field plates
• Electrically isolated conductors
(field plates) act as equipotential
surfaces.
P+
depletion layer
boundary
N-
SiO 2
P
depletion
layer
boundary
P
P+
guard
ring
N
-
N+
aluminum
contact
Copyright © by John Wiley & Sons 2003
• Correct placement can force
depletion layer boundary to have
larger radius of curvature and t;hus
minimize field crowding.
• Electrically isolated p-regions
(guard rings)has depletion regions
which interact with depletion region
of main pn junction.
• Correct placement of guard rings
can result in composite depletion
region boundary having large radius
of curvature and thus minimize field
crowding.
Diodes - 6
Surface Contouring to Minimize Field Crowding
depletion layer
boundary
N+
N-
SiO
N+
2
N-
P+
bonding pad
P+
bonding pad
high field
region
• Large area diodes have depletion
layers that contact Si surface.
• Difference in dielectric constant of Si
and air causes field crowding at surface.
• Electric fields fringing out into air
attract impurities to surface that can
lower breakdown voltage.
Copyright © by John Wiley & Sons 2003
• Proper contouring of surface can
mimimize depletion layer curvature and
thus field crowding.
• Use of a passivation layer like SiO2 can
also help minimize field crowding and
also contain fringing fields and thus
prevent attraction of impurities to
surface.
Diodes - 7
Conductivity Modulation of Drift Region
• Forward bias injects holes into drift
region from P+ layer. Electrons
attracted into drift region from N+
layer. So-called double injection.
x
P
+
+
N
-
N+
-
• If Wd ≤ high level diffusion length La ,
carrier distributions quite flat with p(x)
≈ n(x) ≈ na.
W
d
p(x) = n(x)
log scale
16
= n a= 10
n (x)
p
n no=
10
p (x)
n
14
p
n
po
p
=
no
• For na >> drift region doping Nd, the
resistance of the drift region will be
quite small. So-called conductivity
modulation.
no
10 6
x
Copyright © by John Wiley & Sons 2003
• On-state losses greatly reduced below
those estimated on basis of drift region
low-level (Nd) ohmic conductivity.
Diodes - 8
Drift Region On-State Voltage Estimate
QF q A W d n a
• IF =
=
; Current needed


to maintain stored charge Q
q [µ n + µ p ] n a A V
• IF =
Wd
F.
d
W
d
x
;
Ohm’s Law (J = E)
P
Wd 2
• Vd =
; Equate above
[µ n + µ p ] 
two equations and solve for V
d
• Conclus ion: long lifetime
Copyright © by John Wiley & Sons 2003
+
+
N
-
IF
+ V j
+
V
d
N+
Cross-sectional
area = A
 minimizes V d .
Diodes - 9
Diode On-State Voltage at Large Forward Currents
• µn + µp =
µo
1 +
na
;
nb - 1 0 1 7 cm-3 .
nb
• Mobilit y reduct ion due t o increased
carrier-carrier scat t ering at large na.
q na A V d
• IF =
Wd
µo
1 +
na
; Ohms Law
nb
wit h densit y -dependent mobilit y .
• Inv ert Ohm’s Law equat ion t o find V d as
funct ion IF assuming na > > nb .
If Wd
• Vd =
q µo nb A
• V d = IF Ron
• V = Vj + Vd
Copyright © by John Wiley & Sons 2003
Diodes - 10
Diode Switching Waveforms in Power Circuits
Q rr
di
F
/ dt
= I
d i / dt
R
I F
rr
t
rr
I
0 .2 5
/ 2
rr
t
I
t
V
t
3
t
4
t
Von
FP
rr
5
•
rr
t
t
t
V
2
1
Copyright © by John Wiley & Sons 2003
t
S =
t
V
rr
R
•
diF
diR
dt and dt determined
by external circuit.
Inductances or power
semiconductor devices.
5
4
Diodes - 11
Diode Internal Behavior During Turn-on
t
i (t)
F
- +
- +
+
P - +
- +
Csc
interv al
1
N-
Rd
di F
V FP - I F Rd + L
dt
A
Csc (V) =
W(V)
Wd
Rd =
q n N d A
N+
L = stray or
wiring inductance
L
t interval
2
P+
i (t)
F
- +
- +
- +
N
-
N+
V j - 1.0 V
• Injection of excess
carriers into drift
region greatly
reduces Rd.
time
time
time
x
Copyright © by John Wiley & Sons 2003
Diodes - 12
Diode Internal Behavior During Turn-off
t - t
3
i (t)
R
P+
-
+
++
interval
4
N
N+
-
•
V - 1.0 V
j
C
Rd
sc
L
Rd i ncr eases as ex cess
car r i er s ar e r emov ed v i a
r ecombi nat i on and car r i er
sweep- out ( negat i v e cur r ent ) .
time
time
time
•
di R
V r = I r r Rd + L
dt
x
•
t s i nt e r v a l
Insuf f i ci e nt e x ce ss car r i e r s r e m ai n t o sup p o r t I r r , so
P+ N- j unct i o n b e co m e s r e v e r se - b i ase d and cur r e nt
d e cr e ase s t o ze r o .
•
V o l t ag e d r o p s f r o m V r r t o V R as cur r e nt d e cr e ase s
t o ze r o . Ne g at i v e cur r e nt i nt e g r at e d o v e r i t s t i m e
d ur at i o n r e m o v e s a t o t al char g e Qr r .
Copyright © by John Wiley & Sons 2003
Diodes - 13
Factors Effecting Reverse Recovery Time
diR
diR t rr
• Irr =
t =
; Defined on
dt 4
dt ( S + 1 )
swit ching wav eform diagram
Irr t rr
diR
t rr 2
• Qrr =
=
; Defined
2
dt 2 ( S + 1 )
on wav eform diagram
• If st ored charge remov ed most ly
by sweep-out Qrr - QF - IF 
• Using t his in eqs. for Irr and t rr
and assuming S + 1 - 1 giv es
t rr =
2 IF 
and
diR
dt
• Inv ert ing Qrr equat ion t o solv e for t rr y ields
t rr =
2 Qrr ( S+ 1 )
diR
dt
and Irr =
Copyright © by John Wiley & Sons 2003
diR
2 Qrr
dt
(S + 1)
Irr =
diR
2 IF 
dt
Diodes - 14
Carrier Lifetime-Breakdown Voltage Tradeoffs
Conclusions
• Low on-state losses require
kT

q [µ n + µ p ]
L = W d • W(V) = 10 -5 BVBD
L=
D  =
• Solving for the lifetime yields
Wd 2
=
= 4x10 -12 (BV BD) 2
(kT/q) [µ n+µ p ]
• Substituting for
 in I rr and t rr equations gives
• t rr = 2.8x10 -6 BVBD
• Irr = 2.8x10 -6 BVBD
Copyright © by John Wiley & Sons 2003
IF
(di R/dt)
1.
Higher breakdown v olt ages
require larger lifet imes if low
on-st at e losses are t o be
maint ained.
2.
High breakdown v olt age
dev ices slower t han low
breakdown v olt age
dev ices.
3.
Turn-off t imes short ened
diR
by large
but Irr is
dt
increased.
di R
IF
dt
Diodes - 15
Schottky Diodes
anode
Charact erist ics
• V( on) = 0 .3 - 0 .5 v olt s.
SiO2
P
P
• Breakdown v olt ages
Š 1 0 0 -2 0 0 v olt s.
• Majorit y carrier dev ice - no
st ored charge.
guard
ring
depletion layer
boundary with
guard rings
N
• Fast swit ching because of lack
of st ored charge.
depletion layer
boundary
without guard
rings
N+
cathode
Copyright © by John Wiley & Sons 2003
aluminum
contact rectifying
aluminum
contact ohmic
Diodes - 16
Physics of Schottky Diode Operation
• Elect rons diffuse from Si t o Al
because elect rons hav e larger
av erage energy in silicon
compared t o aluminum.
• Deplet ion lay er and t hus pot ent ial
barrier set up. Giv es rise t o
rect ify ing cont act .
• No hole inject ion int o silicon. No
source of holes in aluminum. Thus
diode is a majorit y carrier dev ice.
• Rev erse sat urat ion current much
larger t han in pn junct ion diode.
This leads t o smaller V( on) ( 0 .3 0 .5 v olt s)
Copyright © by John Wiley & Sons 2003
+ V i(t)
n-type Si
Aluminum
Electron Energy
E
E
Al
Al
Diffusing
electrons
-
+
+
+
Si
N-Si
Depletion layer
Diodes - 17
Schottky Diode Breakdown Voltage
• Breakdown v olt age limit ed t o
1 0 0 -2 0 0 v olt s.
• Narrow deplet ion region
widt hs because of heav ier
drift region doping needed for
low on-st at e losses.
• Small radius of curv at ure of
deplet ion region where
met allizat ion ends on surface
of silicon. Guard rings help t o
mit igat e t his problem.
• Deplet ion lay er forms right at
silicon surface where
maximum field needed for
breakdown is less because of
imperfect ions, cont aminant s.
Copyright © by John Wiley & Sons 2003
Diodes - 18
Schottky Diode Switching Waveforms
• Schot t ky diodes swit ch much
fast er t han pn junct ion diodes. No
minorit y carrier st orage.
Current
I
• Foreward v olt age ov ershoot V FP
much smaller in Schot t ky diodes.
Drift region ohmic resist ance R
• Rev erse recov ery t ime t rr much
smaller in Schot t ky diodes. No
minorit y carrier st orage.
• Rev erse recov ery current Irr
comparable t o pn junct ion diodes.
space charge capacit ance in
Schot t ky diode larger t han in pn
junct ion diode becasue of
narrower deplet ion lay er widt hs
result ing from heav ier dopings.
Copyright © by John Wiley & Sons 2003
F
t
V
FP
V(on)
t
voltage
C(Schottky) - 5 C(PN)
R (Sch.) << R (pn)

Diodes - 19
Ohmic Contacts
• Elect rons diffuse from Al int o pt y pe Si becasue elect rons in Al
hav e higher av erage energy .
• Elect rons in p-t y pe Si form an
accumulat ion lay er of great ly
enhanced conduct iv it y .
• Cont act pot ent ial and rect ify ing
junct ion complet ely masked by
enhanced conduct iv it y . So-called
ohmic cont act .
• In N+ Si deplet ion lay er is v ery
narrow and elect ric fields approach
impact ionizat ion v alues. Small
v olt ages mov e elect rons across
barrier easily becasue quant um
mechanical t unneling occurs.
Copyright © by John Wiley & Sons 2003
Electron Energy
E
Al
E
Si
Accumulation layer
i(t)
Al
-
P-Si or
N+-Si
Diffusing
electrons
Diodes - 20
PN Vs Schottkys at Large BVBD
• Minorit y carrier drif t region
relat ionships
q [ µn + µp ] na A V d
• IF Wd
• Maximum pract ical v alue of na = 1 0 1 7
cm-3 and corresponding t o
µn + µp = 9 0 0 cm2 / ( V-sec)
• Desired breakdown v olt age requires
Wd • 1 0 -5 BV BD
IF
Vd
= 1 .4 x1 0 6
A
BV BD
• Majorit y carrier drif t region
relat ionships
q [ µn + µp ] Nd A V d
•
IF Wd
Copyright © by John Wiley & Sons 2003
•
Desired breakdown v olt age
1 .3 x1 0 1 7
and
requires Nd =
BV BD
Wd • 1 0 -5 BV BD
• Large BV BD ( 1 0 0 0 V) requires Nd
= 1 0 1 4 cm-3 where µn + µp =
1 5 0 0 cm2 / ( V-sec)
Vd
IF
6
- 3 .1 x1 0
•
A
[ BV BD] 2
• Conclusion: Minorit y carrier
dev ices hav e lower on-st at e
losses at large BV BD.
Diodes - 21
PSPICE Built-in Diode Model
• Components
• Circuit diagram
i
+
diode
•
Cj - nonlinear space-charge capacitance
•
Cd - diffusion capacitance. Caused by excess
+
v
Cj
diode
v
j
C
d
carriers. Based on quasi-static description of
stored charge in drift region of diode.
i (v )j
dc
-
•
Current source idc(vj) models the exponential
I-V characteristic.
•
Rs accounts for parasitic ohmic losses at high
Rs
v
= v +j R i
diode
s diode
Copyright © by John Wiley & Sons 2003
currents.
Diodes - 22
Stored Charge in Diode Drift Region - Actual
Versus Quasi-static Approximation
• One dimensional diagram of a
power diode.
• Quasistatic view of decay of
excess carrier distribution
during diode turn-off.
n(x,t) = n(x=0,t) f(x)
• Redistribution of excess
carriers via diffusion ignored.
Equ;ivalent to carriers moving
with inifinte velocity.
• Actual behavior of stored
charge distribution during
turn-off.
Copyright © by John Wiley & Sons 2003
Diodes - 23
Example of Faulty Simulation Using Built-in Pspice Diode Model
L
stray
50 nH
D
V
d
100 V
+
I
o
50 A
f
Sw
• Test circuit example - step-down converter.
• PSPICE diode model parameters - (TT=100ns
Cjo=100pF Rs=.004 Is=20fA)
• Diode voltage transient
• Diode current transient.
Copyright © by John Wiley & Sons 2003
Diodes - 24
Improved (lumped-charge) Diode Model
• More accurately model distributed nature
of excess carrier distribution by dividing
it into several regions, each described by
a quasi-static function. Termed the
lumped-charge approach.
N - region
p(x) = n(x)
+
P
region
Q
1

Q
2
Q
4
Q3
N+
region
x
d
• Circuit diagram of improved diode model. Circuit written in
terms of physical equations of the lumped-charge model.
• Detailed equations of model given in subcircuit listing.
• Many other even better (but more complicated models available in
technical literature..
Copyright © by John Wiley & Sons 2003
Diodes - 25
Details of Lumped-Charge Model
Subcircuit Listing
.Subckt DMODIFY 1 9 Params: Is1=1e-6, Ise=1e-40, Tau=100ns,
+Tm=100ns,Rmo=Rs=.001, Vta=.0259, CAP=100p, Gde=.5,
+ Fbcoeff=.5, Phi=1, Irbk=1e20,Vrbk=1e20
*Node 1= anodeand Node 9 = cathode
Dcj 1 2 Dcap ; Included for space charge capacitance and reverse
*breakdown.
.model Dcap D (Is=1e-25 Rs=0 TT=0 Cjo={CAP} M={Gde}
+FC={Fbcoeff} Vj={Phi} +IBV={Irbk} BV=Vrbk})
Gd 1 2 Value={(v(5)-v(6))/Tm +Ise*(exp(v(1,2)/Vta)-1)}
*Following components model forward and reverse recovery.
Ee 5 0 VALUE = {Is1*Tau*(exp(V(1,2)/(2*Vta))-1)}; Ee=Qe
Re 5 0 1e6
Em 6 0 VALUE = {(V(5)/Tm-i(Vsense1))*Tm*Tau/(Tm+Tau)}
*Em=Qm
Rm 6 0 1e6
Edm 7 0 VALUE = {v(6)};Edm=Qm
Vsense1 7 8 dc 0 ; i(vsense1)=dQm/dt
Cdm 8 0 1
Rdm 8 0 1e9
Rs 2 3 4e-3
Emo 3 4 VALUE={2*Vta*Rmo*Tm*i(Vsense2)
+/(v(6)*Rmo+Vta*Tm)}; Vm
Vsense2 4 9 dc 0
.ends
Copyright © by John Wiley & Sons 2003
• Symbolize subcircuit listing into
SCHEMATICS using SYMBOL
WIZARD
• Pass numerical values of
parameters Tau, Tm, Rmo,Rs, etc.
by entering values in PART
ATTRIBUTE window (called up
within SCHEMATICS).
• See reference shown below for
more details and parameter
extraction procedures.
• Peter O. Lauritzen and Cliff L. Ma,
"A Simple Diode Model with
Forward and Reverse Recovery",
IEEE Trans. on Power Electronics,
Vol. 8, No. 4, pp. 342-346, (Oct.,
1993)
Diodes - 26
Simulation Results Using Lumped-Charge Diode Model
Diode voltage and current waveforms
Simulation Circuit
L
stray
50 nH
+
-
V
D
d
100 V
Io
50 A
f
Sw
• Note soft reverse
recovery and forward
voltage overshoot.
Qualitatively matches
experimental
measurements.
Copyright © by John Wiley & Sons 2003
Diodes - 27