Download I - Clarkson University

An Efficient and Accurate Thermal Model of Silicon-On-Insulator (SOI)
Integrated Circuits
Dave Kopp
Department of Electrical and Computer Engineering
Clarkson University, Potsdam NY 13699-6261
Advisor: Dr. Ming-Cheng Cheng
Department of Electrical and Computer Engineering
Clarkson University, Potsdam NY 13699-5720
Abstract: Silicon-on-insulator (SOI) MOSFET structure with a layer of buried silicon
oxide added to isolate the device body and the silicon substrate can significantly cut down
source and drain depletion capacitances and can dramatically minimize the short channel
effect. However, the low thermal conductivity of the buried oxide (BOX) also causes local
heating, altered electrical properties, changed heat flow down interconnects, and thermal
failure of devices. The existing thermal models that are currently used in circuit simulation
to account for thermal effects do not accurately capture the heat flow in the devices. On the
other hand, more accurate models currently rely on large network circuits or numerical
simulations which do not execute quickly enough for large scale integrated circuit
simulation. The thrust of this project is to develop an approach that is an efficient balance
between speed, accuracy, and adaptability and can be used in large scale simulation. The
approach will incorporate efficient SOI device thermal model with the interconnect thermal
model into integrated circuit simulation, and will offer an accurate and efficient electrothermal simulation tool for large scale SOI integrated circuit structure.
I.
Introduction
The demand for faster and cheaper microelectronic devices has led to an incredible
shrinking of devices and a corresponding increase in component density. This modern
technology brings with it some difficult problems of heat transfer. Thermal power is
produced at many device junctions, and the heat needs to diffuse away from the components,
or the devices would suffer from self-heating heating effects, including degradation of
reliability and electronic performance. Some of these junctions involve appreciable power
dissipation. The oxide of silicon-on-insulator (SOI) structure has a very low thermal
conductivity of approximately 1.4W/m/K, which may be compared with values near
100W/m/K in bulk silicon [1]. Due to the fact that the oxide is buried between the silicon
device body and silicon substrate, self-heating in such SOI structure is substantially
enhanced.
It has been estimated that the mean failure rate in semiconductor devices doubles for
every 10K increase in temperature [2]. Self heating in a device increases device temperature
which enhance impact ionization rate, increase the losses due to leakage current at junctions,
reduce mobility due to stronger scattering, and otherwise alter the electrical characteristics of
a SOI device [3]. In addition, self-heating enhances heat flow from devices to interconnects,
and raises metal-line and chip temperatures, which may lead to strong electromigration in
interconnects [4]-[6]. An increase in temperature in microelectronic devices and
interconnects should be carefully modeled to determine the effects on the electrical and
mechanical parameters and reliability [7] of devices and interconnects .
Lfox
Lfox
LSi
tbox
II.
Thermal Models in SOI Structures
A. Conventional approaches
Thermal analysis in semiconductor devices or interconnects are based on the heat
flow equation given below.
c
T
   (k T )  pd ,
t
(1)
where, k is the thermal conductivity,  is density, c is specific heat, and pd is power density.
In the SOI MOSFET structure shown in Figure 1, because most of potential change appears
(i.e., most of power/heat is generated) near the channel-drain junction, pd can be
approximated by
pd  (
Vds I d
) ( x  x J ) ,
t Si w
(2)
where V ds is the drain-to-source voltage, I d is the drain current, w is the device width, t Si is
the silicon island thickness, and xJ is the location of the channel-drain junction. For boundary
conditions, heat flow into the air is ignored, and heat transfer to the oxide on top of the device
in Figure 1 is assumed negligible [1]. If the length of field oxide (FOX), Lfox, is large enough
(greater than the thermal length in FOX), it can be further assumed that the heat transfer
sidewise is also negligible. These assumptions may be expressed by the adiabatic conditionh
T
 0 , where  represents an outward derivative around the surfaces dotted in Figure 1.

Because of the large thermal conductivity, the temperature of the silicon substrate is taken to
be 300K. In the lightly doped substrate, thermal conductivity ksub  148W / Km , in the thin
silicon island, kSi  63W / Km , and in the oxide, kox  1.4W / Km [8].
Instead of using numerical methods, heat flow in devices based on (1) can actually be
simulated based on the electric circuit analogy [9] [10]. In this analogy, currents represent
power and voltages represent temperature. Quantities akin to resistances and capacitances
may then be defined accordingly, and a table summarizing the analogy [8] is pictured in
Table 1. The detailed parameter definition and interpretation are presented in [8].
Table 1 Analogy between electric and thermal circuits [8]
Charge, Q [C]
Energy, w [J]
Voltage, V [V]
Temperature, T [K]
Current, I [A]=[C/s]
Power, p [W]=[J/s]
Charge flux, J = V [A/m2]
Heat flux, H = kT [W/m2]
Conductivity,  [A/Vm]
Thermal conductivity, k [W/Km]
Capacitance, C [F]=[C/V]
Thermal capacitance, Cth [J/ oC]
Resistance, R  V / I [V/A]
Thermal resistance, Rth  T / P [K/W]
Conductance, G  I / V [A/V]
Thermal conductance, Gth  P / T [W/K]
To avoid the time-consuming numerical approach to solving the heat flow equation in (1) for
the SOI devices, thermal analysis in microelectronics industry is currently based on a
simplified 1D single time constant (STC) thermal circuit with a constant device temperature
built in the BSIMSOI model [3] for SPICE simulation, as given in Figure 2. The current
source in Figure 2 is represented by the I2R heat of the junction. The ground node is taken at
the silicon substrate due to its high relative thermal conductivity. The thermal resistance Rthc
is given by
Rthc 
Tch
t
t
 box  box ,
P
keff Ag keff wLg
(3)
where tbox is the box thickness, eff is the effective BOX thermal conductivity accounting for
2D heat flow from the device channel through FOX and BOX to the substrate, Tch is the
average channel temperature, and Lg is the gate length. Rthc in the single-time constant circuit
describes the heat loss from the device channel through the source/drain and BOX/FOX to
the silicon substrate.
ch
thc
th
Temperature (K)
150
device simulation
device simulation
Analytical model
120
Rint = 0.1mK/W
90
Tint,s=20K
Tint,g=15K
Tint,d=10K
tsi= 40nm
Vds=1.5 V
60
Vds=2.4 V
30
F
F
S C D
O
O
x ( m)
Figure 3 Temperature
profiles above the
X ambient
X
temperature in the silicon film with t = 40nm at V =
0
-1
Figure 2 Single time
constant thermal circuit.
0
1
2
si
gs
1.5V. FOX regions are in x < 0 and x > 1.18m. [1]
This STC thermal circuit given in Figure 2 has only one node, and the temperature at
that node represents an average for the circuit. J. Lin et. al. found in [1] that the temperature
predicted by the STC circuit differed from the temperature simulated using a device
simulator by as much as 20K when the device was stimulated by continual 1GHz pulses [1].
It has also been noted that the temperature in the channel-drain junction is “usually
considerably higher” than the source or drain temperatures [8], as illustrated in Fig. 3. These
temperatures at the source, drain and junction would be considered equal in the STC circuit.
The STC circuit method is a primary means by which large-scale systems of integrated
circuits (ICs) are currently modelled in the industry. This method is extremely easy and
efficient to use on a large-scale basis, but it is evidently not accurate in the SOI MOSFETs.
Because the device failure rate is strongly dependent on the peak temperature instead of the
average one, this implies that the actual mean failure rate in SOI is much higher than
predicted by the STC method. In addition, due to the incorrect source, drain and gate
temperatures resulting from the STC method, the predicted heat flow to interconnects would
not be accurate. This will lead to erroneous temperature distributions and stress in the
interconnects. The device junction temperature and device/interconnect temperature
distributions have strong influences on device and interconnect reliability and characteristics,
and need to be taken into account for design of SOI ICs.
To obtain temperature profiles and transient thermal behavior in semiconductor
devices, numerical approaches are usually used to solve the heat flow equation in (1) with a
large number of grids. This can also be achieved using a circuit network with a large number
of nodes. These approaches are however time consuming and impractical for large-scale IC
simulation. Alternatives would be the approaches splitting an MOSFET into several regions,
as proposed in [1],[8],[11], to capture the peak temperature. However, the number of nodes
has to be small enough to allow efficient simulation for ICs. This project will be focused on
developing efficient and accurate steady-state for ICs. The steady-state model presented in
[8] and [11] will be briefly discussed below.
B. Improved methods for steady-state heat flow problems in SOI MOSFETs
A method has been adopted from [8] and [11] that allows moderately rapid evaluation
of (1) for the steady-state case
  (kT )  pd
(4).
In the silicon thin island using a short-interconnect approximation, it has been shown that (4)
with some appropriate assumption [8] can be reduced to a one dimensional heat flow
equation given (5).
Table 2 Summary of the short-channel interconnect model [8]
TSi  Tint,n TSi  Toeff ,n
 2TSi
TSi



,
Z Si,n
Z Si,int,n
Z eff ,n
x 2
Z Si ,n  Rthf kSi ,n LSi ,n wtSi ,
Z Si,int,n  Rint,n k Si,n Ac ,n t Si ,
(5)
1
Z eff ,n

1
Z Si,n

1
Z int,n
,

Z Si,n
Toeff ,n  
 Z Si,n  Z Si,int,n

Tint,n ,


TSi is the temperature in the silicon film
Tint,n is the temperature at the end of a poly or metal line that extends into region n
Rint,n is the thermal resistance of the interconnect that extends into region n
Rthf is the film thermal resistance that describe heat flow from the film to the substrate
kSi,n is the thermal conductivity of silicon in region n
tSi is the thickness of the silicon film
w is the width of the device
LSi,n is the length of region n in the silicon film
It should be noted that the film thermal resistant Rthf is defined differently from Rthc
given in (3). Rthf is defined as [8]
TSi
Rthf 
P

tbox
kbox ,eff ASi

tbox
,
kbox ,eff wLSi
(6)
where TSi is the average temperature along the silicon thin film, kbox,eff is the effective BOX
thermal conductivity accounting for heat flow from the silicon film through BOX/FOX to the
substrate, and ASi and LSi are the silicon film area and length, respectively.
(5) may then be solved using appropriate boundary conditions following [8] and [11].
Some simple cases yield analytic models in terms of infinite series. For other cases, we
transform (5) into the general matrix equation into the more general tridiagonal matrix
equation
P = GthT,
(7)
which is a generalization of the last line of Table 1, and solve this model instead. The Gth
factor here accounts for thermal conductances for transverse and longitudinal heat flow in the
silicon thin island, BOX/FOX and the interconnects.
If the interconnects are long with respect to the characteristic thermal length int of
the interconnect lines, a long interconnect approach is needed instead. Here, int is given in
Table 3.
Table 3 Characteristic length, int
int 2 
k int
(t ox t int )
k ox,eff
k ox,eff 
 k ox h 


 0.15w 
1
(8)
 k int t 


 k ox w 
  h 
 ln 1   
  w 
0.1
0.66
(9)
kint is the thermal conductivity of the interconnects or poly lines
kox is the thermal conductivity of the oxide
h, w, and t are the height, width, and thickness of the rectangular interconnects,
respectively
In this case, the interconnects cannot be modeled as simple thermal resistors because the heat
flow from the interconnect/poly lines to the surrounding oxide cannot be neglected. Instead,
they must be represented as exponential functions as in [11]. However, upon satisfying the
appropriate boundary conditions, it is found that the tridiagonal matrix equation of (7) is
recovered with the matrix and vector elements accounting for additional heat flow from the
interconnect/poly lines to oxide, and the same form of the equation may be used. It can be
shown that, with int >> Lint, the long-interconnect approach reduces to the short-interconnect
approximation.
III.
Proposed Work
Several problems still persist with the thermal model presented above [8],[11]. One
item is that the Gth elements that describe the devices themselves are intermixed with the
elements that describe the interconnects. This is highly undesirable for large-scale IC
simulation because Gth is dependent on the interconnect layout. Each time the user would
input a new IC structure, and new matrix elements would need to be constructed. For the
simple current mirror in [11], this is acceptable, but the difficulty becomes greater as the
number of elements increases. In addition, the joule heat in the interconnect metal lines is
not considered in the model described in Section II, which is reasonable for a small circuit,
such as the current mirror structure in [11] where the 2 SOI devices are placed in close
proximity. For IC structure with long or high density interconnect lines, joule heat induced in
the metal lines must be included to predict more accurate temperature distributions.
The first thrust of this proposal is to streamline the model so that it may be
implemented on a larger scale. The device and interconnect matrix equations describing the
heat flow in devices and interconnects, respectively, need to be separated so that a user can
modify elements in the interconnect matrices/vectors without change any element in the
device matrices/vectors. Interface temperatures between devices and interconnects have to be
properly assigned and evaluated to adequately handle the heat flow between interconnects
and devices. The joule heating in the interconnects will be implemented in the interconnect
matrices and vectors. A user interface simplifying the entry of interconnect matrix/vector
elements based on the IC layouts may be designed. The ultimate goal is to develop an
algorithm to assign the interconnect matrix elements automatically based VLS layouts.
The second aim of the proposal is to create a proof-of-concept system illustrating that
the steady-state model functions on a large scale. A sufficiently large SOI IC will be
designed. The developed model for the SOI IC will be coupled together with the SPICE
circuit simulator to carry out the electrothermal simulation. The developed model will be
compared to 3D commercial device and interconnect simulators to demonstrate the validity
and efficiency of the model.
This model, when it is implemented, will offer an efficient tool for accurate thermal
simulation in SOI devices and contribute to the development of SOI-based circuits.
References
Cheng M-C, Yu F, Jun L, Shen M, Ahmadi G. “Steady-state and dynamic thermal
models for heat flow analysis of silicon-on-insulator MOSFETs,” in Microelectronics
Reliability Vol. 44, 2004; pp. 381-396.
[2] Lin J, Shen M, Cheng M-C, Glasser M. “Efficient thermal modeling of SOI MOSFETs
for fast dynamic operation” in IEEE Transactions of Electronic Devices, Vol. 51, No.
10, Oct-2004; pp. 1659-1666.
[3] Yu F, Cheng M-C. “Application of heat flow models to SOI current mirrors” in SolidState Electronics, Vol. 48, 2004; pp. 1733-1739.
[4] Bar-Cohen, Avram. “Thermal Management of Electronics” in The Electrical
Engineering Handbook, CRC Press LLC, 2000, pp. 890-904.
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[7] BSIM Group. BSIMSOI3.1 Mosfet Model, Feb-2003, pp. 5.1-5.2.
At
http://www.device.eecs.berkeley.edu/~bsimsoi.
[8] D.S. Peck, “The analysis of data from accelerated tests,” Proc. 9th Reliability Phys.
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[10] W. Wu, S.H. Kang, J.S. Yuan, A.S. Oates, Thermal effect on electromigration
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