Op-Amp Circuits
... Steps in Analyzing Op-Amp Circuits 1) Remove the op-amp from the circuit and draw two circuits (one for the + and one for the – input terminals of the op amp). 2) Write equations for the two circuits. 3) Simplify the equations using the rules for op amp analysis and solve for Vout/Vin Why can the o ...
... Steps in Analyzing Op-Amp Circuits 1) Remove the op-amp from the circuit and draw two circuits (one for the + and one for the – input terminals of the op amp). 2) Write equations for the two circuits. 3) Simplify the equations using the rules for op amp analysis and solve for Vout/Vin Why can the o ...
11 mW Power, 2.3 V to 5.5 V, Complete DDS AD9838
... Phase Select Input. PSELECT controls which phase register, PHASE0 or PHASE1, is added to the phase accumulator output. The phase register to be used can be selected using the PSELECT pin or the PSEL bit. When the PSEL bit is used to select the phase register, the PSELECT pin should be tied to CMOS h ...
... Phase Select Input. PSELECT controls which phase register, PHASE0 or PHASE1, is added to the phase accumulator output. The phase register to be used can be selected using the PSELECT pin or the PSEL bit. When the PSEL bit is used to select the phase register, the PSELECT pin should be tied to CMOS h ...
Features
... power when compared to the original PLD or FPGA. This is especially true when compared to many PLD and CPLD architecture devices, which typically consume 100mA or more even when not being clocked. The UA1E series has a very low standby consumption of 0.3nA/gate typically commercial temperature, whic ...
... power when compared to the original PLD or FPGA. This is especially true when compared to many PLD and CPLD architecture devices, which typically consume 100mA or more even when not being clocked. The UA1E series has a very low standby consumption of 0.3nA/gate typically commercial temperature, whic ...
MAX5741 10-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface General Description
... or brought high. CS must be brought high for a minimum of 80ns before the next write sequence, since a write sequence is initiated on a falling edge of CS. Not keeping CS low during the first 15 SCLK cycles discards input data. The serial clock (SCLK) can idle either high or low between transitions. ...
... or brought high. CS must be brought high for a minimum of 80ns before the next write sequence, since a write sequence is initiated on a falling edge of CS. Not keeping CS low during the first 15 SCLK cycles discards input data. The serial clock (SCLK) can idle either high or low between transitions. ...
MAX14954 Ruggedized Quad PCIe Redriver with Equalization and Extended Temperature Operation General Description
... Lead Temperature (soldering, 10s).................................. +300°C Soldering Temperature (reflow)........................................+260°C ...
... Lead Temperature (soldering, 10s).................................. +300°C Soldering Temperature (reflow)........................................+260°C ...
AN1775 APPLICATION NOTE STR71x Hardware Development Getting Started
... a 1.8V supply to the chip through the V18BKP pin for use by RTC and Wake-Up block. In this case we must to keep the 3.3V on pin V33 even if the two regulators are switch off to keep stable state on the I/Os. Remark:The PLL is automatically disabled (PLL off) when the MVR is switched off and the maxi ...
... a 1.8V supply to the chip through the V18BKP pin for use by RTC and Wake-Up block. In this case we must to keep the 3.3V on pin V33 even if the two regulators are switch off to keep stable state on the I/Os. Remark:The PLL is automatically disabled (PLL off) when the MVR is switched off and the maxi ...
LT6108-1/LT6108-2 - High Side Current Sense Amplifier with Reference and Comparator
... Amplifier Output Short-Circuit Duration (to V–)... Indefinite Operating Temperature Range (Note 3) LT6108I.................................................–40°C to 85°C LT6108H............................................. –40°C to 125°C Specified Temperature Range (Note 3) LT6108I................ ...
... Amplifier Output Short-Circuit Duration (to V–)... Indefinite Operating Temperature Range (Note 3) LT6108I.................................................–40°C to 85°C LT6108H............................................. –40°C to 125°C Specified Temperature Range (Note 3) LT6108I................ ...
FEATURES GENERAL DESCRIPTION
... portable devices. The LDO maintains a power supply rejection of greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage. Each regulator is activated by a high level on the respective enable pin. The ADP5043 is available with factory programmable default outpu ...
... portable devices. The LDO maintains a power supply rejection of greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage. Each regulator is activated by a high level on the respective enable pin. The ADP5043 is available with factory programmable default outpu ...
MAX3171/MAX3173 +3.3V Multiprotocol 3Tx/3Rx Software-Selectable Control Transceivers General Description
... +3.3V supply. The MAX3171/MAX3173, along with the MAX3170 and MAX3172/MAX3174, form a complete software-selectable data terminal equipment (DTE) or data communications equipment (DCE) interface port that supports V.28 (RS-232) and V.10/V.11 (RS-449, V.36, EIA-530, EIA-530-A, X.21, RS-423) protocols. ...
... +3.3V supply. The MAX3171/MAX3173, along with the MAX3170 and MAX3172/MAX3174, form a complete software-selectable data terminal equipment (DTE) or data communications equipment (DCE) interface port that supports V.28 (RS-232) and V.10/V.11 (RS-449, V.36, EIA-530, EIA-530-A, X.21, RS-423) protocols. ...
EPM7064AELI44-7 WORD
... speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 7000E and MAX 7000S devices also provide an opt ...
... speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 7000E and MAX 7000S devices also provide an opt ...
AXIMA 2000/4000 Installation Manual
... The AC power connects to a removable connector on the top of the AXIMA 2000/4000 chassis. The AC power input must be between 96 and 264 VAC, single phase, and 50 to 60 Hertz. At 115 VAC, 1.0 amps RMS is required, or at 230 VAC, 0.5 amps RMS is required. However, at power-up the logic supply has an i ...
... The AC power connects to a removable connector on the top of the AXIMA 2000/4000 chassis. The AC power input must be between 96 and 264 VAC, single phase, and 50 to 60 Hertz. At 115 VAC, 1.0 amps RMS is required, or at 230 VAC, 0.5 amps RMS is required. However, at power-up the logic supply has an i ...
MAX 7000
... speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 7000E and MAX 7000S devices also provide an opt ...
... speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 7000E and MAX 7000S devices also provide an opt ...
Eddystone Broadcast ---- XE35/75/150/300 Series 35
... Mono) the modulator and associated frequency synthesiser, the main hardware control and monitor microprocessor and all connections to other boards, modules and options within the Exciter. The associated Input/Output Board connects to a socket on the Main Board and carries all the parallel and RS232 ...
... Mono) the modulator and associated frequency synthesiser, the main hardware control and monitor microprocessor and all connections to other boards, modules and options within the Exciter. The associated Input/Output Board connects to a socket on the Main Board and carries all the parallel and RS232 ...
SP3203E 数据资料DataSheet下载
... The SP3203E provides a RS-232 transceiver solution for portable and hand-held applications such as palmtops, PDA's and cell phones. The SP3203E uses an internal high-efficiency, charge-pump power supply that requires only 0.1µF capacitors during 3.3V operation. This charge pump and Exar's driver arc ...
... The SP3203E provides a RS-232 transceiver solution for portable and hand-held applications such as palmtops, PDA's and cell phones. The SP3203E uses an internal high-efficiency, charge-pump power supply that requires only 0.1µF capacitors during 3.3V operation. This charge pump and Exar's driver arc ...
MAX11156 18-Bit, 500ksps, ±5V SAR ADC with Internal Reference in TDFN General Description
... Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Expo ...
... Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Expo ...
18-Bit, 1-MSPS Data Acquisition (DAQ) Block Optimized for Lowest
... helpful from the amplifier stability perspective, but higher values of RFLT add distortion due to interactions with the non-linear input impedance of the ADC. The distortion increases with source impedance, input signal frequency, and input signal amplitude; therefore, the selection of RFLT requires ...
... helpful from the amplifier stability perspective, but higher values of RFLT add distortion due to interactions with the non-linear input impedance of the ADC. The distortion increases with source impedance, input signal frequency, and input signal amplitude; therefore, the selection of RFLT requires ...
DS1339 I C Serial Real-Time Clock
... comparator circuit that monitors the VCC level. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If VPF is less than VBACKUP, the device power is switched from VC ...
... comparator circuit that monitors the VCC level. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If VPF is less than VBACKUP, the device power is switched from VC ...
GENERAL DESCRIPTION FEATURES
... should not be placed in series between the backup source and the VBACKUP input, or improper operation will result. If a backup supply is not required, VBACKUP must be grounded. UL recognized to ensure against reverse charging current when used with a lithium cell. For more information, visit www.max ...
... should not be placed in series between the backup source and the VBACKUP input, or improper operation will result. If a backup supply is not required, VBACKUP must be grounded. UL recognized to ensure against reverse charging current when used with a lithium cell. For more information, visit www.max ...
BX-35 Lynx Panel Meter 3 1/2 DIGIT 0.56” LED
... but the display will not be updated until Pin 9 is disconnected from Pin 11. Pin 10 - Display Test: When this pin is connected to the Common Pin 11, all segments of the display light up and 1888 is displayed. This is used to detect any missing segments in the display. Page 2 ...
... but the display will not be updated until Pin 9 is disconnected from Pin 11. Pin 10 - Display Test: When this pin is connected to the Common Pin 11, all segments of the display light up and 1888 is displayed. This is used to detect any missing segments in the display. Page 2 ...
ADM690 数据手册DataSheet 下载
... capacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the watchdog timeout period (see Table I and Figure 4). With OSC SEL high or floating, the internal oscillator is enabled and the reset active time is fixed at 50 ms typ. (ADM691/ADM693) or 200 ms typ ...
... capacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the watchdog timeout period (see Table I and Figure 4). With OSC SEL high or floating, the internal oscillator is enabled and the reset active time is fixed at 50 ms typ. (ADM691/ADM693) or 200 ms typ ...
ST7LNB0V2Y0
... microcontroller specifications version 1.0, the ST7LNB0V2Y0 does not scan the control pins in order to determine the slave configuration. Instead all configuration parameters must be programmed for each specific application, and an option list (see Section 8: Device configuration) must be filled-in ...
... microcontroller specifications version 1.0, the ST7LNB0V2Y0 does not scan the control pins in order to determine the slave configuration. Instead all configuration parameters must be programmed for each specific application, and an option list (see Section 8: Device configuration) must be filled-in ...
MAX9814 - Part Number Search
... period before slowly increasing to the normal value. This process is known as the hold and release time. The speed at which the amplifiers adjust to changing input signals is set by the external timing capacitor CCT and the voltage applied to A/R. The AGC threshold can be set by adjusting VTH. Gain ...
... period before slowly increasing to the normal value. This process is known as the hold and release time. The speed at which the amplifiers adjust to changing input signals is set by the external timing capacitor CCT and the voltage applied to A/R. The AGC threshold can be set by adjusting VTH. Gain ...
Flip-flop (electronics)
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary digit) of data; one of its two states represents a ""one"" and the other represents a ""zero"". Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.