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Transcript
AN1775 APPLICATION NOTE STR71x Hardware Development Getting Started Introduction This application note is intended for system designers who require a hardware implementation overview of the development board features such as the power supply, the clock management, the reset control, the boot mode settings and the debug management. It shows how to use the STR71x product family and describes the minimum hardware resources required to develop an STR71x application. Detailed reference design schematics are also contained in this document with descriptions of the main components, interfaces and modes. Rev 3 1/27 October 2005 www.st.com www.BDTIC.com/ST 27 AN1775 Contents 1 2 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Power management block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Clock control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 USB clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.1 Hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Boot management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 5.1 ICE debug tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2 JTAG / ICE connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 Main . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1.4 Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3 USB full speed interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.4 CAN interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.5 RS232 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6 Serial ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6.1 SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6.2 I2C EEPROM: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.7 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.8 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/27 www.BDTIC.com/ST AN1775 7 6.9 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.10 LCD interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.11 Conclusions and recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3/27 www.BDTIC.com/ST AN1775 1 Power management 1 Power management 1.1 Overview The chip is powered by an external 3V3 supply(V33: 2.7 to 3.6 V, AVDD: 3.0 to 3.6 V). All I/Os are 3V3-capable. An internal Voltage Regulator generates the supply voltage for core logic (~=1.8V). The two V18 pins must be connected to external stabilization capacitors. The following figure indicates the recommended configuration for the power supply pins: Figure 1. STR71x power supply pins STR71x 3V3 V33 V33IO-PLL V18 33nF 10µF GND VSSIO-PLL VSS VSSBKP GND 1µF V18BKP GND 1.2 Power management block The following figure describes the power management block implemented on the STR71x devices. Figure 2. Power Management Block 3V3 3.3 V I/O circuitry V33 Main Voltage Regulator (MVR) V18 Low Power Voltage Regulator (LPVR) 1.8 V CORE 10µF 33nF GND V18BKP switch see note 1 1µF Backup block GND The STR71x power management block has two regulators: ● The Main Voltage Regulator MVR. ● The Low Power Voltage Regulator LPVR. Note the following remarks about the two regulators: ● Both regulators can be switched-off by software 4/27 www.BDTIC.com/ST AN1775 1 Power management ● V18 can be used to supply an externally regulated 1.8V, but V33 must supply the IOs ● V18BKP pin can be used to externally supply the backup logic, but V33 must supply the IOs ● The switch in Figure 2, opened only during STANDBY mode, disconnects the V18 domain from the V18BKP domain It is possible to switch-off the MVR and keep LPVR on when the device is in low-power mode (SLOW, WFI, LPWFI, STOP or STANDBY). The LPVR has a different design from the main VR and generates a non-stabilized and non-thermally-compensated voltage of approximately 1.6V. In STANDBY mode the Low Power VR can be switched off when an external regulator provides a 1.8V supply to the chip through the V18BKP pin for use by RTC and Wake-Up block. In this case we must to keep the 3.3V on pin V33 even if the two regulators are switch off to keep stable state on the I/Os. Remark:The PLL is automatically disabled (PLL off) when the MVR is switched off and the maximum allowed operating frequency is 1 MHz. This is due to the limitation imposed by the LPVR which is not able to generate sufficient current to operate in run mode. The MAIN DEVICE CORE is powered from an external 3V3 power supply pin (V33) through the main regulator. For more details on the power regulators, refer to the STR71x Reference Manual. 5/27 www.BDTIC.com/ST AN1775 2 Clock management 2 Clock management The STR71x offers a flexible way for selecting core and peripherals clocks, the devices have up to 3 external clock sources: 2.1 ● The PRCCU generates the internal clocks for the CPU and for the on-chip peripherals. The PRCCU may be driven by an external pulse generator, connected to the CK pin. ● The Real time Clock 32kHz oscillator is connected to the internal CK_AF signal (if present on the application), and this clock source may be selected when low power operation is required. ● USB clock source available only with devices with USB feature. Clock control unit The STR71x clock control unit must be driven by an external oscillator, connected to the CK pin, at a frequency of up to 16 MHz. It generates the clocks for the CPU and for the on-chip peripherals. A range of available multiplication and division factors allows for a large number of operating clock frequencies to be driven from the input frequency. However, great care must be taken to respect the recommendations for allowed frequency limits. For more details on allowed operating frequencies for each clock, refer to the Reference Manual. The following diagram shows the basic implementation of the main external clock. Figure 3. Main clock oscillator OSCILLATOR STR71x 33 CK 10K 3V3 VSS GND GND The following table gives frequency range examples of the Main clock for some input clock values: 2.2 Input Clock MCLK (Main Clock) Range 4 MHz [15625 Hz, 50 MHz] 8 MHz [31250 Hz, 50 MHz] 16 MHz [62500 Hz, 50MHz] Real Time Clock The Real Time Clock operates at a speed of 32 kHz. This clock must be provided by an external resonator circuitry. The RTC is used to generate a time base, and can be selected when low power operation is needed. Refer to the Reference Manual for more details. 6/27 www.BDTIC.com/ST AN1775 2 Clock management Figure 4. RTC oscillator STR71x 32kHz CRYSTAL 15pF* RTCXTI RTCXTO 15pF* VSS GND GND * these values are given only as examples, refer to the crystal manufacturer for more details 2.3 USB clock STR710 and STR711 series microcontrollers contain a USB 2.0 Full Speed device module interface that operates at a precise frequency of 48 MHz. This clock is usually provided by an external oscillator connected to the USB clock pin USBCLK. However, to save the board’s space and cost, the 48MHz USB clock can also be generated by the internal PLL2 using one single external oscillator for both system and USB module. This part of the application note describes the hardware and software reference implementation. USB Full Speed signal quality and jitter results can be measured using a single external oscillator to generate not only the System PLL clock and Peripheral’s clocks, but also the 48MHz USB clock. 2.3.1 Hardware implementation The hardware implementation guidelines are described in the figure below. 7/27 www.BDTIC.com/ST AN1775 2 Clock management Figure 5. USB clock and pins implementation V33 47K USB Indicate 56K BC547E GND 56K STR710/STR711 GND GPIO GND 1K5 GPIO 0 Ohm Vbus 15pF DP D+ USB connector D- DM 0 Ohm 15pF GND VSS GND V33 56K 48MHz Oscillator USB CLK GND USB full speed interface device supported via type B connector. The USB clock uses a separate 48 MHz oscillator. Transistor circuit used to indicate the cable status (Cable connected USB/IND pin = 0 logic, Cable deconnected = USB/IND pin = 1 logic). 8/27 www.BDTIC.com/ST AN1775 3 3 Reset management Reset management Both the Main Voltage Regulator and the Low Power Voltage Regulator contain an LVD. They keep the device under reset when the corresponding controlled voltage value (V18 or V18BKP falls below 1.35V±10%). The LVDs do not monitor V33 which supplies the I/O and analog parts of the device. During power-on, a reset must be provided externally. At power on, the nRSTIN pin must be held low by an external reset circuit until V33. Figure 6 gives an example of the hardware implementation of the RESET circuit for STR71x devices. ● The STM1001 low-power CMOS microprocessor supervisory circuit is used to assert a reset signal whenever the V33 voltage falls below a preset threshold or a manual reset is asserted. Figure 6. Hardware reset implementation STR71x V33 +3V3 +3V3 1 not Reset nRSTIN VSS GND +3V3 +3V08 STM1001T 2K2 Reset_PB Note: 1nF VCC 2 GND 3 GND GND * these values are given only as typical example 9/27 www.BDTIC.com/ST AN1775 4 Boot management 4 Boot management Three different boot modes are available and can be enabled by means of three input pins: BOOTEN, BOOT0 and BOOT1. The following table describes the different boot mode configurations. BOOTEN BOOT0 BOOT1 BOOT Mode 0 x x 1 0 0 1 1 0 Reserved 1 0 1 RAM: boot from internal RAM memory 1 1 1 EXTMEM: boot from external memory mapped on the EMI interface at 0000 0000h address. USER: boot from internal FLASH memory The following figure gives an implementation example of boot management for STR71x devices. BOOT0 and BOOT1 are alternate function pins used for boot configuration during the RESET phase (floating-input configuration), so they can be used afterwards in the application as standard I/Os. For more details concerning boot configuration, refer to the device reference manual. Figure 7. Boot mode selection implementation example STR71x 3V3 3V3 10K* BOOTEN 3V3 nSTDBY 10K* GND 10K* BOOT0 3V3 10K* GND BOOT1 TEST GND GND * these values are given only as typical example Note: 1 As the nSTDBY pin has a floating input configuration, an external pull-up has to be provided to avoid remaining in stand-by mode. 2 The TEST pin of the STR71x must always be forced to ground (ST reserved test pin) 10/27 www.BDTIC.com/ST AN1775 5 5 Debug management Debug management The Host/Target interface is the hardware equipment that connects the Host to the application board. This interface is made of three components: a hardware debug tool, such as Micro-ICE from ARM, a JTAG connector and a cable connecting the host to the debug tool. Figure 8 shows the connection of the host to the STR71x board. Figure 8. Host to board connection ICE Debug tool ICE connector HOST PC STR71x BOARD 5.1 Power Supply ICE debug tool ICE Debug tool is a host interface that connects a PC to an STR71x development board featuring a debug interface as shown in Figure 8. The Embedded ICE is an intelligent host interface that provides fast access to host services, access to on-chip emulation and debug facilities. When you are using the ST7R71x board as stand-alone system, the ICE Debug tool can be used to download programs. The STR71x development kit supports the ARM RealView ICE Micro Edition. The Micro-ICE is plugged in to the host via a USB cable. 5.2 JTAG / ICE connector The ICE connector enables JTAG hardware debugging equipment, such as RealView-ICE, to be connected to the ST7R71x board. It is possible to both drive and sense the system-reset line, and to drive JTAG reset to the core from the ICE connector. The Figure 9 shows the ARM ICE connector pin-out. The STR71x has a user debug interface. This interface contains a five-pin serial interface conforming to JTAG, IEEE standard 1149.1-1993, “Standard Test Access Port-Scan Boundary Architecture”. JTAG allows the ICE device to be plugged to the board and used to debug the software running on the STR71x. JTAG emulation allows the core to be started and stopped under control of the connected debugger software. The user can then display and modify registers and memory contents, and set break and watch points. 11/27 www.BDTIC.com/ST AN1775 5 Debug management Figure 9. Ice connector implementation 3V3 JTAG Connector CN9 CONN_2*10 RA_IDC 3V3 3V3 STR71x (1) VTref (3) nTRST (5) TDI (7) TMS (9) TCK (11) RTCK (13) TDO (15) nSRST (17) DBGRQ (19) DBGACK** nJTRST JTDI JTMS JTCK JTDO nRSTIN DBGRQS 10K* 10K* See GND GND J4 Note 1 J4 3V3 GND 10K* GND 22K 10K 47K (2) (4) (6) (8) (10) (12) (14) (16) (18) (20) TR1 BC846 GND 50v 10nF TR2 BC846 GND GND GND * these values are given only as typical example ** The Debug acknowledge to JTAG equipment (DBGACK pin) is not used. Note: 1 In order for JTAG and Chip Reset to be synchronized the J4 jumper must be fitted. 2 STR71x has a Debug Request (DBGRQS) pin, on 144-pin packages only. This active high signal can be used to force the core to enter Debug Mode, giving the Emulation system access to internal resources (code, registers, memory, etc). This pin must be kept LOW when emulation is not being used. The following table describes the JTAG connector pins: Std Name STR71x nTRST JTRST Test Reset (from JTAG equipment) This active LOW open-collector is used to reset the JTAG port and the associated debug circuitry. It is asserted at power-up by each module, and can be driven by the JTAG equipment. TDI JTDI Test data in (from JTAG equipment) TDI goes down the stack of modules to the motherboard and then back up the stack, labelled TDO, connecting to each component in the scan chain. JTMS Test mode select (from JTAG equipment) TMS controls transitions in the tap controller state machine. TMS connects to all JTAG components in the scan chain as the signal flows down the module stack. JTCK TCK synchronizes all JTAG transactions. TCK connects to all JTAG components in the scan chain. Series termination resistors are used to reduce reflections and maintain good Test clock (from signal integrity. TCK flows down the stack of modules and JTAG connects to each JTAG component. However, if there is a equipment) device in the scan chain that synchronizes TCK to some other clock, then all down-stream devices are connected to the RTCK signal on that component. TMS TCK Description Function 12/27 www.BDTIC.com/ST AN1775 5 Debug management Std Name RTCK TDO nSRST DBGRQ STR71x Description Return TCK (to GND JTAG (not used) equipment) JTDO nRSTIN Function Some devices sample TCK (for example a synthesizable core with only one clock), and this has the effect of delaying the time that a component actually captures data. Using a mechanism called adaptive clocking, the RTCK signal is returned by the core to the JTAG equipment, and the clock is not advanced until the core had captured the data. In adaptive clocking mode, the debugging equipment waits for an edge on RTCK before changing TCK. Test data out (to JTAG TDO is the return path of the data input signal TDI. equipment) System reset (bidirectional) DBGRQS Debug request (not used (from JTAG w/ 64pin) equipment) Debug GND acknowledge DBGACK (not used) (to JTAG equipment) nSRST is an active LOW open-collector signal that can be driven by the JTAG equipment to reset the target board. Some JTAG equipment senses this line to determine when a board has been reset by the user. When the signal is driven LOW by the reset controller on the core module, the motherboard resets the whole system by driving nSYSRST low. DBGRQ is a request for the processor core to enter debug state. DBGACK indicates to the debugger that the processor core has entered debug mode. For more details on the JTAG port refer to the IEEE standard 1149.1-1993, “Standard Test Access Port-Scan Boundary Architecture” specification. 13/27 www.BDTIC.com/ST AN1775 6 Reference Design 6 Reference Design 6.1 Main This reference design is based on the STR710FZ2T6, a highly integrated microcontroller, running at 48 MHz that combines the popular ARM7TDMITM 32-bit RISC CPU with 256 Kbytes of embedded flash, 64 Kbytes of high speed SRAM, and numerous on-chip peripherals. 6.1.1 6.1.2 Clock ● +3.3 V surface mounted 16 MHz oscillator provides the main clock source: S113, please refer to Section 2.1 on page 6 for more details. ● RTC real-time clock for wakeup from standby mode with 32 KHz crystal: Y101, please refer to Section 2.2 on page 6 for more details. Reset One push button S112 is used to generate a hardware reset, please refer to Section 3 on page 9 for more details. 6.1.3 Boot mode Three switches S108, S109 and S110 are used to select the boot Mode, please refer to Section 4 on page 10 for more details. 6.1.4 Wake-Up S111 push button is used to exit from STANDBY mode (power supply voltage removed except Real time Clock). For more details, please refer to the STR71x reference manual. 6.2 Power supplies Power to the board is supplied using a power supply providing 5 V DC to the board. All other required voltages are provided by the on-board voltage regulator 3V3 LD1085V33 and Zener Diode LM4040 for ADC input voltage. For more details, refer to LD1085V33, LM4040 datasheets and Section 1 on page 4. 6.3 USB full speed interface USB full speed interface device supported via type B connector. The USB clock uses a separate 48 MHz oscillator. A transistor circuit is used to indicate the cable status (Cable connected USB/IND pin = 0 logic, Cable deconnected = USB/IND pin = 1 logic). 14/27 www.BDTIC.com/ST AN1775 6.4 6 Reference Design CAN interface A general purpose, asynchronous serial I/O data port connected through a 9-pin D-type male connector with micro switches selectable between High or Low bus output S702, and between Standby or Slope control S700. For more details, refer to CAN transceiver SN65HVD230D datasheet. 6.5 RS232 serial interface A general purpose, asynchronous serial I/O data ports is connected through 9-pin D-type male connectors. RS232 connects directly to UART0, transmit and receive only (null modem). RTS is shorted to CTS and DTR is shorted to DSR at the connector. For more details, refer to RS232 transceiver ST3232 datasheet. 6.6 Serial ROM 6.6.1 SPI Flash 1-Mbit SPI serial flash connected to the buffered serial peripheral interface (BSPI). Switch S603 is used to enable or disable write protect (pull down = Write protect, pull up = Write enabled). For more details, refer to SPI Flash M25P10-A datasheet. 6.6.2 I2C EEPROM: 8-kbit EEPROM connected to the I2C0 interface, Switch S600 is used to enable or disable write protect (pull down = Write protect, pull up = Write enabled). For more details, refer to I2C Eeprom M24C08 datasheet. The values R614 and R616 are dependent on the I2C communication speed. For more details on theses values, please refer to the STR71x reference manual. 6.7 JTAG interface Refer to the section Section 5 on page 11. 6.8 SRAM Two SRAM 2M byte are connected to External Interface Memoy EMI and mapped from 0x6200 0000 to 0x623F FFFF. For more details, refer to the SRAM memory TC55V8200FT-12 datasheet. 15/27 www.BDTIC.com/ST AN1775 6 Reference Design 6.9 Flash One Flash 2M word is connect to External Interface Memoy EMI and mapped from 0x6000 0000 to 0x603F FFFF (boot bank). For more details, refer toFlash memory M28W320ECB datasheet. 6.10 LCD interface LCd 2 * 16 is connected to external interface memory EMI. Address 2 A2 is used as the LCD register address signal. Region space available from 0x6400 0000 to 0x65FF FFFF 6.11 Conclusions and recommendations ● System clock jitter values decrease when the system clock is delivered by STR71x internal PLL1 (comparing to the jitter values on the external oscillator inputs), because the noise injected in the CLK pin input was filtered by the internal PLL. ● It is possible to use one single external 4MHz oscillator to generate both core, peripheral’s clocks and 48MHz USB clock to minimize and save board cost and space. ● With this single external oscillator generating both the system clock using PLL1 and the 48Mhz USB clock using PLL2, the STR710/STR711 has all the characteristics to pass the requirements for USB revision 2.0 full speed device test and get the USB certification. Particular care must be taken to decrease external oscillator noise while routing its clock on board. 16/27 www.BDTIC.com/ST A B C page 2 RS R/W notE DATA (7:0) LCD.Sch page 4 not CS_SRAM not OE not WR0 not WR1 1 2 74LCX14 VCC +3V3 U101A page 3 1 not CS_FLASH not OE not WR vpp not RESET ADD (23:0) DATA (15:0) FLASH.Sch ADD (23:0) SW SPDT S110 SW SPDT S109 DATA (15:0) SRAM.Sch 10K 10K R102 10K R101 * For not used pins set to logic level by software ADD2 BOOT.1 BOOT.0 2 R122 R103 R104 10nF SW-PB C100 S111 R133 R134 R140 22 22 22 DBGRQS 22 22 22 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 ADD0 ADD1 ADD2 ADD4 ADD5 ADD6 ADD7 ADD8 ADD9 ADD10 ADD11 ADD12 ADD13 ADD14 ADD15 ADD16 ADD17 ADD18 ADD19 ADD20 ADD21 ADD22 ADD23 ADD24 R127 1K 3 38 36 35 44 18 2 137 136 61 62 63 64 65 78 79 80 81 82 92 93 94 95 96 97 98 99 100 101 102 114 115 116 117 118 119 120 121 122 130 131 132 133 134 135 13 14 15 17 7 8 11 12 R128 STR710 R129 10K +3V3 47 51 P2.0_not CS.0 P2.1_not CS.1 P2.2_not CS.2 P2.3_not CS.3 TEST TEST NU DBGRQS P2.8 not RD not WE.0 not WE.1 D.0 D.1 D.2 D.3 D.4 D.5 D.6 D.7 D.8 D.9 D.10 D.11 D.12 D.13 D.14 D.15 A.0 A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 A.13 A.14 A.15 A.16 A.17 A.18 A.19 P2.4_A.20 P2.5_A.21 P2.6_A.22 P2.7_A.23 +3V3 6 22 40 83 104 113 138 10uF C101 +3V3AN V33_1 V33_2 V33_3 V33_4 V33_5 V33_6 V33_7 D +3V3 3 58 59 33nF C102 4 RTCXTO RTCXTI CK CKOUT JTDI JTDO JTCK JTMS not JTRST not RSTIN 4 P1.2_T3.OCMPA_AIN.2 P1.1_T3.ICAPA_AIN.1 P1.3_T3.ICAPB_AIN.3 P1.4_T1.ICAPA P1.5_T1.ICAPB P1.6_T1.OCMPB P1.7_T1.OCMPA P1.9 P1.15_HTXD P0.8_U0.RX_U0.TX P0.10_U1.RX_U1.TX_SCDATA P0.12_SCCLK P2.13 P2.14 P2.15 P2.9 P2.10 P0.0_S0.MISO_U3.TX P0.1_S0.MOSI_U3.RX P0.2_S0.SCLK_I1.SCL P0.3_S0.SSN_I1.SDA P1.0_T3.OCMPB_AIN.0 P0.13_U2.RX_T2.OCMPA P0.14_U2.TX_T2.ICAPA P1.14_HRXD_I0.SDA P1.13_HCLK_I0.SCL P0.4_S1.MISO P0.5_S1.MOSI P0.6_S1.SCLK P0.7_S1.SSN P1.8 USBDP USBDN P1.10_USBCLK P2.11 P2.12 P1.11_CANRX P1.12_CANTX BOOT_EN P0.9_U0.TX_BOOT.0 P0.11_U1.TX_BOOT.1 V18_1 VSS18_1 SW SPDT S108 2 55 54 V18BKP VSSBKP BOOT_EN R100 +3V3 66 AVDD VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 42 84 103 112 139 5 21 P0.15_WAKEUP not STDBY 129 128 V18_2 VSS18_2 AVSS www.BDTIC.com/ST 67 ADCIN LED_P0.0 LED_P0.1 LED_P0.2 LED_P0.3 Button_1 Button_2 71 123 124 125 126 23 24 73 72 74 75 76 77 85 105 111 143 1 4 27 28 29 RX TX 9 10 108 107 127 140 141 142 86 90 91 106 25 26 88 89 16 BOOT_EN 144 BOOT.0 3 BOOT.1 50 RTCXTO 49 RTCXTI 46 CK 45 CKOUT 30 33 32 31 34 52 not RESET 1.0uF C103 LED_P0.3 LED_P0.2 LED_P0.1 LED_P0.0 page 6 SDA SCL MISO MOSI SCLK SSN not S Serial_ROM.Sch DBGRQS 560 560 R142 560 R141 560 R136 R135 RX TX page 9 page 5 5 Date: File: B Size Title D109 D108 D107 D106 RX TX RS232.Sch USBDP USBDN USBCLK USBV_IND USB_PULL_UP USB.Sch page 7 CAN_RX CAN_TX page 8 CAN.Sch DBGRQS JTDI JTDO JTCK JTMS not JTRST not Reset JTAG.Sch 5 LED LED LED LED 1 22-Jun-2005 Number ADCIN CK S112 SW-PB not RESET 33 STR710 MCU S116 SW-PB R137 10K +3V3 Button_1 RTCXTO RTCXTI 3 2 32KHz C106 15pF 50V Y101 VCC +3V3 OUT EN S113 16MHz OSC VCC 6 1 6 C115 0.1uF 1.0 R139 4K7 S117 SW-PB Revision Button_2 R138 10K +3V3 Sheet 1 of 10 Drawn By: C114 0.1uF S115 C113 15pF 50V R131 10K +3V3 +3V3 *Switch used for ADC calibration +2V5AN R132 not RESET SW SPDT S114 C104 1nF 1 R130 2K2 D105 STM1001T (3.08V) VSS 3 not Reset A B C D 7 1 AN1775 7 Schematics Schematics Figure 10. Reference design top level schematics 17/27 18/27 www.BDTIC.com/ST A B C D 1 1 RS 2 notE RnotW DATA (7:0) 2 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 18 17 16 15 14 13 12 11 1 DIR G A1 A2 A3 A4 A5 A6 A7 A8 R209 1K 3 74LCX14 VCC +3V3 U200A 74LCX245 VCC +3V3 B1 B2 B3 B4 B5 B6 B7 B8 R201 3 C205 100pF 5 6 4 1 19 2 7 8 9 10 11 12 13 14 2 3 4 5 6 7 8 9 VO GND VCC5V K A 4 LCD LWM 1602 B-BG/SYN R/W E RS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 R202 4 3 1 2 16 15 R200 4K7 +5 R203 10K 5 5 C203 Number 22-Jun-2005 B Date: File: 2 C204 0.1uF Size Title 10uF 16V +5 LCD 6 Sheet 2 of Drawn By: 6 10 Revision 1.0 A B C D 7 Schematics AN1775 Figure 11. LCD interface www.BDTIC.com/ST A B C D 1 1 2 2 not RESET not CS_FLASH not WR not OE ADD (23:0) R306 10K R307 10K +3V3 +3V3 DATA (15:0) 3 ADD1 ADD2 ADD3 ADD4 ADD5 ADD6 ADD7 ADD8 ADD9 ADD10 ADD11 ADD12 ADD13 ADD14 ADD15 ADD16 ADD17 ADD18 ADD19 ADD20 ADD21 3 14 12 26 11 28 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 15 10 VPP DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 FLASH M28W320ECB VCC +3V3 not WP not RP not CE not WE not OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 R305 13 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 4 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 4 R308 10K +3V3 vpp 5 5 Number 22-Jun-2005 B Size 3 FLASH Date: File: Title 6 Sheet 3 of Drawn By: 6 10 Revision Text A B C D AN1775 7 Schematics Figure 12. EMI Flash 19/27 20/27 www.BDTIC.com/ST A B C D 1 1 2 not OE not WR0 not CS_SRAM 2 R403 10K +3V3 R404 10K +3V3 ADD (23:0) DATA (15:0) ADD1 ADD2 ADD3 ADD4 ADD5 ADD6 ADD7 ADD8 ADD9 ADD10 ADD11 ADD12 ADD13 ADD14 ADD15 ADD16 ADD17 ADD18 ADD19 ADD20 ADD21 15 13 16 42 11 10 9 8 7 48 47 46 45 44 38 37 36 35 34 21 20 19 18 17 39 IO_1 IO_2 IO_3 IO_4 IO_5 IO_6 IO_7 IO_8 3 SRAM TC55V8200FT-12 VCC +3V3 not WE not CE N_CE2 not OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 R401 3 22 24 31 33 49 51 4 6 R405 10K +3V3 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 not WR1 4 ADD1 ADD2 ADD3 ADD4 ADD5 ADD6 ADD7 ADD8 ADD9 ADD10 ADD11 ADD12 ADD13 ADD14 ADD15 ADD16 ADD17 ADD18 ADD19 ADD20 ADD21 4 15 13 16 42 11 10 9 8 7 48 47 46 45 44 38 37 36 35 34 21 20 19 18 17 39 IO_1 IO_2 IO_3 IO_4 IO_5 IO_6 IO_7 IO_8 SRAM TC55V8200FT-12 VCC +3V3 not WE not CE N_CE2 not OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 R402 22 24 31 33 49 51 4 6 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 5 5 Number 4 22-Jun-2005 10 Date: File: B Size Title SRAM Revision 6 Sheet 4 of 10 Drawn By: 6 1.0 A B C D 7 Schematics AN1775 Figure 13. EMI SRAM 1 2 3 T1OUT T2OUT R1IN R2IN 14 7 13 8 5 4 C503 0.1uF 25V 4 1 6 2 7 3 8 4 9 5 DB9 male J500 5 Title RS232 Sheet 5 of Drawn By: 6 Revision 1.0 C D www.BDTIC.com/ST Number 5 22-Jun-2005 Date: File: B Size 6 10 A R510 ST3232 VCC +3V3 T1IN T2IN R1OUT R2OUT C2- C2+ 5 A 11 10 12 9 C1- C1+ C502 0.1uF 25V +3V3 4 B RX TX C500 0.1uF 25V 3 1 C501 0.1uF 25V 3 B C 2 6 V- 2 V+ D 1 AN1775 7 Schematics Figure 14. RS232 interface 21/27 22/27 www.BDTIC.com/ST A B C D 1 1 2 2 R617 10K +3V3 R615 10K +3V3 SCL * connect to pull-up by default SW SPDT S603 R618 10K +3V3 * connect to pull-up by default SW SPDT S600 3 R616 4K7 +3V3 not S SCLK MOSI SSN 3 R620 10K +3V3 R600 R601 R602 10K 10K 10K +3V3 +3V3 +3V3 1 3 7 6 5 7 6 1 2 3 SDA 5 Q 4 SPI_FLAS H M25P10-A VCC +3V3 not S not W not HOLD C D R619 2 I2C_EEP ROM M24C08 VCC +3V3 not WC SCL E1 E2 E3 R603 4 R614 4K7 +3V3 MISO SDA 5 5 Size B Date: File: Title 22-Jun-2005 Number 6 SERIAL MEMORY Revision 1.0 Sheet 6 of 10 Drawn By: 6 6 A B C D 7 Schematics AN1775 Figure 15. Serial ROM interface 2 3 1 2 3 4 RS CANH CANL Vref SN65HVD230D VCC +3V3 D GND VCC R R700 8 7 6 5 S700 4 S702 SW-SP ST R704 120 R701 10K R702 10K R703 10K +3V3 1 6 2 7 3 8 4 9 5 DB9 J701 5 5 Title CAN 7 6 Revision 1.0 C D www.BDTIC.com/ST Size B Date: File: 22-Jun-2005 Number Sheet 7 of 10 Drawn By: 6 A +3V3 SW SPDT +3V3 4 A CAN_RX CAN_TX 3 B 1 2 B C D 1 AN1775 7 Schematics Figure 16. CAN interface 23/27 24/27 www.BDTIC.com/ST A B C D 1 1 2 2 not Reset DBGRQS JTDO not JTRst JTDI JTMS JTCK 3 R800 10K 3 47K R807 R801 10K R804 10K R802 10K +3V3 Q800 BC846 R817 22K +3V3 R803 10K 10K R818 R805 10K +3V3 2 4 6 8 10 12 14 16 18 20 4 Q803 BC846 C800 0.01uF *Switch closed by default S801 SW SPST HEADER 10X2 1 3 5 7 9 11 13 15 17 19 JP801 4 5 5 Number 8 13-Sep-2005 B Date: File: JTAG Size Title Revision 6 Sheet 8 of 10 Drawn By: 6 1.0 A B C D 7 Schematics AN1775 Figure 17. JTAG interface www.BDTIC.com/ST A B C D 1 1 2 2 USBCLK USBDN USBDP USB_PULL_UP C900 15pF R901 1K5 C901 15pF 3 3 R902 R903 3 OUT EN 1 VCC +3V3 R907 10K +3V3 R906 USB_CON VBUS DN DP GND J900 48MHz C OS 0 0 1 2 3 4 R905 56K R904 56K 4 Q900 BC547E R900 47K +3V3 4 USBV_IND 5 5 Size B Date: File: Title 22-Jun-2005 Number9 USB 1.0 Revision Sheet 9 of 10 Drawn By: 6 6 A B C D AN1775 7 Schematics Figure 18. USB interface 25/27 26/27 www.BDTIC.com/ST A B C D 1 J1000 2 +5V 1 JACK +5V 2 1 4 5 6 3 C1011 10uF 10V +5V CG1 CG2 CG3 CV C1013 10uF 10V C1014 10nF 50V 1 C1027 C1025 100nF 25V 100nF 25V +3V3 C1024 C1026 100nF 25V 100nF 25V +3V3 C1012 10uF 10V +3V3 BNX002 SG SV R1000 C1000 47uF 16V +5V 3 C1018 10uF 10V C1022 C1023 100nF 25V 100nF 25v 2 3 C1029 C1031 C1033 C1035 C1037 C1039 C1041 C1043 100nF 25V 100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V C1028 C1030 C1032 C1034 C1036 C1038 C1040 C1042 C1044 100nF 25V 100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V100nF 25V 100nF 25V C1021 100nF 25v C1020 10nF 50V +3V3 C1015 C1016 C1017 C1019 100uF 10V 100uF 10V 10nF 50V 10nF 50V 3 C1001 C1002 C1003 C1004 100nF 25V 100nF 25V 100nF 25V 100nF 25V U1001 VOLT_REG_3V3 Vin Vout 2 GND 2 1 4 +3V3 4 L1001 FBEAD D1000 LED R1002 1K 5 1K R1001 Size B Date: File: Title 22-Jun-2005 +2V5AN D1002 LM4040 10 POWER Number D1001 LED R1003 560 +3V3 C1046 C1047 0.1uF 25V 10nF 50v +5V 10uF 16V C1045 +3V3AN 5 Revision 1.0 Sheet 10 of 10 Drawn By: 6 6 A B C D 7 Schematics AN1775 Figure 19. Power schematics AN1775 7 Schematics “THE PRESENT NOTE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH A NOTE AND/OR THE USE MADE BY CUSTOMERS OF THE INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.” Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 27/27 www.BDTIC.com/ST