a AN-420 APPLICATION NOTE •
... *Current was measured with a 50 MHz clock, +5 V supplies and 50 Ω loads on the signal output pins. †These supplies are not required for DAC operation. (Current drain depends on what components are mounted.) ...
... *Current was measured with a 50 MHz clock, +5 V supplies and 50 Ω loads on the signal output pins. †These supplies are not required for DAC operation. (Current drain depends on what components are mounted.) ...
DAC908 数据资料 dataSheet 下载
... resistor, RSET. The resulting IREF is internally multiplied by a factor of 32 to produce an effective DAC output current that can range from 2mA to 20mA, depending on the value of RSET. ...
... resistor, RSET. The resulting IREF is internally multiplied by a factor of 32 to produce an effective DAC output current that can range from 2mA to 20mA, depending on the value of RSET. ...
3-Phase Power Supply, Primary Switch Mode for
... than 20 ms at full load. All 3-phase QUINT POWER units provide the complete output power even in the event of a continuous phase failure. Reliable startup of heavy loads is ensured by a power reserve of up to 50% - the POWER BOOST. Preventive function monitoring diagnoses an impermissible operating ...
... than 20 ms at full load. All 3-phase QUINT POWER units provide the complete output power even in the event of a continuous phase failure. Reliable startup of heavy loads is ensured by a power reserve of up to 50% - the POWER BOOST. Preventive function monitoring diagnoses an impermissible operating ...
Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator w/ Universal
... The differential voltage of a differential signal can be described by two different definitions causing confusion when reading datasheets or communicating with other engineers. This section will address the measurement and description of a differential signal so that the reader will be able to under ...
... The differential voltage of a differential signal can be described by two different definitions causing confusion when reading datasheets or communicating with other engineers. This section will address the measurement and description of a differential signal so that the reader will be able to under ...
LT5568-2 - GSM/EDGE Optimized, High Linearity Direct Quadrature Modulator.
... using differential baseband I and Q signals. It supports GSM, EDGE, CDMA, CDMA2000 and other systems that operate in the 850MHz to 965MHz band. It may be configured as an image reject upconverting mixer, by applying 90° phase-shifted signals to the I and Q inputs. The I/Q baseband inputs consist of v ...
... using differential baseband I and Q signals. It supports GSM, EDGE, CDMA, CDMA2000 and other systems that operate in the 850MHz to 965MHz band. It may be configured as an image reject upconverting mixer, by applying 90° phase-shifted signals to the I and Q inputs. The I/Q baseband inputs consist of v ...
Noise Measurements - Harvard University Department of Physics
... Both the SR760 and the SR785 have an 18-bit ADC with 2 bits used for sign, so the dynamic range is 216 = 65536 bins or 90 dB. However the SR785 has a more advanced chip which uses a technique called “noise injection” or “dithering”. If the actual signal is relatively quiet, and sits, say 80% of the ...
... Both the SR760 and the SR785 have an 18-bit ADC with 2 bits used for sign, so the dynamic range is 216 = 65536 bins or 90 dB. However the SR785 has a more advanced chip which uses a technique called “noise injection” or “dithering”. If the actual signal is relatively quiet, and sits, say 80% of the ...
ADS7813 数据资料 dataSheet 下载
... (3) Full scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (4) After the ADS7813 is initially powered on and full ...
... (3) Full scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (4) After the ADS7813 is initially powered on and full ...
DAC900 数据资料 dataSheet 下载
... RSET. The resulting IREF is internally multiplied by a factor of 32 to produce an effective DAC output current that can range from 2mA to 20mA, depending on the value of RSET. ...
... RSET. The resulting IREF is internally multiplied by a factor of 32 to produce an effective DAC output current that can range from 2mA to 20mA, depending on the value of RSET. ...
MAX9180 400Mbps, Low-Jitter, Low-Noise LVDS Repeater in an SC70 Package General Description
... The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium, as defined by the ANSI/ TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, achieving higher data ...
... The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium, as defined by the ANSI/ TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, achieving higher data ...
PDF
... parallel processing (PP), razor-based dynamic voltage scaling (DVS), and dedicated MP operands scheduling to provide optimum performance for a variety of operating conditions. All of the building blocks of the proposed reconfigurable multiplier can either work as independent smaller-precision multip ...
... parallel processing (PP), razor-based dynamic voltage scaling (DVS), and dedicated MP operands scheduling to provide optimum performance for a variety of operating conditions. All of the building blocks of the proposed reconfigurable multiplier can either work as independent smaller-precision multip ...
A 10-BIT 1.2-GS/s NYQUIST CURRENT
... is minimized by limiting the amplitude of the control signals just high enough to switch the tail current completely to the desired output branch of the differential pair. In addition the switch transistors are kept relatively small in order to avoid large parasitic capacitances. Clock distribution ...
... is minimized by limiting the amplitude of the control signals just high enough to switch the tail current completely to the desired output branch of the differential pair. In addition the switch transistors are kept relatively small in order to avoid large parasitic capacitances. Clock distribution ...
Unit 21
... the d.c. output voltage, is also constant, it follows that the voltage VR across resistor R will be constant as well, because Vi = VR + VL. The current I through R equals VR/R and is therefore constant. But I = ID + 1L where ID and IL are the currents through the diode and the load respectively. Hen ...
... the d.c. output voltage, is also constant, it follows that the voltage VR across resistor R will be constant as well, because Vi = VR + VL. The current I through R equals VR/R and is therefore constant. But I = ID + 1L where ID and IL are the currents through the diode and the load respectively. Hen ...
Switched flip-flop based preprocessing circuit for ISFET
... The sensitivity of an ISFET is usually expressed as the gate-voltage change per decade of the hydrogen-ion concentration (pH), where the pH denotes -log [H+]. For example, if the value of the pH is equal to 2, the concentration of the hydrogen ions amounts to be 10-2 mole per liter. As measurement m ...
... The sensitivity of an ISFET is usually expressed as the gate-voltage change per decade of the hydrogen-ion concentration (pH), where the pH denotes -log [H+]. For example, if the value of the pH is equal to 2, the concentration of the hydrogen ions amounts to be 10-2 mole per liter. As measurement m ...
ADV7122 数据手册DataSheet 下载
... The ADV7121/ADV7122 (ADV ) is a video speed, digital-toanalog converter on a single monolithic chip. The part is specifically designed for high resolution color graphics and video systems including high definition television (HDTV). It is also ideal for any application requiring a low cost, high spe ...
... The ADV7121/ADV7122 (ADV ) is a video speed, digital-toanalog converter on a single monolithic chip. The part is specifically designed for high resolution color graphics and video systems including high definition television (HDTV). It is also ideal for any application requiring a low cost, high spe ...
Analog-to-digital converter
An analog-to-digital converter (ADC, A/D, or A to D) is a device that converts a continuous physical quantity (usually voltage) to a digital number that represents the quantity's amplitude.The conversion involves quantization of the input, so it necessarily introduces a small amount of error. Furthermore, instead of continuously performing the conversion, an ADC does the conversion periodically, sampling the input. The result is a sequence of digital values that have been converted from a continuous-time and continuous-amplitude analog signal to a discrete-time and discrete-amplitude digital signal.An ADC is defined by its bandwidth (the range of frequencies it can measure) and its signal to noise ratio (how accurately it can measure a signal relative to the noise it introduces). The actual bandwidth of an ADC is characterized primarily by its sampling rate, and to a lesser extent by how it handles errors such as aliasing. The dynamic range of an ADC is influenced by many factors, including the resolution (the number of output levels it can quantize a signal to), linearity and accuracy (how well the quantization levels match the true analog signal) and jitter (small timing errors that introduce additional noise). The dynamic range of an ADC is often summarized in terms of its effective number of bits (ENOB), the number of bits of each measure it returns that are on average not noise. An ideal ADC has an ENOB equal to its resolution. ADCs are chosen to match the bandwidth and required signal to noise ratio of the signal to be quantized. If an ADC operates at a sampling rate greater than twice the bandwidth of the signal, then perfect reconstruction is possible given an ideal ADC and neglecting quantization error. The presence of quantization error limits the dynamic range of even an ideal ADC, however, if the dynamic range of the ADC exceeds that of the input signal, its effects may be neglected resulting in an essentially perfect digital representation of the input signal.An ADC may also provide an isolated measurement such as an electronic device that converts an input analog voltage or current to a digital number proportional to the magnitude of the voltage or current. However, some non-electronic or only partially electronic devices, such as rotary encoders, can also be considered ADCs. The digital output may use different coding schemes. Typically the digital output will be a two's complement binary number that is proportional to the input, but there are other possibilities. An encoder, for example, might output a Gray code.The inverse operation is performed by a digital-to-analog converter (DAC).