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MAX2022 High-Dynamic-Range, Direct Up/ Downconversion 1500MHz to 3000MHz Quadrature Modulator/Demodulator
MAX2022 High-Dynamic-Range, Direct Up/ Downconversion 1500MHz to 3000MHz Quadrature Modulator/Demodulator

... LTE/TD-LTE, cdma2000®, and DCS/PCS base-station applications. Direct conversion architectures are advantageous since they significantly reduce transmitter or receiver cost, part count, and power consumption as compared to traditional IF-based double conversion systems. In addition to offering excell ...
AD9260 数据手册DataSheet下载
AD9260 数据手册DataSheet下载

... offers a complete single-chip 16-bit sampling ADC with a 2.5 MHz output data rate in a 44-lead MQFP. Selectable Internal Decimation Filtering—The AD9260 provides a high performance decimation filter with 0.004 dB pass-band ripple and 85 dB of stop-band attenuation. The filter is configurable with op ...
SN74LS147, SN74LS148 10 LINE TO 4 LINE AND 8 LINE TO 3
SN74LS147, SN74LS148 10 LINE TO 4 LINE AND 8 LINE TO 3

... † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to ...
INA121 数据资料 dataSheet 下载
INA121 数据资料 dataSheet 下载

... The 50kΩ term in Equation 1 comes from the sum of the two internal feedback resistors of A1 and A2. These on-chip metal film resistors are laser trimmed to accurate absolute values. The accuracy and temperature coefficient of these resistors are included in the gain accuracy and drift specifications ...
MAX1927/MAX1928 Low-Output-Voltage, 800mA, PWM Step-Down DC-DC Converters General Description
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... slope compensation ramp are all summed at the PWM comparator. The comparator modulates the output power by adjusting the peak inductor current during the first half of each cycle based on the output-error voltage. The MAX1927/MAX1928 have relatively low ACloop gain coupled with a high-gain integrato ...
by Submitted in partial fulfilment of the requirements for the degree
by Submitted in partial fulfilment of the requirements for the degree

FEATURES DESCRIPTION D
FEATURES DESCRIPTION D

... The OPA830 is a low-power, single-supply, wideband, voltage-feedback amplifier designed to operate on a single +3V or +5V supply. Operation on ±5V or +10V supplies is also supported. The input range extends below the negative supply and to within 1.7V of the positive supply. Using complementary comm ...
HMC690 数据资料DataSheet下载
HMC690 数据资料DataSheet下载

... designed for SONET OC-192 / SDH STM-64, 10GbE and 10Gbps systems employing optical amplifiers. It supports data rates up to 11.3 Gbps. This amplifier provides a differential output voltage that is proportional to an applied current at its input port. This current is typically provided by a photodiod ...
Zero Drift, Digitally Programmable Instrumentation Amplifier AD8231
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... The gains are programmed via digital logic or pin strapping. The AD8231 is ideal for applications that require precision performance over a wide temperature range, such as industrial temperature sensing and data logging. Because the gain setting resistors are internal, maximum gain drift is only 10 ...
OPA657 - Texas Instruments
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... Very low level signals can be significantly amplified in a single OPA657 gain stage with exceptional bandwidth and accuracy. Having a high 1.6-GHz gain bandwidth product gives greater than 10-MHz signal bandwidths up to gains of 160 V/V (44 dB). The very low input bias current and capacitance suppor ...
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... and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. ...
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... This experiment necessitates the construction of two band stop filters, each connecting to the photoelectric eye. In order to construct the circuits efficiently, three breadboards are needed, one for each circuit and a third for the photoelectric eye. A 100 kΩ resistor is required to limit the curre ...
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... that passes the D input to the Q output when the clock signal is high.  This latch is said to be in transparent mode. When the clock is low, the input data sampled on the falling edge of the clock is held stable at the output for the entire phase, and the latch is in hold mode.  The inputs must be ...
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... merit for instrumentation amplifiers. While initial offset may be adjusted to zero, shifts in offset voltage due to temperature variations will cause errors. Intelligent systems can often correct for this factor with an autozero cycle, but there are many smallsignal high-gain applications that don’t ...
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... wideband, unity-gain stable, voltage-feedback architecture. Intended for xDSL receiver applications, the OPA2822 also supports this low input noise with exceptionally low harmonic distortion, particularly in differential configurations. Adequate output current is provided to drive the potentially he ...
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... A similar idea is used in the digital implementation in this paper but here it does not happen periodically. Figure 6 shows the block diagram of this method. Once the voltage across the piezoelectric actuator is equal to zero, the integrator will be restarted. This process is implemented within the ...
Author template for journal articles
Author template for journal articles

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FEATURES DESCRIPTION APPLICATIONS

TLC5618A 数据资料 dataSheet 下载
TLC5618A 数据资料 dataSheet 下载

... CMOS-compatible serial bus. The device receives a 16-bit word for programming and producing the analog output. The digital inputs feature Schmitt triggers for high noise immunity. Digital communication protocols include the SPI, QSPI, and Microwire standards. ...
ADC0803, ADC0804 8-Bit, Microprocessor-Compatible, A/D Features Converters
ADC0803, ADC0804 8-Bit, Microprocessor-Compatible, A/D Features Converters

... 3. For VIN(-) ≥ VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the V+ supply. Be careful, during testing at low V+ l ...
Slides - EECG Toronto - University of Toronto
Slides - EECG Toronto - University of Toronto

... University of Toronto ...
a AN-581 APPLICATION NOTE Biasing and Decoupling Op Amps
a AN-581 APPLICATION NOTE Biasing and Decoupling Op Amps

... Single supply applications have inherent problems that are not usually found in dual supply op amp circuits. The fundamental problem is that an op amp is a dual supply device and so some type of biasing, using external components, must be used to center the op amp’s output voltage at midsupply. This ...
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Phase-locked loop

A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. While there are several differing types, it is easy to initially visualize as an electronic circuit consisting of a variable frequency oscillator and a phase detector. The oscillator generates a periodic signal. The phase detector compares the phase of that signal with the phase of the input periodic signal and adjusts the oscillator to keep the phases matched. Bringing the output signal back toward the input signal for comparison is called a feedback loop since the output is ""fed back"" toward the input forming a loop.Keeping the input and output phase in lock step also implies keeping the input and output frequencies the same. Consequently, in addition to synchronizing signals, a phase-locked loop can track an input frequency, or it can generate a frequency that is a multiple of the input frequency. These properties are used for computer clock synchronization, demodulation, and frequency synthesis.Phase-locked loops are widely employed in radio, telecommunications, computers and other electronic applications. They can be used to demodulate a signal, recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency (frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits such as microprocessors. Since a single integrated circuit can provide a complete phase-locked-loop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many gigahertz.
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