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LT230 series Digital Indicating Controller
LT230 series Digital Indicating Controller

SNx5HVD308xE Low-Power RS-485
SNx5HVD308xE Low-Power RS-485

LK7664 - Electricity matters 3 (for LK9329)
LK7664 - Electricity matters 3 (for LK9329)

... • An electric current is a flow of electrons, tiny particles found in all atoms. • The current is a measure of how many electrons pass each second. • Electrons lose energy as they flow around a circuit, but are not destroyed. The same number of electrons return to the power supply as left it. It is ...
Resistors 101 – Instructional Guide
Resistors 101 – Instructional Guide

An inductorless wideband LNA with a new noise cancelling technique
An inductorless wideband LNA with a new noise cancelling technique

TPS60120 数据资料 dataSheet 下载
TPS60120 数据资料 dataSheet 下载

... The TPS6012x charge pumps consist of an oscillator, a 1.21-V bandgap reference, an internal resistive feedback circuit, an error amplifier, high current MOSFET switches, a shutdown/start-up circuit, a low-battery or power-good comparator, and a control circuit (see the functional block diagram). The ...
PE4460 - Peregrine Semiconductor
PE4460 - Peregrine Semiconductor

... When handling this UTSi device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in table. Latch-Up Avoidance ...
delay analysis and optimal biasing for high speed low power current
delay analysis and optimal biasing for high speed low power current

... Fig. 2. CML D-Latch delay versus normalized bias current. Fig.2 plots the gate propagation delay with respect to the bias current normalized to the peak fT current using equations 3a,3b,3c. It comes as no surprise that the optimum biasing current to provide minimum delay is indeed the transistor pea ...
DAC8820 数据资料 dataSheet 下载
DAC8820 数据资料 dataSheet 下载

... use of an external I/V converter op amp. The R-2R ladder is connected to an external reference input (VREF) that determines the DAC full-scale current. The R-2R ladder presents a code independent load impedance to the external reference of 6 kΩ ±25%. The external reference voltage can vary in a rang ...
Current-shunt feedback
Current-shunt feedback

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Line Driver and Receiver

Optocoupler Common Mode Transient Immunity (CMTI)
Optocoupler Common Mode Transient Immunity (CMTI)

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Currents in a parallel circuit

FAN3278 30V PMOS-NMOS Bridge Driver  FAN3278 — 30V PMOS-NMOS Bridge Driver
FAN3278 30V PMOS-NMOS Bridge Driver FAN3278 — 30V PMOS-NMOS Bridge Driver

... As an example of a power dissipation calculation, consider an application driving two MOSFETs (one Pchannel and one N-channel, both with a gate charge of 60nC each) with VGS=VDD=12V. At a switching frequency of 200kHz, the total power dissipation is: ...
Constant Fraction Discriminator
Constant Fraction Discriminator

... time setting. Input to Output Delay: 15 nsec + constant fraction delay. Delay matched to better than 2 nsec. Test to Output Delay: 30 nsec. Multiple Pulsing: None; one and only one output pulse is produced regardless of input pulse amplitude so long as the dead time setting is greater than the progr ...
MAX6957 4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and 28
MAX6957 4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and 28

II. The Equivalent Input Circuit
II. The Equivalent Input Circuit

... in solution to (14) assumed to be limited to  10%. The total equivalent amplifier offset voltage was assumed to be within  10 mV (rather conservative for modern operational amplifiers). Solution to (14) was sought for minimum and maximum negative conductance of the NIC applied (RN = - 20 M and RN ...
LTC6362 - Linear Technology
LTC6362 - Linear Technology

MAX5951 12V/5V Input Buck PWM Controller General Description Features
MAX5951 12V/5V Input Buck PWM Controller General Description Features

... Analog Ground Connection. Solder the exposed pad to a large AGND plane. Connect AGND and PGND together at one point near the input bypass capacitor return terminal. Synchronization Output. SYNCOUT is a synchronization signal to drive the SYNCIN of a second MAX5950 or MAX5951, if used. Leave SYNCOUT ...
Masters Thesis
Masters Thesis

... swing and reduce harmonic distortion characteristics. In the presented research, local common mode feedback techniques are applied to both single ended and fully differential operational transconductance amplifiers. LCMFB provides wide-range programming of amplifier characteristics and increases the ...
Robust RS-485 Transceiver (Rev. A)
Robust RS-485 Transceiver (Rev. A)

TPS70175-Q1 数据资料 dataSheet 下载
TPS70175-Q1 数据资料 dataSheet 下载

... regulators are sensed at the VSENSE1 and VSENSE2 pins, respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches appro ...
Sure Cross MultiHop Registers Parameters
Sure Cross MultiHop Registers Parameters

... Extended Input Read The Extended Input Read is a bit field parameter that allows multiple inputs to be sampled with the same switch power parameters. If the bit field is set to 0x000F, the first four inputs are sampled after the switch power parameters are satisfied. If this parameter is set in the ...
LT5526 - High Linearity, Low Power Downconverting Mixer.
LT5526 - High Linearity, Low Power Downconverting Mixer.

... input circuit and example external impedance matching components for a 900MHz application. Each RF input pin requires a low resistance DC return to ground capable of handling 7.5mA. The DC ground can be realized using the center-tap of an input transformer (T1), as shown, or through matching inducto ...
Accurate Multiple Input Switching solution for Static Timing Analysis
Accurate Multiple Input Switching solution for Static Timing Analysis

... Timing Verification ensures the adherence of the design to design timing requirements. It ensures that the design’s data will be correctly handled and will stay uncorrupted. In order to elaborate about timing verification, it is important at this stage to discuss the details of the typical design st ...
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