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APPLICATION OF LOCAL COMMON MODE FEEDBACK TECHNIQUES
TO ENHANCE SLEW RATE AND GAIN-BANDWIDTH OF
CMOS OPERATIONAL AMPLIFIERS
BY
MICHAEL LEIGH HOLMES, BSEE
A thesis submitted to the Graduate School
in partial fulfillment of the requirements
for the degree
Master of Science
Major Subject: Electrical Engineering
New Mexico State University
Las Cruces, New Mexico
December 2002
"Application of Local Common Mode Feedback Techniques to Enhance Slew Rate
and Gain-Bandwidth of CMOS Operational Amplifiers," a thesis prepared by Michael
Leigh Holmes in partial fulfillment of the requirements for the degree, Master of
Science in Electrical Engineering, has been approved and accepted by the following:
Linda Lacey
Dean of the Graduate School
Jaime Ramirez-Angulo
Chair of the Examining Committee
Date
Committee in charge:
Dr. Jaime Ramirez-Angulo, Chair
Dr. Paul M. Furth
Dr. Stuart H. Munson-McGee
ii
ACKNOWLEDGEMENTS
First, I have to thank my advisor, Dr. Jaime Ramirez-Angulo, for recognizing
my commitment as an undergraduate and honoring me with this graduate position and
research assistantship; for his guidance, support, and patience, in mentoring me
towards the completion of this research and the largest project of my life. His work
ethic, humor, and emphasis on the little things in life, will not be forgotten.
Second, acknowledgment of the support and commitment I have received
from Dr. Paul Furth throughout the duration of my educational experience. His
dedication to family and his students is a source of admiration.
To my dad, who pushes me to succeed through his interest in my work. My
mom, who, through her determination for me to succeed, has been a source of
financial support, real world ethics, and hard nosed encouragement.
To my loving wife, Brooke, for her constant drive, encouragement, and
optimism, which is in constant harmony with my pessimistic nature; for taking care of
me and pushing me when the walls seemed too high to scale.
To my friends, who won’t let me take “no” for an answer and insist that I push
on to make my mark. To the friends I have made in the research lab, which have
been there on the good and bad days and have pushed me to succeed.
To anyone who contributed directly or indirectly to the completion of this
thesis, and my committee members for taking the time to help me finish.
iii
VITA
May 6, 1978
Born in Great Bend, Kansas
1996
Graduated, Farmington High School, Farmington, New
Mexico
1999
CO-OP NASA, Johnson Space Center, Houston, Texas
2000
Graduated, B.S.E.E, New Mexico State University, Las
Cruces, New Mexico
2000-2002
Research Assistant, Department of Electrical and
Computer Engineering, New Mexico State University
PROFESSIONAL AND HONORARY SOCIETIES
Institute of Electrical and Electronics Engineers (IEEE)
PUBLICATIONS
1. J. Ramirez-Angulo and M. Holmes, “A Simple Technique to Significantly
Enhance Slew Rate and Bandwidth of One-Stage CMOS Operational Amplifiers.”
Proceedings of the 2002 International Symposium on Circuits and Systems,
Phoenix, Arizona, May 2002.
2. M. Holmes, J. Ramirez-Angulo, and R.G. Carvajal, “New Architectures of Class
AB CMOS and BICMOS Operational Amplifiers with Local Common Mode
Feedback” Proceedings of the 2002 Midwest Symposium on Circuits and Systems,
Tulsa, Oklahoma, August 2002.
3. J. Ramirez-Angulo and M. Holmes, “Simple Technique Using Local Common
Mode Feedback To Enhance Slew Rate and Bandwidth of One-Stage CMOS OpAmps.” Electronics Letters, vol. 38 (19), (in print), October 2002.
FIELD OF STUDY
Major Field: Electrical Engineering
Mixed Signal Microelectronics
iv
ABSTRACT
APPLICATION OF LOCAL COMMON MODE FEEDBACK TECHNIQUES
TO ENHANCE SLEW RATE AND GAIN-BANDWIDTH
CMOS OPERATIONAL AMPLIFIERS
BY
MICHAEL LEIGH HOLMES, STUDENT, B.S.
Master of Science, Electrical Engineering
New Mexico State University
Las Cruces, New Mexico, 2002
Dr. Jaime Ramirez-Angulo, Chair
Industry is continuously researching techniques to reduce power requirements,
while increasing speed, to meet the demands of today’s low (battery) powered
wireless systems. The operational transconductance amplifier (OTA) is a
fundamental building block in analog (mixed-signal) design and its performance
characteristics are the foundation of system level characteristics. Improving the
performance of the fundamental amplifier structure, while avoiding costly silicon area
and static power increases, is critical to improving system performance. The
application of Local Common Mode Feedback (LCMFB) [1-3] to the conventional
v
OTA structure provides significant increases in gain-bandwidth and slew rate
performance without an increase in static power and limited additional silicon area.
Both single ended and fully differential amplifier architectures are used in industry
for modern design. Fully differential amplifiers are used to provide additional signal
swing and reduce harmonic distortion characteristics. In the presented research, local
common mode feedback techniques are applied to both single ended and fully
differential operational transconductance amplifiers. LCMFB provides wide-range
programming of amplifier characteristics and increases the versatility of the amplifier
structure. A comparative analysis of LCMFB versus conventional structures via
theoretical calculation, simulation, and experimentation, emphasizes the benefits of
LCMFB in both single ended and fully differential structures. Results indicate gainbandwidth increases of a factor greater than 2 and slew rate increases at a factor close
to 4, with equal static power dissipation, and a minimal 15% increase in silicon area.
vi
TABLE OF CONTENTS
Page
LIST OF TABLES............................................................................................
xii
LIST OF FIGURES ..........................................................................................
xiii
1
INTRODUCTION ......................................................................................
1
1.1
The Operational Transconductance Amplifier.........................................
1
1.2
Local Common Mode Feedback..............................................................
3
1.3
Characterization Parameters ....................................................................
5
1.4
Research Focus ........................................................................................
5
2 THE CONVENTIONAL TRANSCONDUCTANCE AMPLIFIER..........
7
2.1
Introduction..............................................................................................
7
2.2
Operation..................................................................................................
8
2.3
Signal Analysis ........................................................................................
9
2.3.1
Open Loop Gain....................................................................................
9
2.3.2
AC Analysis ..........................................................................................
10
2.3.3
Gain Bandwidth ....................................................................................
12
2.3.4
Maximum Output Current.....................................................................
12
2.3.5
Slew Rate ..............................................................................................
12
DC Analysis .............................................................................................
13
Input Common Mode Range.................................................................
13
2.4.1.1
Minimum Input Voltage ....................................................................
13
2.4.1.2
Maximum Input Voltage....................................................................
14
Output Voltage Range...........................................................................
15
2.4
2.4.1
2.4.2
vii
2.4.3
Static Power Dissipation .......................................................................
16
Characterization .......................................................................................
16
2.5.1
Gain and Phase Margins .......................................................................
16
2.5.2
Input Offset Voltage .............................................................................
17
2.5.2.1
Random Offset ...................................................................................
17
2.5.2.2
Systematic Offset ...............................................................................
17
2.5.3
Total Harmonic Distortion....................................................................
18
2.5.4
Noise .....................................................................................................
19
2.5.4.1
MOSFET Noise Models ....................................................................
19
2.5.4.2
Cascode Stage Noise..........................................................................
21
2.5.4.3
Noise Analysis ...................................................................................
22
Fully Differential Implementation ...........................................................
23
Structure................................................................................................
23
2.6.2 Common Mode Feedback .....................................................................
25
2.6.3
Stability .................................................................................................
27
Conclusions..............................................................................................
27
3 THE PROPOSED TRANSCONDUCTANCE AMPLIFIER.....................
29
3.1
Introduction..............................................................................................
29
3.2
Operation..................................................................................................
30
3.3
Signal Analysis ........................................................................................
32
Open Loop Gain....................................................................................
32
Differential Input ...............................................................................
33
2.5
2.6
2.6.1
2.7
3.3.1
3.3.1.1
viii
3.3.1.2
Common Source Output Shell ...........................................................
34
3.3.1.3
Collective Open Loop Gain ...............................................................
35
3.3.2
AC Analysis ..........................................................................................
36
3.3.3
Gain Bandwidth ....................................................................................
38
3.3.4
Maximum Output Current.....................................................................
38
3.3.5
Slew Rate ..............................................................................................
39
DC Analysis .............................................................................................
39
3.4.1
Input Common Mode Range.................................................................
39
3.4.2
Output Voltage Range...........................................................................
40
3.4.3
Static Power Dissipation .......................................................................
40
Characterization .......................................................................................
40
3.5.1
Gain and Phase Margins .......................................................................
40
3.5.2
Input Offset Voltage .............................................................................
41
3.5.3
Total Harmonic Distortion....................................................................
41
3.5.4
Noise .....................................................................................................
41
3.5.4.1
MOSFET Noise Models ....................................................................
41
3.5.4.2
Cascode Stage Noise..........................................................................
42
3.5.4.3
Noise Analysis ...................................................................................
42
Fully Differential Implementation ...........................................................
43
Structure................................................................................................
43
3.6.2 Common Mode Feedback .....................................................................
44
3.6.3
45
3.4
3.5
3.6
3.6.1
Stability .................................................................................................
ix
3.7
Conclusions..............................................................................................
46
4 ANALYSIS.................................................................................................
47
4.1
Introduction..............................................................................................
47
4.2
Design ......................................................................................................
48
4.2.1
Design Specifications and Parameters ..................................................
48
4.2.2
Single Ended Conventional OTA .........................................................
49
4.2.2.1
Theoretical Design .............................................................................
49
4.2.2.2
Final Design .......................................................................................
51
4.2.3
Single Ended LCMFB OTA .................................................................
51
4.2.4
Fully Differential Conventional OTA...................................................
55
4.2.5
Fully Differential LCMFB OTA...........................................................
56
Calculation-Simulation-Experimentation ................................................
57
4.3.1
Parameters.............................................................................................
58
4.3.2
Results and Analysis .............................................................................
59
4.3.2.1
Open Loop Gain.................................................................................
59
4.3.2.2
Gain Bandwidth .................................................................................
60
4.3.2.3
Maximum Output Current..................................................................
62
4.3.2.4
Slew Rate ...........................................................................................
63
4.3.2.5
Static Power Dissipation ....................................................................
64
4.3.2.6
Gain and Phase Margin......................................................................
65
4.3.2.7
Input Offset Voltage ..........................................................................
65
4.3.2.8
Harmonic Distortion ..........................................................................
66
4.3
x
4.3.2.9
Noise ..................................................................................................
67
4.3.2.10
Common Mode Feedback Characterization.....................................
68
4.3.2.11
Silicon Area .....................................................................................
69
Conclusions..............................................................................................
70
5 APPLICATIONS ........................................................................................
72
5.1
Fully Differential Charge Scaling Digital-Analog Converter..................
72
5.1.1
Simulation Specifications and Parameters............................................
73
5.1.2
Results and Analysis .............................................................................
74
Proposed Applications .............................................................................
77
4.4
5.2
Appendices
A. DESIGN CALCULATIONS ......................................................................
79
B. THEORETICAL ANALYSIS CALCULATIONS.....................................
81
C. MICROGRAPHS ........................................................................................
90
D. INTERNET LINKS ....................................................................................
93
REFERENCES .................................................................................................
95
xi
LIST OF TABLES
Table
Page
4.1 Design Specifications and Parameters. .......................................................
48
4.2 Conventional OTA Theoretical Design Transistor Sizes............................
50
4.3 Conventional OTA Final Design Transistor Sizes......................................
51
4.4 SE-LCMFB MR1,2 Design Transistor Sizes..............................................
54
4.5 Fully Differential Conventional OTA Shell Transistor Sizes.....................
55
4.6 Fully Differential Conventional OTA CMFB Transistor Sizes..................
56
4.7 FD-LCMFB MR1,2 Design Transistor Sizes. ............................................
57
4.8 Simulation Parameters. ...............................................................................
58
4.9 Open Loop Gain Results.............................................................................
60
4.10 Gain Bandwidth Results. ..........................................................................
61
4.11 Maximum Output Current Results............................................................
62
4.12 Slew Rate Results. ....................................................................................
64
4.13 Static Power Dissipation Results. .............................................................
64
4.14 Gain and Phase Margin Simulation Results..............................................
65
4.15 Offset Voltage Simulation Results............................................................
65
4.16 Harmonic Distortion Simulation Results. .................................................
66
4.17 Total Input Noise at 10MHz. ....................................................................
68
4.18 Common Mode Feedback Circuit Simulation Results..............................
69
4.19 Analysis Summary Results. ......................................................................
70
5.1 Fully Differential Charge Scaling DAC Design Parameters ......................
73
5.2 Simulated DAC Specifications Summary...................................................
76
xii
LIST OF FIGURES
Figure
Page
1.1 OTA Symbol and Equivalent Circuit..........................................................
1
1.2 Conventional One Stage Operational Transconductance Amplifier...........
2
1.3 OTA Structure with Local Common Mode Feedback Resistors: R1,R2....
3
1.4 OTA with Local Common Mode Feedback Transistors MR1,2.................
4
2.1 Conventional One Stage Operational Transconductance Amplifier...........
7
2.2 Conventional One Stage OTA Open Loop Gain Schematic.......................
9
2.3 Conventional One Stage OTA AC Analysis Schematic. ............................
10
2.4 Input Differential Pair With Diode Connected Load..................................
13
2.5 Conventional OTA Cascoded Output. ........................................................
15
2.6 MOSFET With Thermal (iTH2(f)) and Flicker (iFL2(f)) Noise Sources. ......
19
2.7 Simplified MOSFET Noise Model. ............................................................
20
2.8 Cascode Output Stage With Cascode Transistor Noise Sources (Vn2). ......
21
2.9 Conventional OTA with MOSFET Noise Sources.....................................
22
2.10 Fully Differential Conventional OTA and Common Mode Feedback
Circuit. ......................................................................................................
23
2.11 Implemented Dual Shell Fully Differential Conventional OTA...............
24
3.1 OTA With Local Common Mode Feedback...............................................
29
3.2 LCMFB OTA With MOS Transistors MR1,MR2......................................
30
3.3 LCMFB OTA Differential Input Stage.......................................................
33
3.4 (a) Input Stage Simplified Gain Analysis Schematic (b) Small Signal
Equivalent Circuit (c) Simplified Small Signal Equivalent Circuit...........
33
xiii
3.5 LCMFB OTA Common Source Output Shell. ...........................................
35
3.6 LCMFB One Stage OTA AC Analysis Schematic. ....................................
36
3.7 LCMFB OTA Maximum Output Current Schematic. ................................
38
3.8 LCMFB OTA with MOSFET Noise Sources.............................................
42
3.9 Fully Differential LCMFB OTA And Common Mode
Feedback Circuit. ........................................................................................
44
4.1 Diagrams: (a) SE-CONV (b) SE-LCMFB (c) FD-CONV
(d) FD-LCMFB...........................................................................................
47
4.2 Conventional One Stage Operational Transconductance Amplifier...........
49
4.3 Single Ended OTA with Local Common Mode Feedback. ........................
52
4.4 SE-LCMFB OTA MR1,2 Design Schematic..............................................
53
4.5 Fully Differential, Dual Shell, Conventional OTA.....................................
55
4.6 Fully Differential OTA with Local Common Mode Feedback. .................
56
4.7 Open-Loop Simulation Circuit Configurations: (a) SE (b) FD. .................
59
4.8 Gain-Bandwidth Test Circuit Configurations: (a) SE (b) FD.....................
60
4.9 Maximum Output Current Test Circuit Configurations: (a) SE (b) FD......
62
4.10 Slew Rate Test Circuit Configurations: (a) SE (b) FD. ............................
63
4.11 OTA Total Input Noise Simulation Plots (a) SE (b) FD...........................
67
4.12 CMFB Open Loop Characterization Simulation Circuit
Configuration. ...........................................................................................
68
4.13 Layout (a) SE-CONV (b) SE-LCMFB (c) FD-CONV
(d) FD-LCMFB.........................................................................................
69
5.1 Fully Differential Charge Scaling Analog-Digital Converter.....................
72
5.2 FD-CONV DAC Analysis Plots (a) DNL (b) INL. ....................................
74
xiv
5.3 FD-LCMFB DAC Analysis Plots (a) DNL (b) INL. ..................................
75
5.4 Transient, Full Scale Settling Time Response. ...........................................
76
Figure C.1 Micrograph of Fabricated SE-CONV Structure (11880µm2) ..............
91
Figure C.2.2 Micrograph of Fabricated SE-LCMFB Structure (14421µm2) ........
91
Figure C.3 Micrograph of Fabricated FD-CONV Structure (32340µm2)..............
91
Figure C.4.4 Micrograph of Fabricated FD-LCMFB Structure (36822µm2) .......
91
Figure C.5.5 Micrograph of Fabricated 0.5um CMOS Test Chip ....................
92
xv
1
INTRODUCTION
1.1
The Operational Transconductance Amplifier
The schematic symbol and equivalent circuit model for an Operational
Transconductance Amplifier (OTA) are shown in Figure 1.1(a),(b) respectively.
io
VI(+)
VI(-)
+
_
VO
+
vi
_
(a)
+
Gmvi
Ri
RO vo
_
(b)
Figure 1.1 OTA Symbol and Equivalent Circuit.
The OTA converts an input voltage to an output current relative to a transconductance
gain parameter Gm=io/vi. Ideally the input and output resistances are infinite
(Ri=Ro=∞) such that ii=iRo=0 and the output current is absorbed solely by the load.
The conventional OTA is classified as a class A amplifier and is capable of
generating maximum output currents equal to the bias current applied. The
equivalent circuit model indicates the transconductance amplifier generates an output
current (io) proportional to an input voltage (vi) based on the transconductance gain
Gm. The open circuit voltage gain of the conventional OTA model in Figure 1.1 (b) is
given by A=GmRo.
A conventional, one stage, CMOS, Operational Transconductance Amplifier
(OTA) configuration is shown in Figure 1.2.
1
Vdd
M5
1:K
K:1
M6
M4
M3
Vcasp
Vi(-)
M1
M2
Vi(+)
Vout
Ibias
MB1
M10
MB2
M7
Vcasn
M9
M8
Vss
Figure 1.2 Conventional One Stage Operational Transconductance Amplifier.
The OTA employs a differential input pair and three current mirrors. The differential
input pair is comprised of transistors M1,2. The differential pair is biased by MB1,2.
Mirrors formed by M3,5 and M4,6 reflect currents generated in the differential pair to
the output shell. The current generated by the mirror of M3,5 is then reflected to the
output via the mirror formed by M7,8. The mirror gain factor, K, indicates the gain in
mirrors formed by M3,5 and M4,6 with the following relations: β5=Kβ3, β6=Kβ4
where β=(KP/2)(W/L). Cascoding transistors M9,10 are biased by Vcasn/Vcasp and
provide increased gain via increased (cascoded) output resistance.
The conventional OTA is differentiated from other amplifiers by the fact that its
only high impedance node is located at the output terminal. The conventional OTA
does not employ an output buffer and is therefore, only capable of driving capacitive
loads. The gain of the OTA (GmRo) is dependent on the large output resistance of the
2
shell (M5-M10) and is decreased to GmRo//RL≈GmRL if a parallel resistive load RL is
applied. A detailed analysis of the conventional OTA is presented in Chapter 2.
1.2
Local Common Mode Feedback
Industry is researching techniques to reduce power requirements, while
increasing speed, to meet the demands of low (battery) powered wireless systems.
These systems require amplifiers with low bias currents, capable of producing large
dynamic currents. Application of Local Common Mode Feedback (LCMFB) [1-3]
techniques to the conventional OTA architecture produces an efficient class AB
amplifier with enhanced gain-bandwidth and slew rate. An OTA structure, with local
common mode feedback, provided by R1,R2, is shown in Figure 1.3.
Vdd
M5
C
M3
K:1
A
Id3
Id4
R1
Vi(-)
M4
M1
M2
Id1
M6
B
Vcasp
R2
IR
1:K
M10
Vi(+)
Id2
Vout
Ibias
MB1
MB2
M7
Vcasn
M9
M8
Vss
Figure 1.3 OTA Structure with Local Common Mode Feedback Resistors: R1,R2.
3
The active load transistors M3,4 are reconnected to have a common gate (node C) and
matched resistors R1, R2 are used to connect the gate and drain terminals of M3, M4.
Resistors R1,R2 can be implemented with PMOS transistors MR1,2 operating in the
triode region as shown in Figure 1.4 below.
Vdd
M5
C
M3
A
Vi(-)
MR1
M6
M4
B
MR2
M1
VR
Vcasp
M2
M10
Vi(+)
Vout
Ibias
MB1
MB2
M7
Vcasn
M9
M8
Vss
Figure 1.4 OTA with Local Common Mode Feedback Transistors: MR1,2.
Control of the gate voltage of MR1,2 (VR) provides control of the triode resistance
generated. This variable resistance (voltage) allows programmability of the OTA and
provides increased gain-bandwidth and slew rate via a tradeoff in gain and phase
margin. A detailed analysis of the LCMFB OTA is presented in Chapter 3.
4
1.3
Characterization Parameters
Several common characterization methods are used to classify the
functionality of OTA structures. These performance measurement techniques will be
used to analyze designed structures via theoretical calculation, simulation, and
experimentation throughout the documentation presented in the following chapters.
A list of the measured characteristics is provided below. Detailed definitions and
derivations are provided in Chapter 2.
1. Open Loop Gain (AOL)
2. Gain Bandwidth(GB)
3. Maximum Output Current (IOUTMAX)
4. Slew Rate (SR)
5. Static Power Dissipation (PSTATIC)
6. Gain/Phase Margin (GM/PM)
7. Offset Voltage (VOS)
8. Harmonic Distortion (THD)
9. Noise (i2ni)
1.4
Research Focus
Four OTA structures were designed, simulated, fabricated, and tested
experimentally as follows:
1. Single Ended Conventional (SE-CONV)
2. Single Ended with Local Common Mode Feedback (SE-LCMFB)
3. Fully Differential Conventional (FD-CONV)
4. Fully Differential with Local Common Mode Feedback (FD-LCMFB)
5
The focus of the research presented will be a detailed comparison and analysis of
performance characteristics of the designed single ended and fully differential OTA
structures. Chapter 2 will provide a detailed, theoretical analysis of the single ended
and fully differential conventional OTA structures. Likewise, Chapter 3 will provide
a detailed, theoretical analysis of the modified single ended and fully differential
OTA structures with local common mode feedback. Chapter 4 will present a
comparative summary of performance characteristics (outlined in Section 1.3) of all
four OTA structures via theoretical calculation, simulation, and experimental results.
An outline of applications, including implementation of a fully differential, charge
scaling, digital to analog converter will be discussed in Chapter 5.
6
2
2.1
THE CONVENTIONAL TRANSCONDUCTANCE AMPLIFIER
Introduction
A conventional, one stage, Operational Transconductance Amplifier (OTA)
configuration is shown in Figure 2.1.
Vdd
M5
1:K
K:1
M6
M4
M3
Vcasp
Vi(-)
M1
M2
Vi(+)
Vout
Ibias
MB1
M10
MB2
M7
Vcasn
M9
M8
Vss
Figure 2.1 Conventional One Stage Operational Transconductance Amplifier.
The OTA employs a differential input pair and three current mirrors. The differential
input pair is comprised of transistors M1,2. The differential pair is biased by MB1,2.
Mirrors formed by M3,5 and M4,6 reflect currents generated in the differential pair to
the output shell. The current generated by the mirror of M3,5 is then reflected to the
output via the mirror formed by M7,8. The mirror gain factor, K, indicates the gain in
mirrors formed by M3,5 and M4,6 with the following relations: β5=Kβ3, β6=Kβ4
where β=KP/2(W/L). In the following analysis, it will be shown that an increase in K
will increase the slew rate and gain bandwidth of the conventional OTA at the cost of
7
increased area/static power dissipation and a decrease in phase margin. Cascoding
transistors M9,10 are biased by Vcasn/Vcasp and provide increased gain via increased
(cascoded) output resistance.
2.2
Operation
The conventional OTA (Figure 2.1) uses a differential pair in conjunction with
three current mirrors to convert an input voltage into an output current. Common
mode signals (Vi(+)=Vi(-)) are, ideally, rejected. For a common mode input voltage,
the currents are constant and will be: id1=id2=IBIAS/2, and iout=0. A differential input
signal will generate an output current proportional to the applied differential voltage
based on the transconductance of the differential pair. Although the output stage is a
push-pull structure, the conventional OTA is only capable of producing an output
current with a maximum amplitude equal to the bias current in the output shell
(K*IBIAS,OS). For this reason, the conventional OTA is a referenced as a class A
structure capable of producing maximum signal currents equal to that of the bias
current applied. Slew rate (SR) is directly proportional to the maximum output
current and is defined as the maximum rate of change of the output voltage. For a
single stage amplifier, the slew rate is the output current divided by the total load
capacitance. The conventional OTA therefore suffers the consequence that high
speed requires large bias currents which translates to large static power dissipation.
Wireless and battery powered systems require high slew rate and gain bandwidth
values with low static power dissipation. These requirements are difficult to achieve
with class A structures such as the conventional OTA. The proposed class AB
8
structure with Local Common Mode Feedback (LCMFB), presented in Chapter 3, can
meet these requirements [2].
2.3
Signal Analysis
2.3.1
Open Loop Gain
Figure 2.2 will be referenced to determine the open loop gain.
Vdd
1:K
K:1
M5
M6
M4
M3
Id2
Id1
Vcasp
Vi(-)
M1
Id2
Id1
M2
M10
Vi(+)
Iout
Rout
Ibias
Vcasn
M9
Id1
M7
M8
Vss
Figure 2.2 Conventional One Stage OTA Open Loop Gain Schematic.
The output current, in terms of the mirror gain factor (K), is given by:
iout = Kid 2 − Kid 1
(2.1)
id 1 = gm1Vi (−), id 2 = gm2Vi (+)
(2.2)
where:
Assuming: gm1=gm2, and substituting (2.2) into (2.1):
iout = Kgm1, 2 (Vi (+) − Vi (−))
9
(2.3)
This indicates the transconductance gain of the OTA is given by:
Gm = Kgm1, 2
(2.4)
The output resistance is a cascode resistance and is given by:
ROUT = gm10 ro10 ro 6 // gm9 ro 9 ro8
(2.5)
Combining (2.3) and (2.5), the output voltage is then given by:
vout = iout Rout = Kgm1, 2 (Vi (+) − Vi(−))( gm10 ro10 ro 6 // gm9 ro 9 ro8 )
(2.6)
and the open loop gain is:
AOL =
2.3.2
vout
= Kgm1, 2 ( gm10 ro10 ro 6 // gm9 ro 9 ro8 )
vin
AC Analysis
Figure 2.3 will be referenced for AC analysis.
Vdd
M5
Cgs5
K:1
Cgd5
Cgs3 Cgs4
Cgs6
M3
Cdb3
Cgd1
Vi(-)
1:K
M6
M4
A
B
Cdb1
Cdb2
M1
M2
Cgd6
Cdb4
Cgd2
Vcasp
M10
Cgd10
Cdb10
Vi(+)
Iout
OUT
Ibias
CL
Cgd9
M9
Vcasn
Cdb9
Id1
M7
M8
Vss
Figure 2.3 Conventional One Stage OTA AC Analysis Schematic.
10
(2.7)
The gain bandwidth of the conventional one stage OTA is limited mainly by the low
impedance, high frequency, poles at nodes A/B, in conjunction with the high
impedance, low frequency pole at the output node [2].
The following analysis will define the high frequency pole and will assume
nodes A and B are equivalent nodes in terms of resistance and parasitic capacitance
(M1=M2, M3=M4, and M5=M6). The resistance at nodes A/B is dominated by the
diode connected resistance (1/gm) of M3,4 and is given by:
R A, B =
1
1
// ro1, 2 ≈
gm3, 4
gm3, 4
(2.8)
The parasitic capacitance at A/B is given by:
C A, B = C gd 1, 2 + C db1, 2 + C db 3, 4 + C gs 3, 4 + C gd 5, 6 + C gs 5, 6 ≈ C gs 3, 4 + C gs 5,6
(2.9)
Combining (2.8), (2.9), and the relation Cgs5,6=KCgs3,4 the pole at A/B is:
f pA, B =
1
2πC A, B R A, B
=
gm3, 4
2πC gs 3, 4 ( K + 1)
(2.10)
The output node capacitance is dominated by the load capacitance (CL) and is:
COUT = Cdg 9 + Cdb 9 + Cdg10 + Cdb10 + CL ≈ CL
(2.11)
Combining (2.5) and (2.11), the dominant pole/bandwidth of the OTA is given by:
f pOUT =
1
2πCOUT ROUT
=
1
= f 3dB
2πCL ( gm10 ro10 ro 6 // gm9 ro 9 ro8 )
11
(2.12)
This analysis indicates the relation between the phase margin and the mirror
gain factor (K). Equation (2.10) indicates the high frequency pole fpA,B is inversely
proportional to K. An increase in K will result in a decrease in fpA,B and consequently
a decrease in phase margin. The bandwidth of the conventional OTA is given in
Equation (2.12) and is inversely proportional to the load capacitance (CL).
2.3.3
Gain Bandwidth
Equations (2.7) and (2.12) are combined for the gain bandwidth (GB) product:
GB =
Kgm1, 2
2πC L
(2.13)
This relation indicates that the GB is directly proportional to K.
2.3.4
Maximum Output Current
The maximum output current of the conventional OTA is limited by the
mirror gain factor (K) and the bias current and is given by:
MAX
I OUT
= KI BIAS
2.3.5
(2.14)
Slew Rate
The slew rate (SR) is given by:
SR =
MAX
I OUT
KI
= BIAS
CL
CL
The slew rate therefore, increases linearly with K.
12
(2.15)
2.4
2.4.1
DC Analysis
Input Common Mode Range
The common mode range (CMR) is defined as the range of voltage
(VINMAX ,VINMIN ) for which the input differential pair will remain in saturation. This
range is determined by the amplifier structure, transistor sizes, and bias current. For
the differential input stage with diode connected loads, the minimum and maximum
input voltages can be found by analysis of Figure 2.4.
Vdd
Vsg3
M4
M3
M1
Vds1
M2
Vi+
Vgs1
Vbias
MB2
Ibias
VdsMB2
Vss
Figure 2.4 Input Differential Pair With Diode Connected Load.
2.4.1.1 Minimum Input Voltage
The minimum input voltage can be expressed as:
SAT
Q
SAT
SAT
VINMIN = VSS + VDSMB
2 + VGS 1 = VSS + VDSMB 2 + VDS 1 + VTHN 1
and substituting:
13
(2.16)
SAT
=
VDS
2I D L
WKP
(2.17)
The minimum input voltage becomes:
VINMIN = VSS +
2 I BIAS LMB 2
I L
+ BIAS 1 + VTHN 1
WMB 2 KPN
W1KPN
(2.18)
where VTHN1 is body effected and may be larger than the zero bias threshold voltage.
The minimum input voltage is therefore limited by the VDS,SAT drop requirements
across M1,MB2 and a threshold drop across M1. The minimum input voltage is
inversely proportional to the widths of transistors M1,MB2 and directly proportional
to the bias current. To reduce VINMIN the bias current must be reduced or the widths of
the input transistors must be increased.
2.4.1.2 Maximum Input Voltage
The maximum input voltage (Figure 2.4) and can be expressed:
Q
SAT
Q
VINMAX = VDD − VSG
3 − VDS 1 + VGS 1 = VDD − VSG 3 + VTHN 1
(2.19)
and with substitution of (2.17):
 I L

VINMAX = VDD −  BIAS 3 + VTHP 3  + VTHN 1
 W3 KPP

(2.20)
Again, VTHN1 is body effected and will be larger than anticipated. In this case, the
body effect actually increases input range by contributing to VINMAX . These results
indicate the bias current must be reduced and the width of M3 must be increased to
14
increase VINMAX . The maximum input voltage is, therefore, only limited by a VGS drop
across M3. For this reason, the input voltage range is typically limited by VINMIN . The
common mode range of the NMOS differential pair is capable of swinging further in
the positive direction than the negative direction.
2.4.2
Output Voltage Range
MAX
MIN
The output voltage range is defined as VOUT
, VOUT
which represents the
maximum output swing available. The output range of the conventional OTA is
reduced due to cascoding at the output shown in Figure 2.5.
Vdd
Vi+
M6
Vcasp
M10
Iout
Vcasn
M9
Vi-
M8
Vss
Figure 2.5 Conventional OTA Cascoded Output.
The output voltage range is given as:
MAX
VOUT
= VDD − VDS , SAT 6 − VDS , SAT 10
15
(2.21)
MIN
VOUT
= VSS + VDS , SAT 8 + VDS , SAT 9
2.4.3
(2.22)
Static Power Dissipation
The static power dissipation (PSTATIC) is the product of the sum of the currents
flowing through the current sources or sinks with the power supply voltages and is
given by [3]:
PSTATIC = (VDD − VSS )[ I D ,M 1 + I D ,M 2 + I D ,M 5 + I D ,M 6 + I D ,MB1 ]
(2.23)
and in terms of IBIAS and K (Figure 2.1):
PSTATIC = (VDD − VSS )I BIAS (2 + K )
(2.24)
An increase in the mirror gain factor (K) will increase the SR and GB of the
conventional OTA at the cost of increased area and static power dissipation and a
decrease in phase margin.
2.5
2.5.1
Characterization
Gain and Phase Margins
The application of negative feedback requires analysis of the open loop gain.
Some circuits will cause a phase shift in the input signal large enough that the
feedback becomes positive (adds to the input), resulting in an unstable system [4].
Stability requires a phase shift in the feedback signal less than 180° for open loop
gain values larger than 0dB. This requirement necessitates the definition of two
measures of stability: gain margin (GM) and phase margin (PM). Gain and phase
margin parameters can be measured via analysis of the open loop AC response
simulation. The gain margin is defined as the difference (in dB) in the gain at a phase
16
of -180° and unity gain. Design guidelines typically specify a GM greater than 10dB.
The phase margin is defined as the difference (in degrees) in the phase at unity gain
and -180°. The phase margin should be greater than 45° with an optimum, critically
damped, value of 60° [5]. For PM values less than 60° the system is under-damped,
and the transient response will indicate increased slew rate at the cost of rise and fall
peaking. For PM values greater than 60° the system is over-damped, and the
transient response will indicate decreased slew rate. Phase margin depends on the
relative position of the high frequency pole fpA (Figure 2.3) and the gain bandwidth
(unity gain frequency). The position of the high frequency pole location is therefore
directly related to the phase margin.
2.5.2
Input Offset Voltage
Ideally, if both inputs of the OTA are grounded, the output voltage should be
zero [4]. Practically, a nonzero output voltage (offset) will be present and is due to
random and systematic errors.
2.5.2.1 Random Offset
Random errors are due to mismatches in the input stage as a result of
fabrication including (but not limited to): threshold voltage differences and geometric
differences. Random errors can be estimated via Monte Carlo simulations [4].
2.5.2.2 Systematic Offset
Systematic errors are inherent to the design. Systematic errors can be the
result of non-symmetries in the OTA design, creating voltage and current
mismatches. The systematic offset can be determined via simulation and will be
17
evident in the DC sweep simulation as the offset from the zero-zero intercept where
the input voltage and output voltage should both equal zero.
2.5.3
Total Harmonic Distortion
Ideally, the output of an amplifier is a replica of the input signal scaled by the
gain A. The gain for large signal inputs is dependent on the input signal amplitude
[4]. For a purely sinusoidal input signal:
Vin (t ) = VM sin(ωt )
(2.25)
The non-ideal output signal of an amplifier can be expressed as:
Vout (t ) = a1VM sin(ωt ) + a2VM sin(2ωt ) + ....... + anVM sin(nωt )
(2.26)
where the desired output is the fundamental a1VMsin(ωt) and ideally, a2 through an are
zero [3]. The nth term harmonic distortion is then given by:
HDn =
an
,n >1
a1
(2.27)
and the total harmonic distortion (THD) of the amplifier is given by:
THD =
a22 + a32 + a42 + .... + an2
a12
(2.28)
The THD provides a measure of the ratio of the magnitude of output signal harmonics
to the desired fundamental output.
18
2.5.4
Noise
2.5.4.1 MOSFET Noise Models
The dominant sources of noise in MOS transistors are thermal and flicker
noise [6]. These noise parameters must be modeled for circuit noise analysis.
Figure 2.6 shows a schematic of a transistor with both thermal and flicker noise
sources.
iTH2(f)
iFL2(f)
Figure 2.6 MOSFET With Thermal (iTH2(f)) and Flicker (iFL2(f)) Noise Sources.
Thermal noise is due to thermal excitation of charge carriers in a conductor
[5]. It is proportional to temperature. Thermal noise can be modeled as a current
source iTH2(f) (Figure 2.6) in parallel with the transistor. The thermal noise (current
source) can be approximately modeled with the following relation:
2
2
iTH
( f ) = 4kT ( ) gm∆f
3
(2.29)
where k is Boltzmann’s constant (1.38*10-23 JK-1), T is the temperature in Kelvin, gm
is the transconductance of the transistor, and ∆f is the bandwidth in hertz [6].
19
Flicker noise is present under DC conditions and is the result of electron
trapping (delayed release) due to silicon imperfections in the transistor [5]. Flicker
noise is inversely proportional to frequency and is commonly referred to as 1/f noise.
The flicker noise can be modeled with a current source iFL2(f) (Figure 2.6) in parallel
with the transistor.
The current source is modeled with the following equation:
I Dα
i (f)= K
∆f
f
2
FL
(2.30)
where K is the (technology dependent) flicker noise constant, ID is the drain/bias
current, α is a constant (0.5> α <2), and f is the frequency in hertz [6].
A simplified model for transistor noise is shown in Figure 2.7:
in2(f)
Figure 2.7 Simplified MOSFET Noise Model.
The single current noise source can be modeled with the following equation:
Iα
2
i n2 ( f , T ) = 4kT ( gm)∆f + K D ∆f
3
f
20
(2.31)
This equivalent noise source expression is a combination of the thermal (2.29) and
flicker (2.30) noise source equations. This model is accurate for long channel devices
(>1µm). For short channel devices, the thermal noise (first term in Equation 2.31)
may be 2 to 5 times larger than shown [6]. The equivalent noise current source (in2)
can also be represented as a voltage source (vn2) in series with the gate of the
transistor based on the relation vn2=in2/gm2 [6].
2.5.4.2 Cascode Stage Noise
The noise contribution of the output stage cascoding transistors (M9,10)
shown in Figure 2.8 is negligible [7].
Vdd
Vi+
M6
X
2
vn,M9
M10
Iout
2
vn,M10
M9
Y
Vi-
M8
Vss
Figure 2.8 Cascode Output Stage With Cascode Transistor Noise Sources (Vn2).
Cascode transistor noise sources, modeled as voltage sources v2n,M9 and v2n,M10,
introduce a small voltage differential at the gate of transistors M9,10 respectively.
21
This small voltage differential is coupled to nodes X and Y (drains of M6,9) through
M9,10. Transistors M6,9 are operating in saturation and their drain current is
therefore insensitive to small changes in their VDS voltages. Thus, cascode transistors
contribute virtually no noise to the circuit.
2.5.4.3 Noise Analysis
Figure 2.9 shows the conventional OTA structure with MOSFET noise
sources.
Vdd
K:1
in,M5
2
M5
2
in,M3
1:K
2
in,M4
M3
M4
Vcp
Vi(-)
M1
2
in,M2
2
in,M1
M2
2
in,M6
M6
M10
2
in,M10
Vi(+)
Vout
Ibias
Vcn
2
in,M7
M7
M9
2
in,M9
M8
2
in,M8
Vss
Figure 2.9 Conventional OTA with MOSFET Noise Sources.
Assuming matching (M1=M2, KM3=KM4=M5=M6, M7=M8), neglecting the noise
introduced by cascoding transistors M9, M10, and neglecting common mode noise
introduced by the biasing transistors (the output is taken as a difference, eliminating
common mode noise), the input referred noise can be derived (in terms of K and in2)
as follows.
22
ini2 ,OTA = 2[in2, M 1 + in2, M 3 +
1 2
(in , M 5 + in2, M 7 )]
2
K
(2.32)
For unity mirror gain (K=1) the equivalent noise is just the summation of transistor
noise sources M1-M8. The noise in transistors M5-M8 decreases with a factor 1/K2,
indicating a decrease in noise with an increase in current.
2.6
2.6.1
Fully Differential Implementation
Structure
A conventional, fully differential (FD), implementation of the one stage OTA
with common mode feedback circuitry is shown in Figure 2.10. Advantages of the
fully differential structure include: improved output voltage swing, less susceptibility
to common mode noise, and cancellation of even-order nonlinearities [6].
Vdd
M5
K:1
1:K
M4
M3
Vdd
B
A
M7
M6
Vcasp
Vcasp
M8
M14
M15
Vbiasp
Vi(-)
M1
M2
Vi(+)
Vcmref
Vo(+)
Vo(-)
M9
Vcasn
Vcasn
M16
Vo(+)
M18
M17
M19
M10
Vcm
M20
M11
Vbiasn
Vcm
M12
K/2:1
Vbiasn
M21
M13
1:K/2
Vss
Vss
Common Mode Feedback Circuit
Fully Differential Conventional OTA
Figure 2.10 FD Conventional OTA and Common Mode Feedback Circuit.
23
Vo(-)
The architecture of the fully differential OTA is similar to that of its single
ended counterpart (Figure 2.1) with the following exceptions. First, the mirror in the
single ended architecture, formed by transistors M7-8, has been replaced with
cascoded current mirrors, biased by Vbiasn, and formed by M9,11 / M10,13. Second, a
common mode feedback circuit formed by transistors M14-21 has been implemented
to control the common mode output voltage. Lastly, the bias current for the
differential pair is now controlled actively by the common mode feedback circuit via
the control voltage Vcm. This design lacks current mirroring capability generated by
M7,8 (Figure 2.1) for the single ended structure and is therefore only capable of a
maximum output current at each output equal to half the bias current.
In order to achieve output currents equal to the bias current at each output, the
dual shell structure shown in Figure 2.11 was implemented.
Vdd
M11
iD3
M5
iD4
M6
M3
Vdd
B
A
M16
M12
M4
Vcasp
Vcasp
M19
M18
M17
M10
M20
Vbiasp
Vi(-)
M1
M2
iD1
Vi(+)
ID2
M21
Vo(+)
Vo(-)
Ibias
ICM
Vcasn
ICM
M15
Vcasn
Vcmref
M22 Vo(+)
M23
M25
M24
M26
ICM
M9
D
M27
M7
Vcasp
M28
M29
M30
M8
ICM
Vss
E
M13
M14
Vss
Common Mode Feedback Circuit
Fully Differential Conventional OTA
Figure 2.11 Implemented Dual Shell Fully Differential Conventional OTA.
24
Vo(-)
This fully differential OTA maintains mirroring capability via mirrors formed by
M7,8 and M13,14 and is capable of generating maximum output currents equal to
IBIAS at each output terminal.
2.6.2
Common Mode Feedback
The implemented common mode feedback (CMFB) circuit for the dual shell structure
(Figure 2.11) is more complex than that of the CMFB circuit for the standard fully
differential OTA (Figure 2.10) but still utilizes dual differential pairs and performs
the same function. The dual differential pair structure introduces only a small
capacitive load (Cgs16,19) at the output of the OTA avoiding resistive loading common
to many CMFB circuits. The function of the common mode feedback circuit is to
define/control the common mode voltage such that:
vo (+) = vo (−) = vcmref = vcm
(2.33)
when a common mode input is applied (vi(+)=vi(-)).
Vcmref is typically set to:
vcmref =
VDD − Vss
= vcm
2
(2.34)
such that for complementary sources, vcm=0. The common mode reference voltage
(Vcmref, Figure 2.10) is compared with vo,cm given by:
vo , cm =
vo (+) − vo (−)
2
via the dual differential pairs.
25
(2.35)
The common mode voltage of the conventional, fully differential, dual shell, OTA is
controlled via current injection from the common mode feedback circuit at low
impedance nodes D/E (Figure 2.11).
The CMFB circuit utilizes two, identical, current mirrors, formed by M27,29 and
M28,29, to generate replica correction currents (ICM) which are injected at low
impedance nodes D/E. These mirrors are required to provide correction currents for
each complementary shell independently. Active control of the bias current will not
correct the common mode voltage of the dual shell fully differential OTA due to the
mirroring function of the shell structures. Adjustment of the bias current would result
in complementary voltage changes at nodes A/B, resulting in complementary drain
current changes for M5,6 and M11,12. The shell structure would mirror these
complementary changes to the output, resulting in zero net voltage change. Replica
common mode correction currents ICM are therefore required to facilitate independent
shell common mode correction. Based on this analysis, two common mode voltage
correction scenarios are possible (referencing Figure 2.11) as follows:
1. If vo,cm > vcmref, less current is passed through M29. This decrease in current is
mirrored to M27,28. ID27,28 is fixed by transistors M17,18 respectively. The
excess current id17,18 generated by these transistors is then injected at nodes
E/D (transistors M7,13) and coupled to the output via mirror transistors
M8,14. The resulting increase in iD8,14 pulls current from the output node and
the output voltage is reduced, to attain: vo(+) = vo(-) = vcmref (Equation 2.33).
26
2. If vo,cm < vcmref, more current is passed through M29. This increase in current
is mirrored to M27,28. ID27,28 is fixed by transistors M17,18 respectively.
The required increase in current is then pulled from nodes D/E (transistors
M7,13) and coupled to the output via mirror transistors M8,14. The resulting
decrease in iD8,14 injects current at the output node and the output voltage is
increased, to attain: vo(+) = vo(-) = vcmref (Equation 2.33).
2.6.3
Stability
Since the CMFB loop is a negative feedback loop, stability is a key issue [4].
The CMFB structure has a dominant low frequency pole (fpIN) at the input (due to CL)
and four high frequency poles associated with diode connected transistors M27,28
and the feedback injection transistors M7,13 (nodes D/E, Figure 2.11). The gain and
phase margin of the CMFB circuit must also be verified and remain within the
parameters outlined in Section 2.5.1.
2.7
Conclusions
A full analysis of the one-stage conventional OTA structure was presented.
The transconductance amplifier rejects common mode signals and generates an output
current dependent on the input voltage. Cascoding of the output shell to increase gain
necessitates the requirement of a purely capacitive load. The structure is class A and
the maximum output current is limited by the magnitude of the bias current in the
output shell. The mirror gain factor K (Figure 2.1) can be increased to increase the
maximum output current (slew rate) and gain bandwidth at the cost of an increase in
static power, and area, as well as a decrease in phase margin and stability.
27
Chapter 3 will provide a detailed analysis of the proposed OTA configuration with
local common mode feedback (LCMFB).
28
3
3.1
THE PROPOSED TRANSCONDUCTANCE AMPLIFIER
Introduction
The proposed operational transconductance amplifier (OTA), with local
common mode feedback (LCMFB) is shown in Figure 3.1.
Vdd
M5
C
M3
K:1
A
Id3
Id4
R1
Vi(-)
M4
M1
M2
Id1
M6
B
Vcasp
R2
IR
1:K
M10
Vi(+)
Id2
Vout
Ibias
MB1
MB2
M7
Vcasn
M9
M8
Vss
Figure 3.1 OTA With Local Common Mode Feedback.
Similar to the conventional OTA, the LCMFB OTA structure utilizes a differential
pair (M1,2) and three current mirrors (M3,5, M7,8, and M4,6). In the LCMFB circuit
however, the active load transistors M3,4 are reconnected to have a common gate
(node C) and matched resistors R1, R2 (Figure 3.1) are used to connect the gate and
drain terminals of M3, M4. This simple modification has several performance
enhancing benefits versus the conventional OTA architecture including class AB
operation which provides enhancement in slew rate (SR), gain bandwidth (GB), and
29
linearity, with equal static power dissipation. Implementation of resistors R1,R2 withh
MOS transistors MR1,MR2, shown in Figure 3.2, provides programmable
performance characteristics (via the control voltage VR), allowing utilization of the
same OTA for multiple applications. Class AB operation characteristics allow the
LCMFB structure to outperform the conventional structure with unity mirror gain.
The analysis for the LCMFB OTA will therefore be based on a unity mirror gain
factor (K=1, M3=M4=M5=M6, and M7=M8).
3.2
Operation
Figure 3.2 shows the LCMFB OTA structure with transistors MR1, MR2
implemented to function in the triode region and act as programmable resistors.
Vdd
iD3
M5
M3
iD4
MR1
B
MR2
M1
Vcasp
M2
VR
iD1
M6
M4
iR
A
Vi(-)
C
M10
Vi(+)
ID2
Vout
Ibias
Vcasn
M7
M9
M8
Vss
Figure 3.2 LCMFB OTA With MOS Transistors MR1,MR2.
30
For quiescent (or common mode) operation, the drain currents of transistors M1-M10
have equal values (ID1-10=Ibias/2) while the current iR in transistors MR1,2 is zero.
The gate-source voltage of M3,4 is the same as their drain-source voltage. For
common mode signals, these transistors perform as low impedance (diode connected)
loads with value:
RLCM =
1
gm3, 4
(3.1)
Upon application of a differential signal, the signal current component (id=ir) flows
through transistors MR1,2, and iD1,2 are given by:
iD1, 2 = I D + id =
I BIAS
± ir
2
(3.2)
where:


v
vd / 2

ir = gm1, 2 d 1 − 

2
 VGS 1, 2 − VTHN 1, 2 
2
(3.3)
and vd is the applied differential voltage. The drain currents in M3,4 remain
unchanged (iD3,4=IBIAS/2). The current ir generates differential complementary
voltage changes at nodes A and B while node C remains at a constant voltage. Signal
voltages at nodes A and B are given by:
v A = −vB = ir RMR1, 2
(3.4)
where RMR1,2 is the resistance generated by transistors MR1, MR2 and, based on the
triode channel resistance equation, is given by:
31
RMR1, 2 =
1
β MR1, 2 (VC − VR − VTH P )
(3.5)
Where VR is the applied control voltage (Figure 3.2), βMR1,2=KP(WMR1,2/LMR1,2), and
VC is the constant voltage at node C. This complementary swing at A,B generates
large, non-complimentary, signal currents in the shell (M5-10) of the OTA by
creating large gate-source voltage differentials for common source transistors M5,
M6, respectively.
3.3
3.3.1
Signal Analysis
Open Loop Gain
Calculation of the open loop gain of the LCMFB OTA structure requires two
independent analyses. The differential input must first be analyzed followed by the
common source output shell. The collective LCMFB OTA gain will then be defined
as the combination of the previous analyses. The following analysis will assume
transistor matching for the following devices M1=M2, M3=M4=M5=M6, M7=M8,
and MR1=MR2. The gain will be analyzed focusing on the path from the negative
input terminal (at the gate of M1) to the output terminal. This analysis will therefore
focus on transistors M1, M3, MR1, and M5 but it should be noted that analysis of the
positive signal input (at the gate of M2) would yield identical results with equivalent
transistor substitutions as listed above.
32
3.3.1.1 Differential Input
The differential input stage is shown in Figure 3.3.
Vdd
C
M3
A
Vi(-)
M4
MR1
B
MR2
M1
Vi(+)
M2
VR
Ibias
Figure 3.3 LCMFB OTA Differential Input Stage.
Given that the common combined gate of M3,4 (node C) is an AC ground, the circuit
can be simplified to the analysis circuit and small signal models (derived from the
MOSFET hybrid-π model) shown in Figure 3.4 (a), (b), and (c).
s3
M3
C
A
Vd
2
vsg3
vsg3=0
MR1
M1
g3
g1
Vd
2
id1
gm3vsg3
ro3
RMR1
g1
Vd
2
gm1vgs1
vgs1
d1,3
s1
gm1vgs1
vgs1
ro1
s1
(a)
(c)
(b)
Figure 3.4 (a) Input Stage Simplified Gain Analysis Schematic (b) Small Signal
Equivalent Circuit (c) Simplified Small Signal Equivalent Circuit.
33
RA,B
The source and gate terminals of M3 are grounded (vgs3=0) in the small signal model
eliminating the dependent current source gm3vgs3. Thus the small signal current is
given by:
id 1, 2 = gm1, 2 v gs1, 2
(3.6)
and the equivalent resistance is given by:
R A,B = ro1, 2 // ro 3, 4 // RMR1, 2
(3.7)
vA,B are then a combination of (3.6) and (3.7) and is given by:
v A,B = id 1, 2 Rout = (ro1, 2 // ro 3, 4 // RMR1, 2 )( gm1, 2 v gs1, 2 )
(3.8)
vd/2=vgs1,2 and the gain of the differential (ACORE) input stage is given by:
ACORE =
v A,B gm1, 2 RA,B ( gm1, 2 )(ro1, 2 // ro 3, 4 // RMR1, 2 )
=
=
vd
2
2
(3.9)
3.3.1.2 Common Source Output Shell
The common source output shell is shown in Figure 3.5 and consists of two
common source amplifiers (M5, M6), a current mirror (M7, M8), and cascoding
output transistors (M9, M10). The cascoded output provides the large output
resistance required for large gain in the output shell. The output resistance of the
LCMFB OTA is identical to that of the conventional OTA (Equation 2.5) and is given
by:
ROUT = gm10 ro10 ro 6 // gm9 ro 9 ro8
34
(3.10)
Vdd
M5
A
B
Vcasp
M6
M10
Vout
Vcasn
M7
M9
M8
Vss
Figure 3.5 LCMFB OTA Common Source Output Shell.
The current mirror has unity gain, and the gain of the output stage (AOS) is given by:
ASHELL = 2 gm5,6 ROUT = 2 gm5,6 ( gm10 ro10 ro 6 // gm9 ro9 ro8 )
(3.11)
3.3.1.3 Collective Open Loop Gain
The open loop gain of the LCMFB OTA is then given by the multiplication of
the gain of the input stage (ACORE, 3.9) and the output shell (ASHELL, 3.11) and is given
by:
AOL = gm1, 2 R A, B gm5, 6 ROUT
(3.12)
This definition indicates that the gain of the LCMFB OTA is a function of the
programmable resistance RMR1,2. This dependence provides an interesting
characteristic of functionality. For RMR1,2≈1/gm, RMR1,2 will dominate the parallel
combination ro1,2//ro3,4//RMR1,2, and the structure will behave as a one stage amplifier
35
(ACORE<<ASHELL). An increase in RMR1,2≈ro1,2//ro3,4 will result in increased gain in the
input stage and the structure will behave as a two stage amplifier (ACORE<ASHELL).
Two stage operation would eliminate the need for cascoding transistors M9,10 and
would require compensation.
3.3.2
AC Analysis
Figure 3.6 is referenced for AC analysis.
Vdd
M5
Cgd5
Cgs3 Cgs4
Cgs5
K:1
Cdb3
MR1
B
Cgd2
M1
Cdb1
M6
Cdb2
VR
Cgd6
Cdb4
MR2
Cgd1
Vi(-)
1:K
M4
CdbMR2
CdbMR1
A
Cgs6
C
M3
M2
Vcasp
M10
Cgd10
Cdb10
Vi(+)
Iout
OUT
Ibias
CL
Cgd9
M9
Vcasn
Cdb9
Id1
M7
M8
Vss
Figure 3.6 LCMFB One Stage OTA AC Analysis Schematic.
Similar to the conventional OTA, the frequency response of the LCMFB OTA is
determined mainly by the low impedance, high frequency, poles at nodes A/B, in
conjunction with the high impedance, low frequency pole at the output node.
36
The following analysis defines the high frequency pole and assumes nodes A and B
are equivalent nodes in terms of resistance and parasitic capacitance (M1=M2,
M3=M4, M5=M6, MR1=MR2). The resistance at nodes A/B (Equation 3.7) becomes
a function of the triode resistance (RMR1,2) created by MR1,2 and is given by:
R A, B = ro1, 2 // ro 3, 4 // RMR1, 2
(3.13)
Given that node C (Figure 3.6) is a virtual ground, the parasitic capacitance at nodes
A/B does not include Cgs3,4. The addition of MR1,2 does introduce an additional
parasitic Csb,MR1,2, but the well known relation Cgs >> Csb, and the relative dimensions
of the transistors W3 >> WMR, indicate the parasitic capacitance at A/B is reduced by a
factor close to 2 (K=1) versus the conventional structure. The parasitic capacitance at
A/B is given by:
C A, B = C gd 1, 2 + C db1, 2 + Cdb 3, 4 + C gd 5, 6 + C gs 5, 6 + C sbMR1, 2 ≈ C gs 5, 6
(3.14)
Combining equations (3.13) and (3.14), the pole at A/B is:
f pA,B =
1
2πC A,B R A,B
=
1
2πC gs 5,6 (ro1, 2 // ro3, 4 // RMR1, 2 )
(3.15)
The output node capacitance is dominated by the load capacitance and is equal to that
of the conventional structure (Equation 2.11):
COUT = Cdg 9 + Cdb 9 + Cdg10 + Cdb10 + CL ≈ CL
Combining (3.10) and (3.16), the dominant pole/bandwidth of the OTA is also
equivalent to the conventional structure (Equation 2.12) and is given by:
37
(3.16)
f pOUT =
3.3.3
1
2πCOUT ROUT
=
1
= f 3dB
2πCL ( gm10 ro10 ro 6 // gm9 ro 9 ro8 )
(3.17)
Gain Bandwidth
Equations (3.12) and (2.17) are combined for the gain bandwidth product:
GB =
[ gm1, 2 R A,B ][ gm5,6 ROUT ] [ gm1, 2 gm5,6 (ro1, 2 // ro 3, 4 // RMR1, 2 )]
=
2πC L ROUT
2πC L
(3.18)
The GB is dependent on the programmable resistance RMR1,2. As RMR1,2 increases, the
GB increases.
3.3.4
Maximum Output Current
The maximum output current can be found by analysis of Figure 3.7.
Vdd
C
M4
VMAX
GS
Q
VDS,SAT
MR2
Vcasp
VR
M6
MAX
IOUT
M10
Iout
Figure 3.7 LCMFB OTA Maximum Output Current Schematic.
Class AB operation provides large non-symmetric currents in the output shell. These
currents are created by the large gate-source voltage swings (generated at nodes A/B)
38
applied to M5,M6. Maximum output current generation occurs when the maximum
gate-source differential is applied to M6 (or M5) and M5 (or M6) is in cutoff.
The maximum output current is given by:
MAX
Q
MAX 2
I OUT
= β 5, 6 (VSD
,SAT 3, 4 + ∆VGS 5, 6 )
(3.19)
where:
∆VGSMAX
5, 6 =
I BIAS
RMR1, 2
2
(3.20)
represents the maximum swing at nodes A and B.
3.3.5
Slew Rate
The slew rate (SR) is then given by:
2
MAX
β 5, 6 (VSDQ , SAT 3, 4 + ∆VGSMAX
I OUT
5, 6 )
=
SR =
CL
CL
(3.21)
The slew rate is a function of ∆VGSMAX
5 , 6 (Equation 3.20) and is therefore directly
proportional to RMR1,2. An increase in RMR1,2 translates to an increase in the slew rate.
3.4
3.4.1
DC Analysis
Input Common Mode Range
The CMR of the LCMFB OTA is equivalent to the CMR of the conventional
structure. The analysis for the CMR can be found in Section 2.4.1.
39
3.4.2
Output Voltage Range
The output voltage range of the LCMFB OTA is also equivalent to the output
range of the conventional structure and a full analysis can be found in Section 2.4.2.
3.4.3
Static Power Dissipation
The static power dissipation (PSTATIC) is the product of the sum of the currents
flowing through the current sources or sinks with the power supply voltages and is
given by:
PSTATIC = (VDD − VSS )[ I D ,M 1 + I D ,M 2 + I D ,M 5 + I D ,M 6 + I D ,MB1 ]
(3.22)
And in terms of IBIAS (K=1 for the LCMFB structure):
PSTATIC = (VDD − VSS )3I BIAS
(3.23)
Class AB operation in the LCMFB OTA produces signal currents much larger
than the bias current applied with the same static power dissipation as that of the
conventional structure (K=1). The advantage of this operation is the capability to
design high slew rate architectures with low static power dissipation.
3.5
3.5.1
Characterization
Gain and Phase Margins
The gain and phase margin are defined in Section 2.5.1. The phase margin is
an indication of the relative position of the high frequency pole fpA,B (Figure 3.2) and
the gain bandwidth. For a fixed GB, an increase in the frequency of fpA,B translates to
an increase in the phase margin. Likewise, a decrease in fpA,B, translates to a decrease
in the phase margin. The addition of transistors MR1,2 results in a factor 2 reduction
40
in the capacitance at nodes A/B (as defined in Section 3.3.2), translating to an
increase in the position of the high frequency pole and an increase in the phase
margin. The position of fpA,B is a function of the resistance generated by transistors
MR1,2 (Figure 3.2) and is defined by equation 3.15. The control voltage VR provides
programmable resistance values for transistors MR1,2 and therefore allows
programmable control of the phase margin. Both the phase margin (via fpA,B) and the
open loop gain (Equation 3.12) are a function of the triode resistance generated by
MR1,2, RMR1,2 (Equation 3.5). As mentioned in Section 2.5.1, a decrease in phase
margin increases slew rate at the cost of decreased stability. The resistance RMR1,2
can, therefore, be used to trade off slew rate and gain bandwidth enhancement with
phase margin.
3.5.2
Input Offset Voltage
The definition of the offset voltage for the conventional OTA is equivalent to
the LCMFB structure and is presented in Section 2.5.2.
3.5.3
Total Harmonic Distortion
The definition of the THD for the conventional OTA is equivalent to the
LCMFB structure and is presented in Section 2.5.3.
3.5.4
Noise
3.5.4.1 MOSFET Noise Models
MOSFET noise models are presented in Section 2.5.4.1 and are equivalent to
models used to perform noise analysis for the LCMFB OTA.
41
3.5.4.2 Cascode Stage Noise
Section 2.5.4.2 defines the negligible contribution of noise sources due to
cascoding transistors. Cascode noise sources will therefore be excluded in the
following analysis.
3.5.4.3 Noise Analysis
Figure 3.8 shows the LCMFB OTA structure with MOSFET noise sources.
Vdd
2
in,M5
M5
M3
in,M3
2
A
Vi(-)
C
in,MR1
in,MR2
MR1
MR2
2
2
2
in,M6
M6
M4
2
in,M4
B
Vcasp
2
in,M10
M10
M2
M1
2
in,M1
VR
2
in,M2
Vi(+)
Vout
Ibias
Vcasn
2
in,M7
M7
M9
2
in,M9
M8
2
in,M8
Vss
Figure 3.8 LCMFB OTA with MOSFET Noise Sources.
Assuming matching (M1=M2, M3=M4=M5=M6, M7=M8, MR1=MR2), neglecting
the noise introduced by cascoding transistors M9, M10, and neglecting common
mode noise introduced by the biasing transistors, the input referred noise can be
derived (in terms of in2) as follows.
42
ini2 ,LCMFBOTA = 2[in2,M 1 + in2,M 3 + in2,MR1 +
1
(in2,M 5 + in2,M 7 )]
2
( gm5, 6 R A,B )
(3.24)
The noise of the LCMFB OTA is a function of the transconductance of M5,6, and the
resistance RA,B (Equation 3.13). RA,B is dependent on RMR indicating that an increase
in RMR results in a decrease in noise contributed from the shell transistors. The
addition of transistors MR1,2 results in the addition of two sources of noise for the
LCMFB configuration (2*i2n,MR1) which contribute negligible additional noise and
decrease the noise contribution of the shell transistors.
3.6
3.6.1
Fully Differential Implementation
Structure
A fully differential implementation of the OTA with local common mode
feedback and a common mode feedback network is shown in Figure 3.9. The basic
structure of the fully differential LCMFB architecture is similar to that of its single
ended counterpart with the following exceptions. A second shell, formed by
transistors M11-16, provides complementary output current. Implementation of the
second shell is required to provide mirroring of large, non-symmetric, class AB
currents at the positive and negative outputs. A common mode feedback circuit,
formed by transistors M17-30, has been implemented to control the common mode
output voltage. The common mode voltage is controlled via current injection from
the common mode feedback circuit at low impedance nodes D/E.
43
Vdd
M11
iD3
M5
M3
M6
MR1
Vcasp
M12
M4
iR
A
M16
iD4
C
Vdd
B
MR2
Vcasp
M19
M18
M17
M10
M20
Vbiasp
Vi(-)
M1
iD1
M2
VR
Vi(+)
ID2
M21
Vo(+)
Vo(-)
Ibias
ICM
Vcasn
ICM
Vcasn
M27
M7
Vcmref
M22 Vo(+)
M23
M25
M24
M26
Vo(-)
ICM
M9
D
M15
Vcasp
M28
M29
M30
M8
ICM
Vss
E
M13
M14
Vss
Fully Differential OTA With Local Common Mode Feedback
Common Mode Feedback Circuit
Figure 3.9 Fully Differential LCMFB OTA And Common Mode Feedback Circuit.
Advantages of the fully differential structure include: improved voltage swing, less
susceptibility to common mode noise, and even-order nonlinearity cancellation [5].
3.6.2
Common Mode Feedback
Common mode voltage variables (vcm (2.36), vcmref (2.36), vo,cm (2.37)) and the
function of the common mode feedback circuit are defined in Section 2.6.1. The
CMFB circuit for the LCMFB OTA utilizes two, identical, current mirrors, formed by
M27,29 and M28,29, to generate replica correction currents (ICM) which are injected
at low impedance nodes D/E (Figure 3.9). These mirrors are required to provide
correction currents for each complementary shell independently. Active control of
the bias current will not correct the common mode voltage of the LCMFB fully
differential OTA due to the mirroring function of the shell structures. Adjustment of
the bias current would result in complementary voltage changes at nodes A/B,
44
resulting in complementary drain current changes for M5,6 and M11,12. The shell
structure would mirror these complementary changes to the output, resulting in zero,
net voltage change. Replica common mode correction currents ICM are therefore
required to facilitate independent shell common mode correction. Based on this
analysis, and similar to the conventional structure, two common mode voltage
correction scenarios are possible (referencing Figure 3.9) as follows:
1. If vo,cm > vcmref, less current is passed through M29. This decrease in current is
mirrored to M27,28. ID27,28 is fixed by transistors M17,18 respectively. The
excess current id17,18 generated by these transistors is then injected at nodes
D/E (transistors M7,13) and coupled to the output via mirror transistors
M8,14. The resulting increase in iD8,14 pulls current from the output node and
the output voltage is reduced, to attain: vo(+) = vo(-) = vcmref (Equation 2.33).
2. If vo,cm < vcmref, more current is passed through M27. This increase in current
is mirrored to M27,28. ID27,28 is fixed by transistors M17,18 respectively.
The required increase in current is then pulled from nodes D/E (transistors
M7,13) and coupled to the output via mirror transistors M8,14. The resulting
decrease in iD8,14 injects current at the output node and the output voltage is
increased, to attain: vo(+) = vo(-) = vcmref (Equation 2.33).
3.6.3
Stability
Stability of the common mode feedback loop is equally important to that of
the differential loop. The LCMFB OTA CMFB structure has a dominant low
frequency pole (fpIN) at the input (due to CL) and four high frequency poles associated
45
with diode connected transistors M27,28 and the feedback injection transistors M7,13
(nodes D/E, Figure 3.9). The gain and phase margin of the CMFB circuit must be
verified and remain within the parameters outlined in Section 2.5.1.
3.7
Conclusions
A full analysis of the LCMFB OTA structure was presented. The addition of
LCMFB was shown to have several performance enhancing benefits versus the
conventional OTA architecture including Class AB operation which provides
enhancement in slew rate (SR), and gain bandwidth (GB), with equal static power
dissipation. Implementation of LCMFB with MOS transistors MR1,MR2, shown in
Figure 3.2, provides programmable gain (via the control voltage VR), allowing
utilization of the same OTA for multiple applications. Class AB operation
characteristics allow the LCMFB structure to outperform the conventional structure
with unity mirror gain (K=1). MR1,2 provide the ability to trade slew rate and gain
bandwidth enhancement for phase margin. The benefits of the LCMFB structure are
considerable for a negligible increase in area and equal static power dissipation.
Chapter 4 focuses on design and testing of the conventional and LCMFB OTA
structures in both the single ended and fully differential configuration and provides a
detailed performance comparison from theoretical, simulation, and experimental
perspectives.
46
4
4.1
ANALYSIS
Introduction
As a method of verifying performance enhancements achieved with the
addition of local common mode feedback, Chapter 4 will focus on a detailed
comparison of performance characteristics for the single ended (SE) and fully
differential (FD) OTA structures with and without local common mode feedback.
The design and evaluation, via theoretical calculation, simulation, and
experimentation, of the following four structures is presented:
1. Single-Ended Conventional (SE-CONV)
2. Single-Ended With Local Common Mode Feedback (SE-LCMFB)
3. Fully Differential Conventional (FD-CONV)
4. Fully Differential With Local Common Mode Feedback (FD-LCMFB)
Transistor level design of all test structures is presented in detail in Section 4.2.
Block diagrams, shown in Figure 4.1, are used to distinguish architectures and
illustrate simulation and experimental configurations throughout the chapter.
VI(+)
VI(-)
+
_SE-CONV
VI(+)
VO
VI(-)
(a)
VI(+)
VI(-)
_
+
_FD-CONV+
+
_SE-LCMFB
VO
(b)
VO(-) VI(+)
VO(+) VI(-)
(c)
_
+
_FD-LCMFB+
VO(-)
VO(+)
(d)
Figure 4.1 Diagrams: (a) SE-CONV (b) SE-LCMFB (c) FD-CONV (d) FD-LCMFB.
47
4.2
4.2.1
Design
Design Specifications and Parameters
The parameters listed in Table 4.1 were used for theoretical design
calculations.
Table 4.1 Design Specifications and Parameters.
PARAMETER
Technology
Lambda (λ)
Threshold Voltages (VTHN,VTHP)
Transconductance (KPN,KPP)
Power Supply (VDD,VSS)
Bias Current (IBIAS)
Gain Bandwidth (GB)
Load Capacitance (CL)
SPECIFICATION
AMI 0.5µm CMOS
1λ=0.3µm
0.75V, 0.95V
116µA/V2,38µA/V2
±1.65V
500µA
100MHz
3.0pF
The AMI 0.5µm technology was available for fabrication and was used to maintain
consistency for theoretical calculations, simulation results, and experimental data.
Voltage supply and bias current values were selected based on technology
parameters, power usage, and the load capacitance and gain bandwidth requirement.
The gain bandwidth parameter was defined at 100MHz to provide a reasonable speed
requirement for OTA architecture comparison while allowing accurate measurement
capability using available lab equipment. The load capacitance was defined based on
an approximation of a reasonable on-chip OTA load requirement.
48
4.2.2
Single Ended Conventional OTA
4.2.2.1 Theoretical Design
The conventional OTA, shown in Figure 2.1, was designed based on a gain
bandwidth product of 100MHz and a load capacitance of 3.0pF.
Vdd
M5
1:K
K:1
M6
M4
M3
Vcasp
Vi(-)
M1
M2
M10
Vi(+)
Vout
Ibias
MB1
MB2
M7
Vcasn
M9
M8
Vss
Figure 4.2 Conventional One Stage Operational Transconductance Amplifier.
The gain bandwidth of the conventional OTA is defined in Equation (2.13) as:
GB =
Kgm1, 2
2πC L
(4.1)
Rearranging (4.1), with unity mirror gain (K=1), the following equation can be used
to calculate the transconductance gain of the input differential pair.
gm1, 2 = GB 2πC L
49
(4.2)
The transconductance of a MOS transistor can be calculated with the following
expression:
gm = 2 KP
W
ID
L
(4.3)
Using this expression, the width of the NMOS differential input pair (M1,2, Figure
2.1) can be determined based on a fixed bias current and predetermined length by
rearranging Equation (4.3) for the following relation:
W1, 2 =
( gm1, 2 ) 2 L1, 2
(4.4)
2 KPN I D
Utilizing a drain current of ID=IBIAS/2=250µA (for VDS,SAT≈0.25V), a length L1=3λ
(L1,2>LMIN=2λ for improved matching) and recognizing KPN=3KPP, Equations (4.2)
and (4.4) can be used to size all transistors for the conventional OTA. Designed
transistor sizes and corresponding VDS,SAT voltages, based on theoretical calculations
(Appendix A), are listed below in Table 4.2.
Table 4.2 Conventional OTA Theoretical Design Transistor Sizes.
TRANSISTORS
M1=M2=M7=M8
M3=M4=M5=M6
M9=M8/2, (LMIN)
M10=M6/2, (LMIN)
MB1=MB2=2M1
DIMENSIONS (λ)
184/3
551/3
92/2
276/2
368/3
50
VDS,SAT (V)
0.26
0.26
0.30
0.30
0.26
Cascoding output transistors (M9,M10 in Figure 2.1) do not require matching design
and were designed with minimum length for speed. Their widths were reduced by a
factor 2 to reduce area.
4.2.2.2 Final Design
Simulation performance and layout considerations resulted in transistor sizing
for matching and performance resulting in final transistor sizing shown in Table 4.3.
Table 4.3 Conventional OTA Final Design Transistor Sizes.
TRANSISTORS
M1=M2
M3=M4=M5=M6
M7=M8
M9
M10
MB1=MB2
DIMENSIONS (λ)
200/3
500/3
250/3
150/2
300/2
500/3
VDS,SAT (V)
0.25
0.28
0.23
0.24
0.30
0.23
Final designed transistor sizes, listed in Table 4.3, are the result of extensive
simulation and are adjusted from theoretical design values in Table 4.2 to provide
increased performance and practical layout topologies with transistor matching via
common-centroid and interdigitation.
4.2.3
Single Ended LCMFB OTA
The SE-LCMFB OTA shown in Figure 1.4 was designed for comparison with
the conventional structure shown in Figure 2.1. For an equivalent comparison, the
SE-LCMFB structure was designed with core transistor sizes identical to those of the
conventional OTA listed in Table 4.3. The core of the SE-LCMFB structure is
51
therefore identical to the conventional structure and the only design required is the
sizing of triode resistance transistors MR1, MR2. As presented in Section 3.5.1, the
Vdd
M5
C
M3
A
Vi(-)
MR1
M6
M4
B
MR2
M1
VR
Vcasp
M2
M10
Vi(+)
Vout
Ibias
MB1
MB2
M7
Vcasn
M9
M8
Vss
Figure 4.3 Single Ended OTA with Local Common Mode Feedback.
resistance formed by MR1,2 (RMR1,2) can be used to trade slew rate and gain
bandwidth enhancement with phase margin for the class AB SE-LCMFB OTA. The
high frequency pole at nodes A/B (Equation 3.15), maximum output current
(Equation 3.19), and open loop gain (Equation 3.12), are all functions of RMR1,2.
RMR1,2 is programmable, is determined by the control voltage VR (Figure 1.4), and is
given by Equation (3.5) as:
RMR1, 2 =
1
β MR1, 2 (VC − VR − VTH P )
52
(4.5)
where VR is the control voltage applied at the gate of MR1,2, VC is the constant
voltage at node C, and βMR1,2=KPP(WMR/LMR). For design of MR1,2, a range of
∆RMR1,2 can be determined based on a desired range of phase margin ∆PM.
Simplifying (Equation 3.15) for the position of the high frequency pole (phase
margin) as a function of the resistance RMR (assuming ro1≈ro2≈ro3≈ro4) the following
expression is obtained:
f pA,B =
2 RMR1, 2 + ro1, 2,3.4
2πRMR1, 2 ro1, 2,3, 4C gs 5,6
≈
1
(4.6)
2πRMR1, 2C gs 5, 6
This relationship indicates a decrease in fpA,B and consequently, a decrease in phase
margin, as RMR1,2 increases. A decrease in RMR1,2 would then lead to an increase in
fpA,B and an increase in the phase margin.
The design method for sizing MR1,2 involves replacing transistors MR1,2
with resistors R1,2 as shown in Figure 4.4.
Vdd
M5
C
M3
K:1
M4
M6
B
A
R1
Vi(-)
1:K
Vcasp
R2
M1
M2
M10
Vi(+)
Vout
Ibias
MB1
MB2
M7
Vcasn
M9
M8
Vss
Figure 4.4 SE-LCMFB OTA MR1,2 Design Schematic.
53
A parametric step of resistors R1,2 in simulation will then determine a desired range
of resistance (∆RMR1,2) corresponding to a desired range of phase margin
(∆PM≈40°<PM<80°). A parametric simulation of the structure shown in Figure 4.4,
with core transistor sizes listed in Table 4.3, resulted in a resistance range of
(RMR,MIN=200Ω>RMR1,2<RMR,MAX=1000Ω) corresponding to a range of phase margin
(40°<PM<80°).
WMR and LMR can then be determined analytically by rearranging Equation
(4.5) for the following:
WMR1, 2
1
=
LMR1, 2 RMR1, 2 KPP (VC − VR − VTH P )
(4.7)
The voltage at node C (VC) can be calculated, leaving the control voltage range
∆VR=VRMAX-VRMIN as the unknown variables. Simultaneous functions of Equation
(4.7) can then be solved for WMR1,2/LMR1,2 based on a voltage range ∆VR that
corresponds to the desired resistance range ∆RMR1,2 as shown in Appendix A. Results
are shown below in Table 4.4.
Table 4.4 SE-LCMFB MR1,2 Design Transistor Sizes.
PARAMETER
Phase Margin (°)
RMR1,2 (Ω)
VR (V)
TRANSISTORS
MR1,MR2
MIN VALUE MAX VALUE
40
80
1000
200
-0.75
-1.75
WMR1,2 (λ)/LMR1,2 (λ)
220/2
54
4.2.4
Fully Differential Conventional OTA
The fully differential dual conventional OTA (FD-CONV) is shown in Figure
4.5 and was designed based on the core transistor sizes listed in Table 4.3.
Vdd
M11
M5
M6
M3
Vdd
B
A
M16
M12
M4
Vcasp
Vcasp
M10
M19
M18
M17
M20
Vbiasp
Vi(-)
M1
M2
Vi(+)
M21
Vo(+)
Ibias
Vo(-)
ICM
ICM
MB1
MB2
Vcasn
M15
Vcasn
Vcmref
M22 Vo(+)
M23
M25
M24
M26
Vo(-)
ICM
M9
D
M27
M7
Vcasp
M8
ICM
M28
M29
M30
Vss
E
M13
M14
Vss
Common Mode Feedback Circuit
Fully Differential Conventional OTA
Figure 4.5 Fully Differential, Dual Shell, Conventional OTA.
The fully differential architecture contains new shell transistors M12-16 and common
mode feedback transistors M17-30. Shell transistors M12-16 were designed to
match those of the interior shell (K=1) and are listed in Table 4.5.
Table 4.5 Fully Differential Conventional OTA Shell Transistor Sizes.
TRANSISTORS
M11=M12
M13=M14
M15
M16
DIMENSIONS (λ)
500/3
250/3
150/2
300/2
Common mode feedback circuit transistors (M17-30) were designed based on
matching concerns and core transistor sizes and are listed in Table 4.6.
55
Table 4.6 Fully Differential Conventional OTA CMFB Transistor Sizes.
TRANSISTORS
M17=M18=M19=M20
M21=M22
M23=M24=M25=M26
M27=M28=M29=M30
4.2.5
DIMENSIONS (λ)
500/3
300/3
500/3
250/3
Fully Differential LCMFB OTA
The FD-LCMFB OTA shown in Figure 4.6 was designed for comparison with
the conventional fully differential structure shown in Figure 4.5.
Vdd
M11
M3
A
M16
C
M5
M6
MR1
Vcasp
M12
M4
Vdd
B
MR2
Vcasp
M10
M19
M18
M17
M20
Vbiasp
Vi(-)
M1
M2
VR
Vi(+)
M21
Vo(+)
Ibias
Vo(-)
ICM
ICM
MB1
MB2
Vcasn
M15
Vcasn
Vcmref
M22 Vo(+)
M23
M25
M24
M26
Vo(-)
ICM
M9
D
M27
M7
Vcasp
M8
ICM
M28
M29
M30
Vss
E
M13
M14
Vss
Fully Differential OTA With Local Common Mode Feedback
Common Mode Feedback Circuit
Figure 4.6 Fully Differential OTA with Local Common Mode Feedback.
For an equivalent comparison, the FD-LCMFB structure was designed with all
transistor sizes (M1-30) identical to those of the fully differential conventional OTA
as listed in Table 4.3, Table 4.5, and Table 4.6. The design of the FD-LCMFB
structure is therefore identical to the conventional structure and, similar to its single
56
ended counterpart, the only design required is the sizing of triode resistance
transistors MR1, MR2. Addition of the second shell (M11-16) for the FD-LCMFB
OTA doubles the capacitance at nodes A/B (Figure 4.6) due to the addition of gatesource capacitances associated with M11,12, respectively. This increase in
capacitance results in a decrease in the position of the high frequency poles at A/B
and reduces the phase margin. This reduction necessitates redesign of MR1,2 for the
FD-LCMFB OTA following the procedure outlined in Section 4.2.3. Parametric
simulation of the FD-LCMFB OTA, with a range of phase margin equal to that of the
SE-LCMFB OTA (∆PM≈40°<PM<80°), indicated a reduced resistance range
(∆RMR1,2) requirement. WMR1,2/LMR1,2 were selected identical to those of the SELCMFB OTA listed in Table 4.4 (WMR1,2/LMR1,2=220/2) and the resistance range was
adjusted with a reduced control voltage range (∆VR) as listed below in Table 4.7.
Table 4.7 FD-LCMFB MR1,2 Design Transistor Sizes.
PARAMETER
Phase Margin (°)
RMR1,2 (Ω)
VR (V)
4.3
MIN VALUE
40
200
-1.75
MAX VALUE
80
650
-0.90
Calculation-Simulation-Experimentation
Theoretical values (calculations, Appendix B), simulation results, and
experimental results, for the single ended (SE-CONV, SE-LCMFB) and fully
differential (FD-CONV, FD-LCMFB) architectures, with and without local common
mode feedback are presented in the following sections. Results for all three
evaluation methods (theory, simulation, and experimentation) for all four
57
architectures will be presented in tabular form in each section to provide a quick
reference of results consistency. Tabular data will also emphasize enhancement
factors as a result of the addition of local common mode feedback.
4.3.1
Parameters
The parameters listed in Table 4.8 were used for test and analysis.
Table 4.8 Simulation Parameters.
PARAMETER
Technology
Power Supply (VDD,VSS)
Bias Current (IBIAS)
Load Capacitance (CL)
VCMREF
VR (SE-LCMFB)
VR (FD-LCMFB)
SPECIFICATION
AMI 0.5µm CMOS
±1.65V
500µA
55pF
0V
-0.75V
-0.90V
The parameters listed above were used consistently for theoretical calculation,
simulation, and experimental measurement configurations for all four devices under
test (SE-CONV, SE-LCMFB, FD-CONV, and FD-LCMFB).
The large load capacitance of 55pF was calculated to match the experimental
test configuration. The load capacitance was determined via several iterations of
experimental measurement and simulation for the single ended conventional OTA.
The experimental load capacitance (CL) can be divided into five dominant
capacitances in parallel: CCHIP (off chip), CBOARD (prototype board), CCABLE (output
coax test cable), CCONN (output coax test cable connectors), and CINST (test instrument
input). The experimental load capacitance is then the summation of these parallel
58
capacitance values. Three experimental and simulation gain bandwidth measurement
test iterations were performed on the SE-CONV architecture in which the
experimental test configuration was identical with the exception of the length of the
output coax test cable. Variation of the cable length (∆CCABLE) provided variation of
the load capacitance (∆CL). This variation, in conjunction with the theoretical GB
equation for the SE-CONV architecture (Equation 2.13), provided a correlation
between simulation and experimental GB values. The net result indicated a load
capacitance of CL=55pF for a six inch coax test cable.
4.3.2
Results and Analysis
4.3.2.1 Open Loop Gain
The open loop gain was calculated and verified via simulation to provide a
reference for simulation validity and to indicate the gain enhancement provided by
the addition of local common mode feedback. Circuit simulation test configurations
for both the (a) single ended and (b) fully differential architectures can be seen in
Figure 4.7.
vIN
CF
+
_
VOUT-SE
55p
10u
CL
CF
RF
10u
100M
vIN
ED
_
+
_
A=0.5
+
55p
VOVO+
55p
RF
CF
RF
10u
100M
CL
CL
100M
(a)
(b)
Figure 4.7 Open-Loop Simulation Circuit Configurations: (a) SE (b) FD.
59
Open loop gain simulation results for the single ended and fully differential
architectures can be seen in Table 4.9 below.
Table 4.9 Open Loop Gain Results.
THEORY
SIMULATION
Open Loop Gain (dB)
SE CONV SE LCMFB FD CONV
66
76
72
60
70
69
FD LCMFB
76
74
Results indicate modest improvements in the open loop gain as the result of the
addition of local common mode feedback.
4.3.2.2 Gain Bandwidth
Gain bandwidth circuit test configurations for simulation and experimental
measurements for both the (a) single ended and (b) fully differential architectures can
be seen in Figure 4.8.
CF
10p
RF
CI
vIN
RI
.01u
+
_
VOUT-SE
50
50
55p
CL
1K
vIN
1K
.01u
Input Network
10p
470K
RI
470K
_
+
_
+
470K
CI
10p
CF
10p
(b)
Figure 4.8 Gain-Bandwidth Test Circuit Configurations: (a) SE (b) FD.
60
CL
VOVO+
55p
RF
470K
(a)
55p
CL
Gain bandwidth experimental measurements were made with the spectrum analyzer
(HP 4195A). The FD test configuration, shown in Figure 4.8(b), implements an
inverting, fully differential, voltage follower, via resistors RI/RF and capacitors CI/CF.
CI and CF provide compensation for the introduction of the feedback (RF) and input
resistors (RI) loading the OTA structures. The input network (also shown in Figure
4.8(b)) formed by two 10nF capacitors, two 50Ω, and two 1KΩ resistors is used
consistently throughout fully differential testing configurations and was realized to
create complementary input signals by forcing floating function generator and
spectrum analyzer inputs. Fifty ohm resistors provide a ground reference at the input.
The 10nF capacitors and 1KΩ resistors form a (low corner frequency) high pass filter
(f3dB=16KHz) at each input, blocking DC and maintaining phase consistency for the
floating input signals.
GB results for theoretical calculations, simulation, and experimental
measurements can be seen below in Table 4.10. Enhancement ratios provide quick
reference for the improvements in bandwidth as a result of the addition of local
common mode feedback for both single ended and fully differential structures.
Table 4.10 Gain Bandwidth Results.
THEORY
ENHANCEMENT
SIMULATION
ENHANCEMENT
EXPERIMENTAL
ENHANCEMENT
GAIN BANDWIDTH (MHz)
SE CONV SE LCMFB FD CONV FD LCMFB
5.7
18.9
5.7
10.6
3.32
1.86
5.9
25
5.6
10.6
4.24
1.89
5.7
19.5
5.1
9.1
3.42
1.78
61
Results indicate a factor greater than 3 increase in GB for the single ended OTA
structures and a factor of nearly 2 increase for the fully differential structures.
4.3.2.3 Maximum Output Current
Maximum output current circuit test configurations for simulation and
experimental measurements for both the (a) single ended and (b) fully differential
architectures can be seen in Figure 4.9.
vIN
+
_
VOUT-SE
RL
_
+
_
vIN+
100
+
vIN-
(a)
RL
100
VOVO+
RL
100
(b)
Figure 4.9 Maximum Output Current Test Circuit Configurations: (a) SE (b) FD.
Maximum output current results for theoretical calculations, simulation, and
experimental measurements can be seen below in Table 4.11.
Table 4.11 Maximum Output Current Results.
MAXIMUM OUTPUT CURRENT (mA)
SE CONV SE LCMFB FD CONV FD LCMFB
0.5
1.95
0.5
1.95
THEORY
ENHANCEMENT
3.9
3.9
0.48
2.34
0.48
2.08
SIMULATION
ENHANCEMENT
4.88
4.33
0.47
1.98
0.48
1.84
EXPERIMENTAL
ENHANCEMENT
4.21
3.83
62
Enhancement
ent ratios provide quick reference for the improvements in output current
as a result of the addition of local common mode feedback for both single ended and
fully differential structures. Results indicate a factor of 4 increase in the maximum
output current for both the single ended and fully differential architectures as a result
of the addition of local common mode feedback. Maximum output currents larger
than four times the bias current indicate class AB characteristics for the structures
with LCMFB.
4.3.2.4 Slew Rate
Slew rate circuit test configurations for simulation and experimental
measurements for both the (a) single ended and (b) fully differential architectures can
be seen in Figure 4.10.
CF
10p
RF
CI
vIN
RI
.01u
+
_
VOUT-SE
50
50
55p
CL
1K
vIN
1K
.01u
10p
470K
RI
470K
_
+
_
+
470K
CI
10p
470K
10p
(b)
Figure 4.10 Slew Rate Test Circuit Configurations: (a) SE (b) FD.
Slew rate results for theoretical calculations, simulation, and experimental
measurements can be seen below in Table 4.12.
63
CL
VOVO+
55p
RF
CF
(a)
55p
CL
Table 4.12 Slew Rate Results.
THEORY
ENHANCEMENT
SIMULATION
ENHANCEMENT
EXPERIMENTAL
ENHANCEMENT
SLEW RATE (V/µs)
SE CONV SE LCMFB FD CONV FD LCMFB
9.1
35.3
18.2
70.7
3.88
3.88
8.6
36.5
15.1
77.1
4.24
5.11
8.2
34.6
17.5
67
4.22
3.83
Enhancement ratios indicate a factor 4 increase in the slew rate (corresponding to a
factor of 4 increase in maximum output current in Section 4.3.2.3) for both the single
ended and fully differential architectures as a result of the addition of local common
mode feedback. Class AB operation in the LCMFB configurations provides large
dynamic currents for increased slew rate capability.
4.3.2.5 Static Power Dissipation
Static power results for theoretical calculations, simulation, and experimental
measurements can be seen below in Table 4.13.
Table 4.13 Static Power Dissipation Results.
STATIC POWER DISSIPATION (mW)
SE CONV SE LCMFB FD CONV FD LCMFB
4.95
4.95
9.90
9.90
THEORY
ENHANCEMENT
1.00
1.00
4.83
4.84
9.42
9.42
SIMULATION
ENHANCEMENT
0.99
1.00
4.91
4.98
9.91
9.92
EXPERIMENTAL
ENHANCEMENT
0.98
0.99
64
Results indicate equal static power dissipation for single ended and fully differential
architectures with and without local common mode feedback.
4.3.2.6 Gain and Phase Margins
Gain and phase margin simulation results can be seen below in Table 4.14.
Table 4.14 Gain and Phase Margin Simulation Results.
GAIN MARGIN (dB) AND PHASE MARGIN (°)
SE CONV SE LCMFB FD CONV FD LCMFB
25.2
15.3
20.6
15.6
GM (dB)
PM (°)
88.3
66.1
84
78.5
Simulations indicate the effect of the application of local common mode feedback via
the reduction in gain and phase margin for both the single ended and fully differential
architectures. LCMFB can be used to trade off slew rate and gain bandwidth
enhancement with gain and phase margin (stability).
4.3.2.7 Input Offset Voltage
Systematic offset voltage simulation results can be seen below in Table 4.15.
Table 4.15 Offset Voltage Simulation Results.
VOS
OFFSET VOLTAGE (V)
SE CONV SE LCMFB FD CONV
15.9m
3.2m
1.9p
FD LCMFB
8.3p
Relatively large offset voltages for the single ended architectures can be attributed to
the non-symmetric structure of the shell structures (Figures 2.1, 3.1). This nonsymmetric shell structure provides increased speed at the cost of increased offset.
65
Results indicate a reduction in the offset voltage with the addition of LCMFB for the
single ended structures and a negligible increase for the fully differential
architectures.
4.3.2.8 Harmonic Distortion
Harmonic distortion simulation results are shown in Table 4.16 below.
Table 4.16 Harmonic Distortion Simulation Results.
Nth Order HD (dB) AND THD (%)
SINGLE ENDED STRUCTURES
VIN
(1KHz)
200mV
400mV
600mV
800mV
2nd
-87.09
-78.27
-67.21
-61.85
VIN
(1KHz)
200mV
400mV
600mV
800mV
2nd
-97.73
-97.40
-95.63
-96.92
SE-CONV
SE-LCMFB
4th
3rd
4th
THD
2nd
3rd
-104.01 -105.28 0.0046 -80.89
-95.49 -105.13
-83.56
-96.25 0.0140 -72.84
-84.07
-94.05
-68.99
-78.03 0.0583 -62.39
-68.23
-72.96
-59.87
-80.10 0.1314 -49.21
-52.85
-56.18
FULLY DIFFERENTIAL STRUCTURES
FD-CONV
3rd
4th
-104.99 -106.83
-125.55 -105.84
-90.37 -102.84
-77.22 -105.05
THD
0.0018
0.0017
0.0037
0.0148
2nd
-97.71
-97.34
-95.52
-97.00
FD-LCMFB
3rd
4th
-104.94 -106.84
-123.79 -105.87
-92.36 -102.85
-80.74 -104.74
THD
0.0092
0.0238
0.0891
0.4556
THD
0.0018
0.0017
0.0032
0.099
Harmonic distortion simulations for all four structures were configured with a 1KHz
sinusoidal input signal with amplitude values of 200, 400, 600, and 800mV. Table
4.16 provides normalized harmonic distortion data in dB for the first three harmonics
at all four applied amplitudes and corresponding percentage THD values. Results
66
indicate an increase in distortion with the addition of LCMFB for both single ended
and fully differential
ferential architectures.
4.3.2.9 Noise
Total input noise spectral density
density plots for all four OTA architectures are
shown in Figure 4.11((a) SE-CONV, SE-LCMFB (b) FD-CONV, FD-LCMFB).
SINGLE ENDED OTA TOTAL INPUT NOISE
65
60
55
Total Input Noise (uV)
50
45
40
35
SE-CONV
30
25
20
15
SE-LCMFB
10
5
0
1
10
100
1k
10k
Frequency (Hz)
(a)
100k
1M
10M
100M
FULLY DIFFERENTIAL OTA TOTAL INPUT NOISE
60
55
Total Input Noise (uV)
50
45
40
35
30
FD-CONV
25
20
15
FD-LCMFB
10
5
0
1
10
100
1k
10k
Frequency (Hz)
(b)
100k
1M
10M
Figure 4.11 OTA Total Input Noise Simulation Plots (a) SE (b) FD.
67
100M
Input noisee results plots show a decrease in noise as a result of the addition of local
common mode feedback. Table 4.17 below lists total noise extracted from spectral
density plots (Figure 4.11) at 10 MHz for all four OTA structures.
Table 4.17 Total Input Noise at 10MHz.
NOISE (µV)
INPUT NOISE AT 10MHz
SE-CONV SE-LCMFB FD-CONV
20
14
18
FD-LCMFB
15
Results indicate a reduction in noise as a result of the addition of LCMFB. This
reduction is the result of increased gain as outlined in Section 3.5.4.3.
4.3.2.10 Common Mode Feedback Characterization
Common mode feedback circuits for the fully differential structures were
characterized via an AC open loop simulation to verify their open loop gain,
bandwidth, gain margin, and phase margin. The common mode feedback circuit test
configuration is shown below in Figure 4.12.
RF
500K
RI
500K
RI
_
+
_
CMIN
500K
RF
+
CL
VOVO+
CL
RT100u
CT
CMINVCM,REF
100M
RT
100M
100u
CMFB
CT
CMIN+
CMOUT
VCM,REF
500K
Figure 4.12 CMFB Open Loop Characterization Simulation Circuit Configuration.
68
Simulation results for the CMFB circuits for both fully differential architectures are
shown below in Table 4.18.
Table 4.18 Common Mode Feedback Circuit Simulation Results.
COMMON MODE FEEDBACK CIRCUIT CHARACTERIZATION
AOL(dB)
GB(MHz)
GM(dB)
PM(º)
54
3.9
28.6
88.7
FD-CONV
54
FD-LCMFB
3.9
28.6
88.7
4.3.2.11 Silicon Area
Layout figures and dimensions for the single ended and fully differential OTA
structures with and without LCMFB are shown in Figure 4.13 below.
SE-CONV
SE-LCMFB
Dimensions: 216µm*55µm=11880µm2
Dimensions: 253µm*57µm=14421µm2
(a)
(b)
FD-CONV
FD-LCMFB
Dimensions: 588µm*55µm=32340µm2
Dimensions: 646µm*57µm=36822µm2
(c)
(d)
Figure 4.13 Layout (a) SE-CONV (b) SE-LCMFB (c) FD-CONV (d) FD-LCMFB.
Results indicate only a 15-20% increase in silicon area as a result of the addition of
local common mode feedback transistors.
69
4.4
Conclusions
Table 4.19 below provides a summary of characteristic improvement factors
for the single ended and fully differential architectures with local common mode
feedback versus their conventional counterparts. The data represents a compilation of
the benefits and costs of the addition of LCMFB as presented in the previous sections.
Table 4.19 Analysis Summary Results.
ANALYSIS SUMMARY
SINGLE ENDED
DIFFERENTIAL
PARAMETER
FACTOR
IMPROVEMENT
FACTOR
IMPROVEMENT
GB
4
2
IOUTMAX
4
4
SR
4
4
PSTATIC
1
1
PARAMETER
EFFECT OF LCMFB
EFFECT OF LCMFB
GM/PM
PROGRAMMABLE
PROGRAMMABLE
VOS
DECREASE
DECREASE
THD
INCREASE
INCREASE
NOISE
DECREASE
DECREASE
AREA
15-20% INCREASE
15-20% INCREASE
Table 4.19 illustrates several performance enhancing benefits of LCMFB versus the
conventional OTA architecture including class AB (IOUTMAX) operation which
70
provides enhancement in slew rate, and gain bandwidth, with equal static power
dissipation and reduced noise. Implementation of LCMFB with MOS transistors
MR1,MR2, (Figure 1.4, Figure 4.6) provides programmable gain (via the control
voltage VR), allowing utilization of the same OTA for multiple applications. MR1,2
provide the ability to trade slew rate and gain bandwidth enhancement for phase
margin. The benefits of the LCMFB structure are considerable for a negligible
increase in harmonic distortion and silicon area.
71
5
5.1
APPLICATIONS
Fully Differential Charge Scaling Digital-Analog Converter
As a test application requiring high slew rate performance, an 8-bit, fully
differential, charge-scaling, digital-to-analog converter was implemented and
simulated for both the FD-CONV (Figure 2.10) and FD-LCMFB (Figure 3.9)
architectures. The designed OTA structures function as the core amplifier for the
charge scaling architecture shown in Figure 5.1 below.
VREF+
RESET
VREFb0
CLK
CU
CU
VREF+
CU
CU
CLK
b0
b1
CLK
bN-1
CLK
(2N)CU
(2N-1)
(2N)CU
2
(2N)CU
(2N-1)
(2N)CU
2
CLK
b1
CLK
bN-1
VREF-
CF=(2N)CU
+
_
_
VO-
+
VO+
CF=(2N)CU
RESET
Figure 5.1 Fully Differential Charge Scaling Analog-Digital Converter.
The fully differential, charge-scaling structure utilizes dual reference voltages
(VREF+, VREF-) at each input for a full scale, differential, reference voltage equal to
VREF=2(VREF+-VREF-). Based on the charge/voltage relation for a capacitor (C=Q/V)
the charge on the scaling capacitors, in terms of the unit capacitance (CU), the digital
input code (b0-b7), and the full scale reference voltage (VREF), can be defined as:

2N C
2N C
2 N CU 
Q = VREF b0CU + b1 N −1U + b2 N −2U + ... + bN −1
2
2
2 

72
(5.1)
The output voltages, in terms of VREF are then given by:
b 
b
b
b
VO+ = −VO− = −VREF  N0 + N1−1 + N2−2 + ... + N −1 
2
2
2 
2
(5.2)
The differential output voltage is given by VO=VO+-VO-, and the maximum output
voltage of the converter, with respect to VREF, is given by:
VOMAX = VREF −
VREF
2N
(5.3)
The DAC shown in Figure 5.1 was implemented for a comparative, application
specific, reference to the operation characteristics of both fully differential amplifiers.
5.1.1
Simulation Specifications and Parameters
Simulation parameters and design specifications for the implemented charge
scaling DAC (Figure 5.1) are shown below in Table 5.1.
Table 5.1 Fully Differential Charge Scaling DAC Design Parameters.
PARAMETER
Technology
Power Supply (VDD,VSS)
Bias Current (IBIAS)
Number of Bits (N)
Reference Voltage (VREF=2(VREF+-VREF-)
Unit Capacitance (CU)
Feedback Capacitance (CF=256*CU )
Resolution (R=VREF/2N)
VOMAX (2(VREF+-VREF-)-Resolution)
VR (FD-LCMFB)
73
SPECIFICATION
AMI 0.5µm CMOS
±1.65V
500µA
8
2.0
0.25pF
64pF
7.8125mV
1.992V
-0.9V
5.1.2
Results and Analysis
The charge scaling DAC structure in Figure 5.1 was simulated with both fully
differential OTA structures (FD-CONV (Section 2.6), FD-LCMFB (Section 3.6))
with identical parameters as defined in Table 5.1. A full digital scale transient
simulation with a clock frequency (fCLK) of 1MHz provided data for analysis of
standard DAC specifications including: differential nonlinearity (DNL), integral
nonlinearity (INL), offset, gain error, and settling time. Figure 5.2 shows (a) DNL
and (b) INL plots for the FD-CONV-DAC.
DNL vs. Input Code
1
0.8
DNLMAX(LSBs)=0.5104
0.6
DNL(LSBs)
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
50
100
150
Digital Input Code(Decimal)
(a)
200
250
200
250
INL vs. Input Code
1
0.8
INLMAX(LSBs)=0.71283
0.6
INL(LSBs)
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
50
100
150
Digital Input Code(Decimal)
(b)
Figure 5.2 FD-CONV-DAC Analysis Plots (a) DNL (b) INL.
74
Annotated DNL and INL values aree listed on the corresponding plots and indicate
indicate the
maximum error measured in simulation. Figure 5.3 shows (a) DNL and (b) INL plots
for the FD-LCMFB-DAC.
DNL vs. Input Code
1
0.8
DNLMAX(LSBs)=0.4624
0.6
DNL(LSBs)
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
50
100
150
Digital Input Code(Decimal)
(a)
200
250
200
250
INL vs. Input Code
1
0.8
INLMAX(LSBs)=0.33578
0.6
INL(LSBs)
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
50
100
150
Digital Input Code(Decimal)
(b)
Figure 5.3 FD-LCMFB-DAC Analysis Plots (a) DNL (b) INL.
Table 5.2 summarizes simulated DAC specifications for both the conventional
and local common mode feedback configurations. Listed characteristics were
determined via a DAC Matlab script.
75
Table 5.2 Simulated DAC Specifications Summary.
PARAMETER
FD-CONV-DAC
FD-LCMFB-DAC
DNL(LSB)
0.5104
0.4624
INL(LSB)
0.7128
0.3358
Offset(V)
0.24m
1.3m
Gain Error(V/LSB)
14.7u
2.16u
Settling Time(sec)
236n
100n
PSTATIC(W)
9.4m
9.4m
Specifications recorded in Table 5.2 identify improvements in all aspects of
the performance of the differential DAC (with the exception of offset voltage), with
equal static power dissipation, due to the addition of local common mode feedback.
Settling time values (Table 5.2) were measured at 99.9% (10 bit resolution) of a full
scale (VREF=2V) input pulse shown in Figure 5.4.
FD-DAC Settling Response
2.0
FD-LCMFB-DAC
Voltage (V) (Vo+,Vo-)
1.5
1.0
FD-CONV-DAC
0.5
0.0
0.5
1.0
1.5
450
500
550
600
650
700
750
800
TIME (ns)
Figure 5.4 Transient, Full Scale Settling Time Response.
76
The LCMFB configuration demonstrates more than a factor of 2 improvement
in settling time. The addition of local common mode feedback to the fully
differential, charge-scaling, digital-to-analog converter, results in increased accuracy
and speed with equal static power dissipation.
5.2
Proposed Applications
Battery powered systems require high gain bandwidth values, high slew rates,
and at the same time very low static power dissipation. The class AB characteristics
of both the single ended and fully differential OTA structures with local common
mode feedback match these requirements. The programmability of the LCMFB
architecture, in conjunction with its ability to generate large dynamic currents with
low static power dissipation, makes it an ideal choice for analog filtering, data
conversion, and wireless applications.
77
APPENDICES
APPENDIX A
DESIGN CALCULATIONS
SINGLE-ENDED CONVENTIONAL OTA (FIGURE 2.1):
DESIGN AND SIMULATION CALCULATIONS: CMOS 0.5um TECHNOLOGY
Parameters:
−6
KPn := 116⋅ 10
Vthn := 0.75
− 15
−6
KPp := 38⋅ 10
− 10
Coxpr := 4.6⋅ 10
− 10
CGDOn := 1.30⋅ 10
−4
−3
CJn := 9.3⋅ 10
CJp := 1.42⋅ 10
Vthp := 0.95
CGDOp := 1.10⋅ 10
L1 := 3
K := 1
Conventional OP-AMP Design (Hand Calculations):
DESIGN SPECIFICATIONS:
−6
IBIAS := 500⋅ 10
ID :=
IBIAS
2
−4
6
ID = 2.5 × 10
GB := 100⋅ 10
− 12
CLD := 3.0⋅ 10
DESIGN CALCULATIONS:
−3
g m1 := GB⋅ 2⋅ π⋅ CLD
 ( g ) 2⋅ L 
 m1 1
W 1 :=
 2KP ⋅ I 
n D

g m1 = 1.885 × 10
W 1 = 183.779
W 2 := W 1
L2 := L1
W 3 := 3W 2
L3 := L2 W 3 = 551.337
W 4 := W 3
L4 := L3
W 5 := W 4
L5 := L4
W 6 := W 5
L6 := L5
W 2 := W 1
W 2 = 200
W 4 := W 3
W 4 = 500
L2 := L1
L4 := L1
L5 := L1
W 6 := K⋅ W 4
W 6 = 500
L6 := L1
W 7 := 500
L7 := L1
W 8 := W 7
W 7 = 500
L8 := L1
W 9 := 150
L9 := 2
W 10 := 300
W MB1 := 500
LMB1 := 3
W MB2 := W MB1
DESIGNED TRANSISTOR SIZES:
W 1 := 200
L1 := 3
W 3 := 500
L3 := L1
W 5 := K⋅ W 3
W 5 = 500
80
L10 := 2
W MB2 = 500
LMB2 := 3
APPENDIX B
THEORETICAL ANALYSIS CALCULATIONS
THEORY-SIMULATION-EXPERIMENTAL PARAMETERS:
−6
VDD := 1.65 VSS := −VDD
IBIAS := 500⋅ 10
ID :=
IBIAS
2
− 12
CL := 55⋅ 10
K := 1
THEORETICAL ANALYSIS:
OPEN LOOP GAIN (EQ: 2.7):
 W1 
g m1 := 2⋅ KPn ⋅ 

L1

⋅ ID
−3
g m1 = 1.966 × 10
Output Resistance (EQ 2.5):
Channel Length Modulation Parameters Of Output Transistors:
λ8. := 0.08
ro8 :=
λ9. := 0.16
1
4
ro8 = 5 × 10
λ8.⋅ K⋅ ID
ro6 :=
λ6. := 0.09
1
ro9 :=
4
ro6 = 4.444 × 10
λ6.⋅ K⋅ ID
 W9 
g m9 := 2⋅ KPn ⋅ 

L9

 W 10 
 L10 
ROUT :=  g m9⋅ ro9⋅ ro8

(
)
4
ro9 = 2.5 × 10
λ9.⋅ K⋅ ID
ro10 :=
1
4
ro10 = 2.222 × 10
λ10.⋅ K⋅ ID
g m9 = 2.086 × 10
−3
K⋅ ID
−1
1
−3
⋅ K⋅ ID
g m10 := 2⋅ KPp ⋅ 
λ10. := 0.18
g m10 = 1.688 × 10
(
+ g m10⋅ ro10⋅ ro6
)
− 1
A OL_VV:= g m1⋅ ROUT

−1
6
ROUT = 1.017 × 10
3
A OL_VV = 2 × 10
82
AC Analysis:
2
2
Cgs3 :=   ⋅ W 3⋅ L3⋅ Coxpr⋅ ( 0.3)
3
− 13
Cgs3 = 4.14 × 10
 
 W3 
g m3 := 2⋅ KPp ⋅ 
⋅ ID
 L3 
−3
g m3 = 1.78 × 10
High Frequency Pole fA (EQ: 2.10):
fA :=
g m3
8
fA = 3.421 × 10
2⋅ π⋅ Cgs3 ⋅ ( 1 + K)
Dominant Pole fout=f3dB (EQ: 2.12):
f3dB :=
1
3
f3dB = 2.845 × 10
2⋅ π⋅ ROUT⋅ CL
GAIN BANDWIDTH (EQ: 2.13):
GB := K⋅
g m1
6
GB = 5.69 × 10
2⋅ π⋅ CL
MAXIMUM OUTPUT CURRENT (EQ: 2.14):
IOUTMAX := K⋅ IBIAS
−4
IOUTMAX = 5 × 10
SLEW RATE (EQ: 2.15):
 IOUTMAX 
SR := 
CL


−6
⋅ 1⋅ 10
SR = 9.091
STATIC POWER DISSIPATION (EQ: 2.24):
(
)
−3
PSTATIC := VDD − VSS IBIAS⋅ ( 2 + K)
PSTATIC = 4.95 × 10
83
SINGLE-ENDED LCMFB OTA (FIGURE 3.2):
HAND CALCULATIONS: MATCH CONVENTIONAL DESIGN
DESIGNED CORE TRANSISTOR SIZES: MATCH CONVENTIONAL DESIGN
SIMULATION PARAMETERS MATCH CONVENTIONAL PARAMETERS
LCMFB OTA: MR1,2 DESIGN:
Calculate Voltage At Node C (Figure 3.1)
 ( IBIAS⋅ L3)
VC := VDD − 



+ Vthp

KPp ⋅ W 3
VC = 0.419

Parametric Sweep To Determine Range of R Corresponding To: 40>PM>80:
RMRMIN := 200
RMRMAX := 1000
Select Appropriate Control Voltage (VR) Range (based on voltage rails):
VRMIN := −1.75
VRMAX := −0.75
VR Selection Determines RWR=W WR/LWR Based On Triode Resistance (EQ;3.5):
1
RWL1 :=
RMRMIN⋅ KPp ⋅  VC − VRMIN − Vthp


RWL1 = 107.938
1
RWL2 :=
RMRMAX⋅ KPp ⋅  VC − VRMAX − Vthp


RWL2 = 120.15
(
)
(
RWL :=
)
(RWL1 + RWL2)
RWL = 114.044
2
Select W MR/LMR Ratio Based On R WL And LMIN =2λ:
W MR := 220
RMRMIN :=
Body Effected Threshold Voltage: V
thp := 1.05
LMR := 2
1
 W MR 
⋅  V − VRMIN − Vthp
KPp ⋅ 

LMR  C


RMRMAX :=
(
)
RMRMIN = 213.788
1
 W MR 
KPp ⋅ 
 LMR

(
3
)
⋅  VC − VRMAX − Vthp


84
RMRMAX = 2.01 × 10
THEORETICAL ANALYSIS:
OPEN LOOP GAIN (EQ: 3.12):
Differential Input Stage Gain (EQ: 3.9):
 W1 
g m1 := 2⋅ KPn ⋅ 
⋅ ID
 L1 
λ1 := 0.06
1
ro1 :=
RAMIN :=  ro1

( )
−1
−3
g m1 = 1.966 × 10
4
ro1 = 6.667 × 10
λ1⋅ ID
( )
+ ro3
−1
− 1
+ RMRMIN
ro3 := ro6
4
ro3 = 4.444 × 10
−1

RAMAX :=  ro1

( )− 1 + (ro3)− 1 + RMRMAX− 1
RAMIN = 212.088
−1
A COREMIN:= g m1⋅ RAMIN
3
RAMAX = 1.869 × 10
A COREMIN = 0.417
A COREMAX := g m1⋅ RAMAX
A COREMAX = 3.675
Output Shell Gain (EQ: 3.11):
 W5 
g m5 := 2⋅ KPp ⋅ 

L5

⋅ ID
−3
g m5 = 1.78 × 10
Output Resistance (Defined Above) (EQ 2.5, 3.10):
6
ROUT = 1.017 × 10
A SHELL:= g m5⋅ ROUT
3
A SHELL = 1.81 × 10
Open Loop Gain (EQ 3.12):
(
)
A OL_VV_MIN:= A COREMIN⋅ A SHELL
(
A OL_VV_MIN = 754.726
)
A OL_dB_MIN := 20⋅ log A OL_VV_MIN
A OL_dB_MIN = 57.556
(
)
3
A OL_VV_MAX := A COREMAX⋅ A SHELL
(
A OL_VV_MAX = 6.651 × 10
)
A OL_dB_MAX := 20⋅ log A OL_VV_MAX
A OL_dB_MAX = 76.458
85
AC Analysis:
2
2
Cgs5 :=   ⋅ W 5⋅ L5⋅ Coxpr⋅ ( 0.3)
3
 
− 13
Cgs3 = 4.14 × 10
High Frequency Pole fA (EQ: 3.15):
fAMIN :=
1
8
fAMIN = 2.057 × 10
2⋅ π⋅ RAMAX ⋅ Cgs5
1
fAMAX :=
9
fAMAX = 1.813 × 10
2⋅ π⋅ RAMIN⋅ Cgs5
Dominant Pole fout (EQ: 3.17):
f3dB :=
1
3
f3dB = 2.845 × 10
2⋅ π⋅ ROUT⋅ CL
GAIN BANDWIDTH (EQ: 3.18):
GBMIN :=
g m1⋅ g m5⋅ RAMIN
GBMAX :=
6
GBMIN = 2.148 × 10
2π⋅ CL
g m1⋅ g m5⋅ RAMAX
7
GBMAX = 1.893 × 10
2π⋅ CL
MAXIMUM OUTPUT CURRENT (EQ: 3.19):

 W 5   2⋅ ID⋅ L3  IBIAS
IOUTMAX :=
⋅
+
⋅ RMRMAX

2
2
 L5   W 3⋅ KPp 
KPp
2
−3
IOUTMAX = 1.944 × 10
SLEW RATE (EQ: 2.15):
 IOUTMAX 
SR := 

CL

−6
⋅ 1⋅ 10
SR = 35.341
STATIC POWER DISSIPATION (EQ: 2.24):
(
−3
)
PSTATIC := VDD − VSS 3IBIAS
PSTATIC = 4.95 × 10
86
FULLY-DIFFERENTIAL CONVENTIONAL OTA:
HAND CALCULATIONS: MATCH CONVENTIONAL DESIGN
DESIGNED CORE TRANSISTOR SIZES: MATCH CONVENTIONAL DESIGN
SIMULATION PARAMETERS MATCH CONVENTIONAL PARAMETERS
THEORETICAL ANALYSIS:
OPEN LOOP GAIN:
(
)
A OL_VV:= 2 g m1⋅ ROUT
(
3
A OL_VV = 3.999 × 10
)
A OL_dB := 20⋅ log A OL_VV
A OL_dB = 72.04
GAIN BANDWIDTH:
GB := 2K⋅
g m1
7
GB = 1.138 × 10
2π⋅ CL
MAXIMUM OUTPUT CURRENT (EQ: 2.14):
Differential:
(
)
IOUTMAX := K⋅ IBIAS
−4
IOUTMAX = 5 × 10
SLEW RATE (EQ: 2.15):
Differential:
 IOUTMAX 
SR := 2
CL


−6
⋅ 1⋅ 10
SR = 18.182
STATIC POWER DISSIPATION (EQ: 2.24):
(
−3
)
PSTATIC := VDD − VSS ⋅ 2⋅ IBIAS⋅ ( 2 + K)


PSTATIC = 9.9 × 10
87
FULLY-DIFFERENTIAL LCMFB OTA:
HAND CALCULATIONS: MATCH CONVENTIONAL DESIGN
DESIGNED CORE TRANSISTOR SIZES: MATCH CONVENTIONAL DESIGN
SIMULATION PARAMETERS MATCH CONVENTIONAL PARAMETERS
THEORETICAL ANALYSIS:
OPEN LOOP GAIN:
VRMAX := −0.9
RMRMIN :=
Body Effected Threshold Voltage: V
thp := 1.1
VRMIN = −1.75
1
 W MR 
KPp ⋅ 
⋅  V − VRMIN − Vthp

LMR  C


(
)
RMRMIN = 223.788
1
RMRMAX :=
 W MR 
KPp ⋅ 
 LMR
RAMIN :=  ro1

( )
−1
( )
+ ro3

(
3
)
⋅  VC − VRMAX − Vthp


−1
− 1
+ RMRMIN
−1

RAMAX :=  ro1

( )− 1 + (ro3)− 1 + RMRMAX− 1
A COREMIN:= g m1⋅ RAMIN
−1
3
RAMAX = 1.049 × 10
A COREMAX = 2.063
(
)
A OL_VV_MIN:= 2⋅ A COREMIN⋅ A SHELL
A OL_VV_MIN = 1.579 × 10
)
A OL_dB_MIN := 20⋅ log A OL_VV_MIN
A OL_dB_MIN = 63.97
(
)
A OL_VV_MAX := 2⋅ A COREMAX⋅ A SHELL
(
RAMIN = 221.925
A COREMIN = 0.436
A COREMAX := g m1⋅ RAMAX
(
RMRMAX = 1.092 × 10
)
A OL_dB_MAX := 20⋅ log A OL_VV_MAX
A OL_VV_MAX = 7.468 × 1
A OL_dB_MAX = 77.464
88
GAIN BANDWIDTH:
GBMIN :=
g m1⋅ g m5⋅ RAMIN
GBMAX :=
6
GBMIN = 2.247 × 10
2π⋅ CL
g m1⋅ g m5⋅ RAMAX
7
GBMAX = 1.062 × 10
2π⋅ CL
MAXIMUM OUTPUT CURRENT:
2

 W 5   2ID⋅ L3  IBIAS
IOUTMAX := KPp ⋅ 
+
⋅ RMRMAX
−3
 IOUTMAX = 1.944 × 10
2
 L5   W 3⋅ KPp 
SLEW RATE:
 IOUTMAX 
SR := 2

CL

−6
⋅ 1⋅ 10
SR = 70.695
STATIC POWER DISSIPATION:
(
)
−3
PSTATIC := VDD − VSS 6IBIAS
PSTATIC = 9.9 × 10
89
APPENDIX C
MICROGRAPHS
Micrographs of all four OTA structures are shown in figures C.1(SE-CONV),
C.2(SE-LCMFB), C.3(FD-CONV), C.4(FD-LCMFB) below.
Figure C.1 Micrograph of Fabricated SE-CONV Structure (11880µm2).
Figure C.2 Micrograph of Fabricated SE-LCMFB Structure (14421µm2).
Figure C.3 Micrograph of Fabricated FD-CONV Structure (32340µm2).
Figure C.4 Micrograph of Fabricated FD-LCMFB Structure (36822µm2).
91
A Micrograph of the fabricated 0.5um MOSIS test chip is shown in Figure
C.5 below.
Figure C.5 Micrograph of Fabricated 0.5um CMOS Test Chip.
92
APPENDIX D
INTERNET LINKS
MOSIS Spice Transistor Model Files Can Be Found At:
http://www.mosis.com/Technical/Testdata/
Thesis Data, Files, and Reference Information Including:
ƒ
ƒ
ƒ
ƒ
ƒ
Thesis: Document/Presentation Files
Simulation: Schematics/Simulation Command Files
Electronics Letters: Publication File
MWSCAS 2002: Publication\Presentation Files
ISCAS 2002: Publication\Presentation Files
Can Be Found At:
http://www.ece.nmsu.edu/vlsi/Research/Theses/Michael-Holmes/Michael-Holmes.htm
94
REFERENCES
[1]
J. Harrison and N. Weste, “350MHz OpAmp-RC Filter in 0.18um CMOS,”
Electronics Letters, vol. 38 (6), pp. 259-260, March 2002.
[2]
J. Ramirez-Angulo and M. Holmes, “A Simple Technique to Significantly
Enhance Slew Rate and Bandwidth of One-Stage CMOS Operational
Amplifiers,” Proceedings of the 2002 International Symposium on Circuits and
Systems, Phoenix, Arizona, May 2002.
[3]
M. Holmes, J. Ramirez-Angulo, and R.G. Carvajal, “New Architectures of
Class AB CMOS and BICMOS Operational Amplifiers with Local Common
Mode Feedback,” Proceedings of the 2002 Midwest Symposium on Circuits and
Systems, Tulsa, Oklahoma, August 2002.
[4]
R. Baker, H. Li, and D. Boyce, CMOS Circuit Design, Layout, and Simulation,
New York: IEEE Press, 1st ed., 1997, Pages: 617-679.
[5]
D. Johns and K. Martin, Analog Integrated Circuit Design, New York: John
Wiley & Sons, 1st ed., 1997, Pages: 181-204.
[6]
P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and Design of Analog
Integrated Circuits, New York: John Wiley & Sons, 4th ed., 2001, Pages: 748802, 808-856.
[7]
B. Razavi, Design of Analog CMOS Integrated Circuits, New York: McGrawHill, 1st ed., 2001, Pages: 232-233.
95