AD7863 Data Sheet
... the signals on both analog inputs. The part accepts an analog input range of ± 10 V (AD7863-10), ± 2.5 V (AD7863-3) and 0 V–2.5 V (AD7863-2). Overvoltage protection on the analog inputs for the part allows the input voltage to go to ± 17 V, ± 7 V or +7 V respectively, without causing damage. A singl ...
... the signals on both analog inputs. The part accepts an analog input range of ± 10 V (AD7863-10), ± 2.5 V (AD7863-3) and 0 V–2.5 V (AD7863-2). Overvoltage protection on the analog inputs for the part allows the input voltage to go to ± 17 V, ± 7 V or +7 V respectively, without causing damage. A singl ...
CD4046B Phase-Locked Loop (Rev. A)
... Phase comparator II is an edge-controlled digital memory network. It consists of four flip-flop stages, control gating, and a 3-state output circuit comprising p and n drivers having a common output node (see Figure 3). When the p-MOS or n-MOS drivers are on, they pull the output up to VDD or down t ...
... Phase comparator II is an edge-controlled digital memory network. It consists of four flip-flop stages, control gating, and a 3-state output circuit comprising p and n drivers having a common output node (see Figure 3). When the p-MOS or n-MOS drivers are on, they pull the output up to VDD or down t ...
LMV793/LMV794 88 MHz, Low Noise, 1.8V
... 1.8V to 5.5V and can operate from a single supply. The LMV793/LMV794 each feature a rail-to-rail output stage capable of driving a 600Ω load and sourcing as much as 60 mA of current. The LMV793/LMV794 provide optimal performance in low voltage and low noise systems. A CMOS input stage, with typical ...
... 1.8V to 5.5V and can operate from a single supply. The LMV793/LMV794 each feature a rail-to-rail output stage capable of driving a 600Ω load and sourcing as much as 60 mA of current. The LMV793/LMV794 provide optimal performance in low voltage and low noise systems. A CMOS input stage, with typical ...
11 mW Power, 2.3 V to 5.5 V, Complete DDS AD9838
... output frequency accuracy and phase noise are determined by this clock. Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase accumulator. The frequency register to be used can be selected using the FSELECT pin or the FSEL bit. When the FSEL bit is u ...
... output frequency accuracy and phase noise are determined by this clock. Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase accumulator. The frequency register to be used can be selected using the FSELECT pin or the FSEL bit. When the FSEL bit is u ...
AD1974 数据手册DataSheet下载
... nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ADCs include on-board digital antialiasing filters with a 79 dB stopband attenuation and a linear phase response, operating at an oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz modes). Digital outputs are supplied through two serial data ...
... nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ADCs include on-board digital antialiasing filters with a 79 dB stopband attenuation and a linear phase response, operating at an oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz modes). Digital outputs are supplied through two serial data ...
AN-1057 Ten Ways to Bulletproof RS-485
... differential data transmission. RS-485 is unique in allowing multiple nodes to communicate bidirectionally over a single twisted pair. No other standard combines this capability with equivalent noise rejection, data rate, cable length, and general robustness. For these reasons, a variety of applicat ...
... differential data transmission. RS-485 is unique in allowing multiple nodes to communicate bidirectionally over a single twisted pair. No other standard combines this capability with equivalent noise rejection, data rate, cable length, and general robustness. For these reasons, a variety of applicat ...
