AD2S81A/AD2S82A: Variable Resolution, Monolithic Resolver-to-Digital Converters Data Sheet
... The AD2S82A is a monolithic 10-, 12-, 14- or 16-bit tracking resolver-to-digital converter contained in a 44-lead J leaded PLCC package. Two extra functions are provided in the new surface mount package–COMPLEMENT and VCO output. The AD2S81A is a monolithic 12-bit fixed resolution tracking resolver- ...
... The AD2S82A is a monolithic 10-, 12-, 14- or 16-bit tracking resolver-to-digital converter contained in a 44-lead J leaded PLCC package. Two extra functions are provided in the new surface mount package–COMPLEMENT and VCO output. The AD2S81A is a monolithic 12-bit fixed resolution tracking resolver- ...
MAX5876 12-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs General Description
... digital-to-analog converter (DAC). This DAC meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from +3.3V and +1.8V supplies, this dual DAC offers exceptional dynamic performance such as 75dBc ...
... digital-to-analog converter (DAC). This DAC meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from +3.3V and +1.8V supplies, this dual DAC offers exceptional dynamic performance such as 75dBc ...
GENERAL DESCRIPTION FEATURES
... Secondary Power Supply. Supply voltage must be held between 1.3V and 3.7V for proper operation. This pin can be connected to a primary cell, such as a lithium button cell. Additionally, this pin can be connected to a rechargeable cell or a super cap when used in conjunction with the trickle-charge f ...
... Secondary Power Supply. Supply voltage must be held between 1.3V and 3.7V for proper operation. This pin can be connected to a primary cell, such as a lithium button cell. Additionally, this pin can be connected to a rechargeable cell or a super cap when used in conjunction with the trickle-charge f ...
M48T08
... As system power returns and VCC rises above VSO, the battery is disconnected and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus trec (min). E1 should be kept high or E2 low as VCC rises past VPFD (min) to prevent inadvertent WRITE cycles pr ...
... As system power returns and VCC rises above VSO, the battery is disconnected and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus trec (min). E1 should be kept high or E2 low as VCC rises past VPFD (min) to prevent inadvertent WRITE cycles pr ...
TLC2543-Q1 数据资料 dataSheet 下载
... 3. To minimize errors caused by noise at the CS input, the internal circuitry waits for a setup time after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup time has elapsed. 4. This is the time required for the clock input si ...
... 3. To minimize errors caused by noise at the CS input, the internal circuitry waits for a setup time after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup time has elapsed. 4. This is the time required for the clock input si ...
ADS1202 数据资料 dataSheet 下载
... The ADS1203 is a delta-sigma (∆Σ) modulator with a 95dB dynamic range, operating from a single +5V supply. The differential inputs are ideal for direct connection to transducers or low-level signals. With the appropriate digital filter and modulator rate, the device can be used to achieve 16-bit ana ...
... The ADS1203 is a delta-sigma (∆Σ) modulator with a 95dB dynamic range, operating from a single +5V supply. The differential inputs are ideal for direct connection to transducers or low-level signals. With the appropriate digital filter and modulator rate, the device can be used to achieve 16-bit ana ...
Optimized Pulse Patterns for the 5-Level ANPC
... The topology under consideration is the 5-level active neutral-point-clamped converter in Fig. 1, which has been introduced in [1]. This new topology only needs one floating capacitor to produce the five different output voltage levels. The redundant switching states are used to balance the capacito ...
... The topology under consideration is the 5-level active neutral-point-clamped converter in Fig. 1, which has been introduced in [1]. This new topology only needs one floating capacitor to produce the five different output voltage levels. The redundant switching states are used to balance the capacito ...
The benefits of ultrashort optical pulses in optically interconnected
... lasers of this design have been shown to give pulse widths less than 6 ps [12].) The diode laser repetition rate is variable; it can be modelocked at harmonics of the 200 MHz fundamental frequency in order to drive the link at high data rates and has been operated above 3 GHz. The wavelength of each ...
... lasers of this design have been shown to give pulse widths less than 6 ps [12].) The diode laser repetition rate is variable; it can be modelocked at harmonics of the 200 MHz fundamental frequency in order to drive the link at high data rates and has been operated above 3 GHz. The wavelength of each ...
5V Zero Power, TotalCMOS, Universal PLD Device
... XCR22V10: 5V Zero Power, TotalCMOS, Universal PLD Output Type The signal from the OR array can be fed directly to the output pin (combinatorial function) or latched in the D-type flip-flop (registered function). The D-type flip-flop latches data on the rising edge of the clock and is controlled by t ...
... XCR22V10: 5V Zero Power, TotalCMOS, Universal PLD Output Type The signal from the OR array can be fed directly to the output pin (combinatorial function) or latched in the D-type flip-flop (registered function). The D-type flip-flop latches data on the rising edge of the clock and is controlled by t ...
ADF4156 (Rev. E)
... There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). The RF output phase is programmable for applications that require a particular phase relationship between the output and th ...
... There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). The RF output phase is programmable for applications that require a particular phase relationship between the output and th ...
AD7666 数据手册DataSheet下载
... analog-to-digital converter that operates from a single 5 V power supply. The part contains a high speed, 16-bit sampling ADC, an internal conversion clock, internal reference, error correction circuits, and both serial and parallel system interface ports. The AD7666 is hardware factory-calibrated a ...
... analog-to-digital converter that operates from a single 5 V power supply. The part contains a high speed, 16-bit sampling ADC, an internal conversion clock, internal reference, error correction circuits, and both serial and parallel system interface ports. The AD7666 is hardware factory-calibrated a ...
A Dual-Output Integrated LLC Resonant Controller and LED
... converters are suitable for integration, since the two inductors required to form the LLC tank can be integrated into one magnetic core without the need for extra components [8]–[11]. The advantage of LLC resonant converters is that they can reduce the switching loss and noise since switching compon ...
... converters are suitable for integration, since the two inductors required to form the LLC tank can be integrated into one magnetic core without the need for extra components [8]–[11]. The advantage of LLC resonant converters is that they can reduce the switching loss and noise since switching compon ...
A 21mW 8-b 125 MS/s ADC in 0.09 mm2 0.13 um
... CMOS ADC occupies 0.09 mm2 and consumes 21 mW. Index Terms—Analog-to-digital conversion, CMOS analog integrated circuits (ICs), subranging analog-to-digital converter (ADC). ...
... CMOS ADC occupies 0.09 mm2 and consumes 21 mW. Index Terms—Analog-to-digital conversion, CMOS analog integrated circuits (ICs), subranging analog-to-digital converter (ADC). ...
MAX5878 16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs General Description
... digital-to-analog converter (DAC). This DAC meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from +3.3V and +1.8V supplies, this dual DAC offers exceptional dynamic performance such as 76dBc ...
... digital-to-analog converter (DAC). This DAC meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from +3.3V and +1.8V supplies, this dual DAC offers exceptional dynamic performance such as 76dBc ...
az of oscilloscope measurement terms
... Digital Storage Oscilloscope (DSO) – A digital oscilloscope that acquires signals using digital sampling (using an analogue-to-digital converter). It uses a serial processing architecture to control acquisition, user interface, and master display. A Digital Phosphor oscilloscope (DPO), shown, is an ...
... Digital Storage Oscilloscope (DSO) – A digital oscilloscope that acquires signals using digital sampling (using an analogue-to-digital converter). It uses a serial processing architecture to control acquisition, user interface, and master display. A Digital Phosphor oscilloscope (DPO), shown, is an ...
Nuclear Electronics Lab
... SCA. Example: The first SCA has a voltage window of 1.0-1.2V so the next SCA would have a voltage window of 1.2-1.4V and so on. Although MCA’s still work on the same principle, they consist of an analog to digital converter which converts the voltage input signal into a binary number. The binary num ...
... SCA. Example: The first SCA has a voltage window of 1.0-1.2V so the next SCA would have a voltage window of 1.2-1.4V and so on. Although MCA’s still work on the same principle, they consist of an analog to digital converter which converts the voltage input signal into a binary number. The binary num ...
Time-to-digital converter
In electronic instrumentation and signal processing, a time to digital converter (abbreviated TDC) is a device for recognizing events and providing a digital representation of the time they occurred. For example, a TDC might output the time of arrival for each incoming pulse. Some applications wish to measure the time interval between two events rather than some notion of an absolute time.In electronics time-to-digital converters (TDCs) or time digitizers are devices commonly used to measure a time interval and convert it into digital (binary) output. In some cases interpolating TDCs are also called time counters (TCs).TDCs are used in many different applications, where the time interval between two signal pulses (start and stop pulse) should be determined. Measurement is started and stopped, when either the rising or the falling edge of a signal pulse crosses a set threshold. These requirements are fulfilled in many physical experiments, like time-of-flight and lifetime measurements in atomic and high energy physics, experiments that involve laser ranging and electronic research involving the testing of integrated circuits and high-speed data transfer.