Time transfer through optical fibers over a distance of 73 km
... [5, 6] and accurate clock (time) comparisons using optical fibers [7, 8, 9]. In the latter cases often the term “time transfer” is used although a calibration of propagation delays is left undone so that the results demonstrate the precision and in some cases the reproducibility of the employed syst ...
... [5, 6] and accurate clock (time) comparisons using optical fibers [7, 8, 9]. In the latter cases often the term “time transfer” is used although a calibration of propagation delays is left undone so that the results demonstrate the precision and in some cases the reproducibility of the employed syst ...
BA6482AK
... switching current drive system, in which the rotor position is sensed by Hall devices. The motor drive current is sensed by a small resistor (RNF). The total drive current is controlled and limited by sensing the voltage developed across this resistor. The motor drive circuit consists of Hall amplif ...
... switching current drive system, in which the rotor position is sensed by Hall devices. The motor drive current is sensed by a small resistor (RNF). The total drive current is controlled and limited by sensing the voltage developed across this resistor. The motor drive circuit consists of Hall amplif ...
Nonvolatile memory chips
... Let us assume that S=0, R=0. o It can easily be seen from the circuit that Q=0 and Q =1 is a consistent state. This state is depicted in Figure 3-21(a). o It can easily be seen from the circuit that Q=1 and Q =0 is also a consistent state. This state is depicted in Figure 3-21(b). o It can easily be ...
... Let us assume that S=0, R=0. o It can easily be seen from the circuit that Q=0 and Q =1 is a consistent state. This state is depicted in Figure 3-21(a). o It can easily be seen from the circuit that Q=1 and Q =0 is also a consistent state. This state is depicted in Figure 3-21(b). o It can easily be ...
DS1307 64 x 8, Serial, I C Real
... Limits at -40°C are guaranteed by design and are not production tested. ICCS specified with VCC = 5.0V and SDA, SCL = 5.0V. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL si ...
... Limits at -40°C are guaranteed by design and are not production tested. ICCS specified with VCC = 5.0V and SDA, SCL = 5.0V. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL si ...
ISSCC D03_04 Karthik
... Inphi, Santa Clara, CA, Inphi, Singapore, Singapore, 3Inphi, Irvine, CA ...
... Inphi, Santa Clara, CA, Inphi, Singapore, Singapore, 3Inphi, Irvine, CA ...
Asynchronous Primitives in CML
... their advantages and disadvantages are discussed. Also, a summary of a brief description of Asynchronous circuit is presented. It is the main goal of this project to integrate the CML primitives into Asynchronous circuits. ...
... their advantages and disadvantages are discussed. Also, a summary of a brief description of Asynchronous circuit is presented. It is the main goal of this project to integrate the CML primitives into Asynchronous circuits. ...
DS1372 General Description Features
... Specified with I2C bus inactive, SCL = SDA = VCC. Measured with a 32.768kHz crystal attached to the X1 and X2 pins. The I2C minimum operating frequency is imposed by the requirement of timeout period. The first clock pulse is generated after this period. A device must internally provide a hold time ...
... Specified with I2C bus inactive, SCL = SDA = VCC. Measured with a 32.768kHz crystal attached to the X1 and X2 pins. The I2C minimum operating frequency is imposed by the requirement of timeout period. The first clock pulse is generated after this period. A device must internally provide a hold time ...
3 Phase Wave Generation
... ► Counter variable incremented by 3 every time Timer/Counter 2 interrupts ► OCRnA:C value generated from lookup table OCRnA = sin_lookup[counter] OCRnB = sin_lookup[counter+1] OCRnC = sin_lookup[counter+2] ► Interrupts ...
... ► Counter variable incremented by 3 every time Timer/Counter 2 interrupts ► OCRnA:C value generated from lookup table OCRnA = sin_lookup[counter] OCRnB = sin_lookup[counter+1] OCRnC = sin_lookup[counter+2] ► Interrupts ...
Article
... the MEG Experiment at PSI, Switzerland. This experiment searches for the lepton-flavor violating decay + e+ with a sensitivity down to 10-13. After a first prototype (DRS1), the second prototype (DRS2) has been fabricated in a 0.25 m CMOS process and successfully been tested. It contains 10 cha ...
... the MEG Experiment at PSI, Switzerland. This experiment searches for the lepton-flavor violating decay + e+ with a sensitivity down to 10-13. After a first prototype (DRS1), the second prototype (DRS2) has been fabricated in a 0.25 m CMOS process and successfully been tested. It contains 10 cha ...
Coulomb`s Law
... Capacitor A circuit element that stores electric energy and electric charges A capacitor always consists of two separated metals, one stores +q, and the other stores –q. A common capacitor is made of two parallel metal plates. Capacitance is defined as: C=q/V (F); Farad=Colomb/volt Capacitanc e only ...
... Capacitor A circuit element that stores electric energy and electric charges A capacitor always consists of two separated metals, one stores +q, and the other stores –q. A common capacitor is made of two parallel metal plates. Capacitance is defined as: C=q/V (F); Farad=Colomb/volt Capacitanc e only ...
32_Channel_Pres1
... frozen and no more channels can be added to the list of the ones to be read-out. (can be 25ns). a) Internal read-out with internal trigger When the trigger source is internal (i.e. tr=0), the first falling edge of the master clock following the activation of the internal trigger enables a counter: t ...
... frozen and no more channels can be added to the list of the ones to be read-out. (can be 25ns). a) Internal read-out with internal trigger When the trigger source is internal (i.e. tr=0), the first falling edge of the master clock following the activation of the internal trigger enables a counter: t ...
Datasheet
... assigned by the factory for each custom configuration, and a separate data sheet is kept on file. For more information on custom part numbers programmed at the factory, please contact your local IDT sales and marketing representative. While the information presented herein has been checked for both ...
... assigned by the factory for each custom configuration, and a separate data sheet is kept on file. For more information on custom part numbers programmed at the factory, please contact your local IDT sales and marketing representative. While the information presented herein has been checked for both ...
A Trigger System with High Voltage Isolation for
... So, the trigger pulses to control these switches play most important role in these designs. There are a number of research papers related to these designs based on different topologies. But, the trigger pulse generators i.e. trigger systems has not been explained completely. ...
... So, the trigger pulses to control these switches play most important role in these designs. There are a number of research papers related to these designs based on different topologies. But, the trigger pulse generators i.e. trigger systems has not been explained completely. ...
Chapter 7: Sampling, Digital Devices, and Data Acq.
... Single-ended connections – use one signal line (+-high) that is measured relative to ground (gnd). No local ground and short wires due to EMI noises. Differential-ended connections – allows voltage difference between two distinct input signals. High (+) and low (-) signals are isolated from grou ...
... Single-ended connections – use one signal line (+-high) that is measured relative to ground (gnd). No local ground and short wires due to EMI noises. Differential-ended connections – allows voltage difference between two distinct input signals. High (+) and low (-) signals are isolated from grou ...
Time-to-digital converter
In electronic instrumentation and signal processing, a time to digital converter (abbreviated TDC) is a device for recognizing events and providing a digital representation of the time they occurred. For example, a TDC might output the time of arrival for each incoming pulse. Some applications wish to measure the time interval between two events rather than some notion of an absolute time.In electronics time-to-digital converters (TDCs) or time digitizers are devices commonly used to measure a time interval and convert it into digital (binary) output. In some cases interpolating TDCs are also called time counters (TCs).TDCs are used in many different applications, where the time interval between two signal pulses (start and stop pulse) should be determined. Measurement is started and stopped, when either the rising or the falling edge of a signal pulse crosses a set threshold. These requirements are fulfilled in many physical experiments, like time-of-flight and lifetime measurements in atomic and high energy physics, experiments that involve laser ranging and electronic research involving the testing of integrated circuits and high-speed data transfer.