Download Extraction of MOSFET Parameters using 4007 Array

Experiment 2 – Extraction of MOSFET parameters
1. Extraction of the specific current IS
Using the current-based model for the long-channel MOSFET in Fig. 1, one can readily prove that:
d  ln( I D 
dVX


t dI R 
1 dI D
2

 1 i f 1

I D dVX
2 I S dVX 
t  i f  ir  
(1)
Additionally, if the MOS transistor operates in saturation, e.g., VY=VDD (1) can be written as:
d  ln( I D 
dVX

t

2
(2)

1 if 1
whereas for VY=VX+t/2, (1) can be written as:
d  ln( I D 
dVX

t

2
1  i f  1  ir

Expression (2) equals -1 deep in weak inversion (if<<1) and equals -0.5 for if=8 (IF=ID=8IS).
 Use the circuit in Fig. 1 with both VY=VDD and VY=VX+t/2 to determine IS for the nominal VT0.
 Set VG= nominal VT0 and measure the normalization current from both (2) and (3).
MY NOTE: Where do I get the nominal Vt?
MY NOTE: Set VG= nominal VT0 and measure the normalization current from both (2) and (3).
Use Vt determined from 8*Is in the first lab.
VY
ID
VG VX
Fig. 1- Extraction of IS from gms/ID
(3)
1.2. Using the methodology described in reference [5], find IS and VT0 of the MOSFET.
 Plot ID vs VG and gmg/ID vs VG.
 Your measurements should range from at least if0.01 to if100.
 What is the thermal voltage associated with your measurements?
 What is the approximate value of n in weak inversion? Don’t forget to register the temperature while
you are taking the measurements.
MY NOTES: Measure plateau level. This allows you to find n and If. Then do the Vt extraction.
2. Extraction of VP
If the drain current is set to 3IS, as shown in the circuit of Fig. 2, then VP = VS. For VS in the range –0.2V
1
to approximately 6 V, plot the curve VS(VP) versus VG. Determine the value of VT0. Also plot n   dVP / dVG  .
Fig. 2: Circuit for the extraction of VP and n.
3. Write a technical report. Due date is July 14. You are expected to comment on the results and compare
results with theory.
References:
[1] A. I. A. Cunha, M. C. Schneider and C. Galup-Montoro, "An MOS Transistor Model for Analog Circuit Design", IEEE
J. Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, October 1998.
[2] C. Galup-Montoro and M. C. Schneider, MOSFET Modeling for Circuit Analysis and Design, WSP, Singapore, 2007.
[3] M. C. Schneider and C. Galup-Montoro, CMOS Analog Design Using All-Region MOSFET Modeling, Cambridge University
Press, Cambridge, 2010.
[4] C. Galup-Montoro, M. C. Schneider, and A. I. A. Cunha, “A Current-Based MOSFET Model for Integrated Circuit Design”,
Chapter 2 in Low-Voltage/Low-Power Integrated Circuits and Systems, edited by E. Sánchez-Sinencio and A. Andreou, IEEE
Press, 1999, ISBN 0-7803-3446-9.
[5] A. I. A. Cunha, M. C. Schneider, C. Galup-Montoro, C. D. C. Caetano, and M. B. Machado, "Unambiguous extraction of
threshold voltage based on the transconductance-to-current ratio", Workshop on Compact Modeling, Anaheim,
USA, Proceedings of Nanotech 2005, pp.139 - 141, May 2005.
[6] Technical reports:
i. Fabiano Luz Cardoso – CNPq 1999
ii. Luiz Henrique Spiller – CNPq 2001
iii. Rafael Matos Coitinho – CNPq 2001