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ENERGY AND AREA EFFICIENT THREE-INPUT XOR/XNORS WITH
SYSTEMATIC CELL DESIGN METHODOLOGY
ABSTRACT:
In this brief, we propose three efficient three-input XOR/XNOR circuits
as the most significant blocks of digital systems with a new systematic cell design
methodology (SCDM) in hybrid-CMOS logic style. SCDM, which is an extension
of CDM, plays the essential role in designing efficient circuits. At first, it is
deliberately given priority to general design goals in a base structure of circuits.
This structure is generated systematically by employing binary decision diagram.
After that, concerning high flexibility in design targets, SCDM aims to specific
ones in the remaining three steps, which are wise selections of basic cells and
amend mechanisms, as well as transistor sizing. In the end, the resultant three-input
XOR/XNORs enjoy full-swing and fairly balanced outputs. They perform well
with supply voltage scaling, and their critical path contains only two transistors.
They also outperform their counterparts exhibiting 27%–77% reduction in average
energy-delay product in HSPICE simulation based on TSMC 0.13-μm technology.
The symmetric schematic topologies significantly simplify and minimize the
layout, as 26%–32% improvement in area is demonstrated.
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EXISTING SYSTEM:
Such studies mostly rely on creative design ideas but do not follow a
systematic approach. As a consequence, most of them suffer from some different
disadvantages.
1) They are implemented with logic styles that have an incomplete voltage swing
in some internal nodes, which leads to static power dissipation.
2) Most of them suffer from severe output signal degradation and cannot sustain
low-voltage operation.
3) They predominantly have dynamic power consumption for nonbalanced
propagation delay inside and outside circuits, which results in glitches at the
outputs.
PROPOSED SYSTEM:
In the first stage, a three-input XOR/XNOR as one of the most complex
and all-purpose three-input basic gates in arithmetic circuits have been chosen. If
the efficiency of the circuits is confirmed in such a competitive environment, it can
show the strength of the methodology. In the second stage, CDM is matured as
systematic CDM (SCDM) in designing the three-input XOR/XNORs for the first
time. It systematically generates elementary basic cell (EBC) using binary decision
diagram (BDD), and wisely chooses circuit components based on a specific target.
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This takes place when the mentioned features are not considered in the
CDM. Therefore, after the systematic generation, the SCDM considers circuit
optimization based on our target in three steps: 1) wise selection of the basic cell;
2) wise selection of the amend mechanisms; and 3) transistor sizing. It should be
noted that BDD can be utilized for EBC generation of other three-input functions.
We consider the power-delay product (PDP) as the design target. It stands as a fair
performance metric, precisely involving portable electronic system targets. The
motivation to use this methodology is the presence of some unique features and the
ability to produce some efficient circuits.
LITERATURE SURVEY:
TITLE NAME: “Low-power high-speed full adder for portable electronic
applications,”
AUTHOR NAME:C.-K. Tung, S.-H. Shieh, and C.-H. Cheng,
A low-power, high-speed full adder (FA), abbreviated as LPHS-FA, is presented as
an elegant way to reduce circuit complexity and improve the performance thereof.
Employing as few as 15 MOSFETs in total, an LPHS-FA requires 60-73% fewer
transistors than other existing FAs with drivability. For validation purpose,
HSPICE simulations are conducted on all the proposed and referenced FAs based
on the TSMC 0.18-μm CMOS process technology. The LPHS-FA is found to
provide a 20.4-21.2% power saving, a 12.3-67.0% delay time reduction and a 35102% reduction in power delay product compared with the referenced FAs. In
short, an LPHS-FA is presented in a concise form as a high-performance FA in
practical applications.
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TITLE
NAME:
“CMOS
full-adders
for
energy-efficient
arithmetic
applications,”
AUTHOR NAME: M. Aguirre-Hernandez and M. Linares-Aranda,
We present two high-speed and low-power full-adder cells designed
with an alternative internal logic structure and pass-transistor logic styles that lead
to have a reduced power-delay product (PDP). We carried out a comparison
against other full-adders reported as having a low PDP, in terms of speed, power
consumption and area. All the full-adders were designed with a 0.18-μm CMOS
technology, and were tested using a comprehensive testbench that allowed to
measure the current taken from the full-adder inputs, besides the current provided
from the power-supply. Post-layout simulations show that the proposed full-adders
outperform its counterparts exhibiting an average PDP advantage of 80%, with
only 40% of relative area.
TITLE NAME: “Design methodologies for high-performance noise-tolerant
XOR-XNOR circuits,”
AUTHOR NAME:S. Goel, M. A. Elgamel, M. A. Bayoumi, and Y. Hanafy,
Scaling down to deep submicrometer (DSM) technology has made noise a metric
of equal importance as compared to power, speed, and area. Smaller feature size,
lower supply voltage, and higher frequency are some of the characteristics for
DSM circuits that make them more vulnerable to noise. New designs and circuit
techniques are required in order to achieve robustness in presence of noise.
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Novel methodologies for designing energy-efficient noise-tolerant
exclusive-OR-exclusive- NOR circuits that can operate at low-supply voltages with
good signal integrity and driving capability are proposed. The circuits designed,
after applying the proposed methodologies, are characterized and compared with
previously published circuits for reliability, speed and energy efficiency. To test
the driving capability of the proposed circuits, they are embedded in an existing 52 compressor design. The average noise threshold energy (ANTE) is used for
quantifying the noise immunity of the proposed circuits. Simulation results show
that, compared with the best available circuit in literature, the proposed circuits
exhibit better noise-immunity, lower power-delay product (PDP) and good driving
capability. All of the proposed circuits prove to be faster and successfully work at
all ranges of supply voltage starting from 3.3 V down to 0.6 V. The savings in the
PDP range from 94% to 21% for the given supply voltage range respectively and
the average improvement in the ANTE is 2.67X.
TITLE NAME: “An odd parity checker prototype using DNAzyme finite state
machine,”
AUTHOR NAME; A. Eshra and A. El-Sayed,
A finite-state machine (FSM) is an abstract mathematical model of computation
used to design both computer programs and sequential logic circuits. Considered as
an abstract model of computation, FSM is weak; it has less computational power
than some other models of computation such as the Turing machine. This paper
discusses the finite-state automata based on Deoxyribonucleic Acid (DNA) and
different implementations of DNA FSMs.
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Moreover, a comparison was made to clarify the advantages and
disadvantages of each kind of presented DNA FSMS. Since it is a major goal for
nanoscince, nanotechnology and super molecular chemistry is to design synthetic
molecular devices that are programmable and run autonomously. Programmable
means that the behavior of the device can be modified without redesigning the
whole structure. Autonomous means that it runs without externally mediated
change to the work cycle. In this paper we present an odd Parity Checker Prototype
Using DNAzyme FSM. Our paper makes use of a known design for a DNA
nanorobotic device due to Reif and Sahu for executing FSM computations using
DNAzymes. The main contribution of our paper is a description of how to program
that device to do a FSM computation known as odd parity checking. We describe
in detail finite state automaton built on 10-23 DNAzyme, and give its procedure of
design and computation. The design procedure has two major phases: designing
the language potential alphabet DNA strands, and depending on the first phase to
design the DNAzyme possible transitions.
TITLE NAME: “Transistor-level optimization of digital designs with flex
cells,”AUTHOR NAME: R. Roy, D. Bhattacharya, and V. Boppana,
The flex-cell approach, either alone or in combination with standard cells,
provides an optimally tuned set of building blocks for integrated circuit design
when optimality is measured using accepted and quantifiably definable metrics
such as clock speed, die size, and power consumption.
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SOFTWARE REQUIREMENTS:
 Xilinx ISE Design Suite 13.1
 Cadence-RTL Complier
 Cadence- encounter
REFERENCES:
[1] C.-K. Tung, S.-H. Shieh, and C.-H. Cheng, “Low-power high-speed full adder
for portable electronic applications,” Electron. Lett., vol. 49, no. 17, pp. 1063–
1064, Aug. 2013.
[2] M. Aguirre-Hernandez and M. Linares-Aranda, “CMOS full-adders for energyefficient arithmetic applications,” IEEE Trans. Very Large Scale Integr. (VLSI)
Syst., vol. 19, no. 4, pp. 718–721, Apr. 2011.
[3] M. H. Moaiyeri, R. F. Mirzaee, K. Navi, T. Nikoubin, and O. Kavehei, “Novel
direct designs for 3-input XOR function for low-power and highspeed
applications,” Int. J. Electron., vol. 97, no. 6, pp. 647–662, 2010.
[4] S. Goel, M. A. Elgamel, M. A. Bayoumi, and Y. Hanafy, “Design
methodologies for high-performance noise-tolerant XOR-XNOR circuits,” IEEE
Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 4, pp. 867–878, Apr. 2006.
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[5] S. Goel, A. Kumar, and M. Bayoumi, “Design of robust, energy-efficient full
adders for deep-submicrometer design using hybrid-CMOS logic style,” IEEE
Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 12, pp. 1309–1321, Dec.
2006.
[6] C.-H. Chang, J. Gu, and M. Zhang, “A review of 0.18-μm full adder
performances for tree structured arithmetic circuits,” IEEE Trans. Very Large
Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 686–695, Jun. 2005.
[7] T. Nikoubin, M. Grailoo, and S. H. Mozafari, “Cell design methodology based
on transmission gate for low-power high-speed balanced XOR-XNOR circuits in
hybrid-CMOS logic style,” J. Low Power Electron., vol. 6, no. 4, pp. 503–512,
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[8] T. Nikoubin, A. Baniasadi, F. Eslami, and K. Navi, “A new cell design
methodology for balanced XOR-XNOR circuits for hybrid- CMOS logic,” J. Low
Power Electron., vol. 5, no. 4, pp. 474–483, 2009.
[9] T. Nikoubin, M. Grailoo, and C. Li, “Cell design methodology (CDM) for
balanced Carry–InverseCarry circuits in hybrid-CMOS logic style,” Int. J.
Electron., vol. 101, no. 10, pp. 1357–1374, 2014.
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[10] A. Eshra and A. El-Sayed, “An odd parity checker prototype using DNAzyme
finite state machine,” IEEE/ACM Trans. Comput. Biol. Bioinf., vol. 11, no. 2, pp.
316–324, Mar./Apr. 2014.
[11] R. Roy, D. Bhattacharya, and V. Boppana, “Transistor-level optimization of
digital designs with flex cells,” Computer, vol. 38, no. 2, pp. 53–61, Feb. 2005.
[12] M. Rahman, R. Afonso, H. Tennakoon, and C. Sechen, “Design automation
tools and libraries for low power digital design,” in Proc. IEEE Dallas Circuits
Syst. Workshop (DCAS), Oct. 2010, pp. 1–4.