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Designing VLSI Systems with Integrated Nano-Electro-Mechanical Relays Vladimir Stojanović (MIT) in collaboration with Tsu-Jae King Liu, Elad Alon (UC Berkeley) Dejan Marković (UCLA) ISSC 2010 Acknowledgements Circuit design Device design Fred Chen, Hossein Fariborzi Matthew Spencer, Abhinav Gupta Cheng Wang, Kevin Dwan Hei Kam, Rhesa Nathanael, Vincent Pott, Jaeseok Jeon Sponsors DARPA NEMS program FCRP (C2S2, MSD) MIT CICS Berkeley Wireless Research Center NSF 2 CMOS is Scaling, Power Density is Not Power Density Prediction circa 2000 Power Density (W/cm2) 10000 100 Rocket Nozzle Nuclear Reactor Core 2 8086 Hot Plate 10 4004 P6 80088085 386 Pentium® proc 286 486 8080 1 1970 1980 1990 2000 2010 Year S. Borkar, Intel Since ~2000 supply voltage (Vdd) stuck at ~1V 1000 Sun’s Surface Leakage stops you from lowering threshold (Vth) Vdd and Vt not scaling well power/area not scaling Performance limited by power, not number of transistors 3 Parallelism to the Rescue IBM CELL processor Lower supply, balanced Vth Parallelize to recover performance Parallelism allows slower, more efficient units Helps scale performance for fixed power Will this last forever? 4 4 Subthreshold leakage: Game Over for CMOS Leakage and sub-threshold slope define minimum energy/op for CMOS Parallelism cannot reduce power if already operating at minimum energy 5 NEM Relays to the Rescue Measured MEM Switch I-V Curve MEM Switch Energy vs. VDD Etotal=Edynamic NEM relays show zero leakage & sharp sub-threshold slope Could potentially enable reduced E/op with scaling Emin set by contact bond energy ~4aJ/switch (10x better than 65nm CMOS) R. Nathanael et al., “4-Terminal Relay Technology for Complementary Logic,” IEDM 2009 6 NEM Relay Structure and Operation Tungsten Channel Tungsten Body Poly-SiGe Gate Poly-SiGe Anchor Poly-SiGe Beam /Flexure Tungsten Source/Drain OFF Relay: |Vgb| < Vpo (pull-out voltage) ON Relay: |Vgb| > Vpi (pull-in voltage) 7 NEM Relay as a Logic Element Gate Source 4-terminal design mimics MOSFET operation Body Drain Electrostatic actuation is ambipolar Non-inverting logic is possible Actuation independent of source/drain voltages 8 NEM Relay Model Anchor Spring k Mechanical Model Damper b Mass m G Cgc S D Rs Cgb Rcs Rcd Rd Cdb Csb B Lumped Verilog-A model for circuit design and simulation: Mechanical dynamics: spring (k), damper (b), mass (m) Electrical parasitics: non-linear gate-body (Cgb), gate-channel (Cgc), and source/drain-body cap (Cs,db), contact (Rcs,d) 9 NEM Relay Characteristics tPI[s] Model 1.E-06 Model Experiment L=50mm 40mm 14mm 10 15 1.E-07 0 5 VDD [V] Simple electro-mechanical model matches experiment well Mechanical “pull-in” delay scales with geometry and overdrive voltage “Pull-in” voltage (threshold) scales with switch geometry Constant E-field scaling Mechanical delay and VPI scale linearly *H. Kam et al., “Design and Reliability of a Micro-Relay Technology…,” IEDM 2009 10 Digital Circuit Design with NEMS NEMS: 12 relays CMOS: delay set by electrical time constant Quadratic delay penalty for stacking devices Buffer & distribute logical/electrical effort over many stages NEMS: delay dominated by mechanical movement Can stack ~100-200 devices before td,elec ≈ td,mech So, want all to switch simultaneously Implement logic as a single complex gate 11 Need to Compare at Block Level NEMS: 12 relays 4 gate delays Delay Comparison vs. CMOS 1 mechanical delay Single mechanical delay vs. several electrical gate delays For reasonable load, NEMS delay unaffected by fan-out/fan-in Area Comparison vs. CMOS Larger individual devices But often need fewer devices to implement same function F. Chen et al., “Integrated Circuit Design with NEM Relays,” ICCAD 2008 12 Example: NEMS Full Adder Cell Full adder cell: 12 NEMS vs. 24 transistors XOR “free” Complementary signals avoid extra mechanical delay (to invert) NEMS all sized minimally 13 Building a 32-bit NEMS Adder Ripple carry configuration Cascade full adder cells to create larger complex gate Stack 32 NEMS, but still single mechanical delay 14 Scaled NEMS vs. CMOS Adders Energy/op vs. Delay/op across Vdd 9x Compare vs. Sklansky CMOS adder* 30x less capacitance 10x 2.4x lower Vdd Lower device Cg, Cd Fewer devices No leakage energy For similar area: >9x lower E/op, >10x greater delay F. Chen et al., “Integrated Circuit Design with NEM Relays,” ICCAD 2008 *D. Patil et. al., “Robust Energy-Efficient Adder Topologies,” in Proc. 18th IEEE Symp. on Computer Arithmetic (ARITH'07). 15 Parallelism helps Energy/op vs. Delay/op across Vdd & CL Can extend energy benefit up to GOP/s throughput As long as parallelism is available Area overhead bounded CMOS needs to be parallelized at some point too 16 16 Contact Resistance Energy/op vs. Delay/op across Vdd & CL Low contact R not critical Good news for reliability… 17 Contact Endurance AFM Measurements 3 μm 1.E+05 1.E+04 L=25mm 0 10 50 20 Height 30 40(nm) Height (nm) Contact Dimple (c) 1.E+0 1.E+3 1.E+6 1.E+9 No. of on/off cycles AFTER 109 cycles 19nm (d) 19nm Dimple Measured in ambient 1.E+02 (b) Relative distribution (a. i.) 1.E+03 FRESH CONTACT Never tested 19nm 19nm Dimple (a) Contact Dimple Relative distribution (a. i.) 100k specification 3 μm Contact resistance [Ω] 1.E+06 Variations likely due to W oxidation No visible surface wear after 1 billion ON/OFF cycles Measured > 60 billion cycles so far 0 10 20 30 40 50 Height (nm) [H. Kam et al., IEDM 2009] 18 NEMS Circuit Demonstration Test Devices Logic Timing Elements Latches, FFs Memory Adders, Compressors SRAM, DRAM I/O ADC, DAC F. Chen et al., “Demonstration of Integrated Micro-Electro-Mechanical Switch Circuits for VLSI Applications,” ISSCC 2010. 19 Things We Learned… Layout Matters Unbalanced current flow: flexures burn up! Parasitic capacitors: can affect Vpi (DIBL-like effect) 20 Measured Inverter VTC VTC looks digital, suggests composability 21 NEMS Latch Shows Composability Designed as if we used MOSFETS, but that is not always optimal… 22 Oscillator Illustrates Delay Characteristics Mechanical time constant (tmech) >> electrical (telec) Contact resistance only affects telec, not tmech. Little impact on overall delay since tmech is large. Higher Rcontact (1-10k) improves reliability (>109 cycles [2]) [2] Kam, et al. IEDM ‘09 23 Relay-based Carry Generation Demonstrates propagate-generate-kill logic as a single complex gate 24 Measured DRAM Results Simultaneous read and write Read latency = tmech,on (decoder) + tmech,off (WLRD relay) 25 CMOS vs. Relays: Mixed Signal I/O energy dominant if core is ~30x more efficient See if I/O circuits can benefit as well Representative examples: DAC & ADC How to process/generate analog signals? No or limited “linear gain” in relays – rely on switching 26 NEM Relay Based DAC DAC Architecture Voltage Output AC Impedance EBIT 2 VIO2 CL Same topology as CMOS, except: Add passive R to set impedance Relays’ gate voltage independent of I/O voltage Energy dominated by actual I/O energy: @VIO=200mV, CL=1pF: 62.8fJ/bit vs. ~780fJ/bit for CMOS 27 Measured DAC Results Code = “Vin” 1 1 Code = 0 0 “Vin” Resistive divider based DAC 2-bit thermometer coded output 2828 Relay-based ADC Vcore = 0.3V C = 500fF R = 4k VREF = 1V fsamp = 10 MS/s 6-bit res: 5.5fJ/conv Energy dominated by resistor string (320fJ out of 350fJ) Power set by input dynamic range (VREF), not core voltage FOM improves with more resolution (up to thermal noise limit) Can get rid of the ladder – size relays differently and get different Vpi’s Main advantages over CMOS stem from RonCg product 29 NEM relay scaling – next design 1um litho NEM relay size 120um x 150um 0.25um litho Scaled NEM relay 20um x 20um 30 Conclusions NEMS unique features enable scaling post-CMOS t Reliability improving Nearly ideal Ion/Ioff Switching delay largely independent of electrical Need to adapt circuit design style Circuit level insights critical (contact R) Demonstrated simple circuits (digital and analog) Can start thinking about building more complex systems Potentially order of magnitude lower E/op than CMOS Next steps: scaling and improved device design, testing larger digital blocks 31