Download Developers Conference - USB.org

Home Network Ready!
Design Issues and
Verification Challenges
Thomas Chow
Mentor Graphics Corporation
Inventra, IP Division
May 9, 2001
2
Historic Trend
May 9, 2001
3
Appliance Semiconductor
Market Snap Shot
May 9, 2001
4
Technology Trend
May 9, 2001
5
Home Network
Gateway Growth
May 9, 2001
6
Typical Home Network
Network
Shops
HN
Device
HN
Device
HN
Device
May 9, 2001
Gateway
Internet
Network
Bank
Network
BtoB
8
Typical Network
Appliance Architecture
Device
logic
and
User I/F
uP / uC
Firmware
I/F
Network Transfer Protocol
May 9, 2001
9
SoC is Difficult
Because It’s a SYSTEM
System
Trade-Offs
HARDWARE
Embedded
Cores
Embedded
Software
Integration &
Verification
Digital
Logic/
Memory
Analog
Integration &
Verification
Reiteration Loop
Reiteration Loop
SOFTWARE
Integration &
Verification
Manufacturing
 Multiple Technologies - Hardware/Software, Analog/Digital
 Multiple Teams - Hardware (Analog/Digital), Software, System
 Multiple Embedded Systems - IP Cores
May 9, 2001
10
SoC Design Flow
EARLY DESIGN
Hardware Design
Re-usable IP
Infrastructure Services
INSPIRATION
POST-SILICON
On-Chip Debug IP
Synchronized Debugging
PRE-SILICON
NEW PRODUCTS
May 9, 2001
Multi-core Debugging
Co-Verification
HW Acceleration
11
Traditional Waterfall
ASIC Design Flow
Specification Development
RTL Code Development
Functional Verification
Synthesis
Timing Verification
Place and Route
Prototype Build and Test
RMM II, Chapter 2, fig. 2.2
Deliver to system integration and software test
May 9, 2001
12
Spiral SoC Design Flow
Parallel, concurrent development of HW-SW
Parallel verification and synthesis of modules
Floorplanning and P&R included in the
synthesis process
Planned iteration throughout
May 9, 2001
13
SoC Verification /
Debug Environment
Driver /
Control
A
Port A
Driver /
Control
B
Test bench
Self-stimulating
Port B
Test Board
Soft Core
Firmware
I/F Bus
Behavior
Model
8-bit MCU
Embedded
IEEE-1284
SRAM/ROM
Model
In Circuit Emulator
OCI / JTAG
EPP
Source Level Debugger Tcl/Tk
Command Line Interface
May 9, 2001
M8051
E- Warp
Debugger
JTAG
14
Choice Processor
Selection Criteria
Preserve legacy 8051 investments
– Tools (off-the-shelf compilers, debuggers)
– Applications
8-bit architecture
– Boost performance
– Address power consumption issues
– Address post-integration issues
May 9, 2001
15
M8051Warp
Power/Performance Balance
20
10
10
20
30
60 MHz M8051 Core
30
40 MHz 80C51 Part
for state machine, CPU,
Timers and Serial I/F
33 MHz 'Turbo' Part
Separate clock controls
40
12 MHz 80C51 Part
– Gated clock
100 MHz M8051Warp Core
50
'MIPS'
In other words,
M8051Warp executes
6X faster than the
standard part
Power management
X6
40
50
60
X3
X1
70
80
90
100
Clock Speed (MHz)
May 9, 2001
16
Fully Evolved:
The M8051E-Warp
The need to test SW on an embedded
core grew in importance:
Post Silicon IP
 Debugger system available through
partnership with First Silicon
Solutions (FS2)
– PC (Windows) Based Software
– In-Target System Analyzer provides
interface to PC
M8051E-Warp
In-Circuit Debug
May 9, 2001
 On-Chip Instrumentation (OCI)
designed into M8051E-Warp for test
access via JTAG port
 Performance and low-power
benefits of the M8051Warp retained
17
Embedded System
Development
System Design
Hardware Design
Prototype Build
Hardware Debug
Software Design
Software Coding
Software Debug
Project Complete
May 9, 2001
18
Benefits for Software
Designers
Embedded Code
Stub Code to Emulate Hardware
HW Simulation
More time to develop and debug your code
Validate code against hardware as you develop
Maintain software design integrity
May 9, 2001
19
Typical Network Appliance
Architecture
Device
logic
and
User I/F
uP / uC
Firmware
I/F
Network Transfer Protocol
May 9, 2001
20
Network Transport
Selection - USB 2.0
 Topology
 Tiered Star
 127 connections (max)
 6 Tiers (max)
USB
 Bus Transactions
 480 / 12 / 1.5 Mbps
 Configuration
 Dynamic insertion/removal
 Auto configuration
 Physical Layer
 2-wire differential signaling,
NRZI, bit-stuffing, CMOS
level (3.3V)
 4-pin connector
 High Speed (480 Mbps)
Pen
HUB
HUB
Kbd
Monitor
Mouse
Speaker
HOST/HUB
PC
Mic
Phone
 Multi-Media, Video, Storage,
Broadband Access, Imaging
May 9, 2001
21
USB Focus on Low Cost,
High Volume Applications
BANDWIDTH
DEVICE COST APPLICATIONS
ATTRIBUTES
LOW
10 - 100Kb/s
$5-25
Input Devices
Control Functions
Very Low cost
Ease of Use
Lots of fanout
1997
FULL
$15-150
200K - 10Mb/s
Telephony/ Modem
Audio, Scanner
Low cost
Guaranteed latency
1997
HIGH
120 - 480Mb/s
$60 - 300
Entertainment, A/V
Imaging
High Speed
2000+
1394A
for CE
HIGH
100 - 400Mb/s
$100-500
Entertainment, A/V
Imaging
Peer-to-peer
Multiple channels
1999
1394B
Gigabit
COMPUTE
1+ Gb/s
$200-500
Primary Disk
Home Backbone
Very High bandwidth 1999
Fiber capability
USB
1.1
USB
2.0
May 9, 2001
STD FEATURE
22
Inventra USB 2.0 Device
Demo System and Diagram
May 9, 2001
23
High Speed Function
Controller
 USB 2.0 compliant for high/full speed functions
DMA
 Configurable
– 1 to 16 endpoints
– Endpoint Direction
– FIFO depth
 16/32bit VCI-compliant
CPU Interface
PP
 DMA access to FIFOs
USB Bus MC
HH
 Synchronous SingleYY
port RAM interface for
Outside of
FIFOs
Soft Core
May 9, 2001
Add
CONTROL
(Transaction State Machine)
Cntl
MCU
I/F
Packet Enc/Dec
CRC Gen/Check
ReSync
FIFO
Controller
Data
High Speed Function Controller
Soft Core
24
USB High Speed Function
Controller - Testbench
USBHSFC Testbench Architecture
Host Model
Host Data
Buffers
May 9, 2001
USB Bus
UTMI
Transceiver
MacroCell
Model
8/16 Bit
Synthesisable
USB Function
Controller Core
Behavioral
RAM
16/32 Bit
BVCI
Interface
Model
MCU Data
Buffers
27
USB High Speed Function
Core - Deliverables
 VHDL or Verilog RTL source code
 Test bench (VHDL or Verilog)
– Achieves > 99% code coverage
 Example synthesis and scan-test scripts (dc_shell)
– Targeted an example 0.18 micron technology
– Fault cover of > 98%
 Simulation scripts (ModelSim)
 Sample Firmware
– C code generated to match your configuration
 Configuration GUI
 User Guide, Product Spec, Datasheet sheet
May 9, 2001
28
Designed for Ease of Reuse
High quality RTL code
Tested on popular EDA tools
Mentor Graphics: ModelSim, Leonardo Spectrum
Synopsys: Design Compiler
TransEDA: VHDLCover, Verisure
Cadence: VerilogXL
VCI complaint CPU Interface
Configuration GUI
May 9, 2001
29
Friendly GUI
Let You Define Your Own USB Parameters
May 9, 2001
30
Gatecount Example
Area (kgates)
Gatecount Analysis
40
35
30
25
20
15
10
5
0
High Speed
Full Speed
1
2
4
8
10
13
15
# User Endpoints
 FIFO depths fixed at 64bytes  High Speed: Approx. 1500 gates
for each additional endpoint
 Number of endpoints varied
May 9, 2001
 Full Speed: Approx. 800 gates
for each additional endpoint
31
From SoC to Final Product
May 9, 2001
Logic
Custom
I/O Logic
Custom
Logic
ROM
RAM
Embedded
Core
32
Xilinx Home
Networking Forum
Xilinx selected Inventra USB 2.0 + M8051E-Warp
cores for Home Networking Reference Design
– Our cores plus Kawasaki’s UTMI PHY are in two
Spartan devices
Press Release on January 29, 2001
Demonstrated at their Forum during
February 1,2001
Additional solutions to follow
May 9, 2001
33
For More information about
Inventra IP’s USB products,
please visit:
www.mentor.com/inventra
and
www.usb.org
May 9, 2001
35