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COMPUTER ORGANIZATION
&
ARCHITECTURE
A digital computer solves problems by executing a sequence of
instructions called a program
Ioan Despi
Instructions can be written as:
1. High level language (C, C++, Java, Pascal) statements:
a=a+b
2. Assembly language statements:
add a,b
3. Bit patterns:
0000100011001100
Required steps to obtain an exe
from assembly language
• At assemble time, assembly language text is converted to
(binary) machine language
– They may be generated by translating instructions,
hexadecimal or decimal numbers, characters, etc.
– Addresses are translated by way of a symbol table
– Addresses are adjusted to allow for blocks of memory
reserved for arrays, etc.
• At link time, separately assembled modules are combined and
absolute addresses assigned
• At load time, the binary words are loaded into memory
• At run time, the PC is set to the starting address of the loaded
module (usually the o.s. makes a jump or procedure call to that
address)
WHAT IS “COMPUTER ARCHITECTURE”?
Applications
O/ S Kernel
Compiler
Instruction Set Architecture
Functional
Units
Memory
I/ O System
Logic Gates (Digital Design)
Devices (Circuit Design)
THE MAIN COMPONENTS OF A COMPUTER
control
input
Processor
Peripheral
Devices
datapath
Memory
output
Control Unit
causes successive instructions to be fetched from
memory and executed : fetch-execute cycle
instructions provided describe the instruction set
architecture (ISA) of the computer
this represents the interface between the hardware
and the lowest software level
Datapath
comprises two components:
arithmetic and logic unit (ALU)
register file
ALU performs simple operations between registers
A+B
A
B
registers
ALU
Memory
divided into cells, each of which has unique address
standard cell size of 8 bits (binary digits) called a byte
often, a parity bit is stored with each byte for checking
purposes;
the bit is chosen so that the total number of 1’s bits is
either
even - even parity
odd - odd parity
Memory
address
0
1
2
3
parity
Memory
• for many operations, bytes are grouped into words
• a machine may have a
2-byte (16-bit),
4-byte (32-bit) or
8-byte (64-bit) word
• some machines insist that accesses to words be aligned.
Access to a word of size S bytes at address A is allowed
only if
A mod S = 0
• an aligned 32-bit word machine would disallow access to a
word at address 3
Memory
Address
0
4
8
12
access disallowed
Memory
– RAM (Random Access Memory) can be both read and
written
– it is volatile : contents lost when power switched off
– DRAM (Dynamic RAM)
• must be refreshed regularly
• access time : ~100ns; capacity : ~16Mbits
• used in main memory (16-64Mbyte)
– SRAM (Static RAM )
• no refresh required
• access time : ~10ns; capacity : ~ 1Mbit
• used in cache memory (256Kbyte - 1Mbyte)
Memory
• Read only Memory (ROM) written once during
manufacture, thereafter only read
• it is non-volatile : contents remains when power switched
off
• several kinds of ROM
– ROM : read only memory (once, factory)
– PROM : programmable ROM (once, customer)
– EPROM : erasable PROM (many times, customer)
– EEPROM : electrically erasable PROM (many times,
customer)
MEMORY ADDRESSING =Logical structure of
a computer's random-access memory (RAM
The generic term for the smallest unit of memory that the CPU
can read or write is cell
In most modern computers, the size of a cell is 8 bits (1 byte)
Hardware-accessible units of memory larger than one cell are ca
words
Currently (1999) the most common word sizes are
32 bits (4 bytes) and
64 bits (8 bytes)
Byte - Addressed Memory
n
1
7 6 5 4 3 2 10
n
2
7 6 5 4 3 2 10
Byte
2n  3
7 6 5 4 3 2 10
Byte
2n  4
7 6 5 4 3 2 10
Byte 2
Byte 2
…
Byte 3
7 6 5 4 3 2 10
Byte 2
7 6 5 4 3 2 10
Byte 1
7 6 5 4 3 2 10
0
7 6 5 4 3 2 10
Byte
Byte -Addressed Memory: 32 bit addressing
Byte FFFFFFFF
7 6 5 4 3 2 10
Byte FFFFFFFE
7
6 5 4 3 2 10
Byte FFFFFFFD
7
6 5 4 3 2 10
Byte FFFFFFFC
7
6 5 4 3 2 10
Byte 00000003
7
6 5 4 3 2 10
Byte 00000002
7
6 5 4 3 2 10
Byte 00000001
7
6 5 4 3 2 10
Byte 00000000
7
6 5 4 3 2 10
The address of a
byte is 4-byte
word (32 bits)
…
addresses
data
addresses
Byte n + 7
Word Addressing
7 6 5 4 3 2 10
Byte n + 6
7 6 5 4 3 2 10
Byte n + 5
7 6 5 4 3 2 10
Byte n + 4
7 6 5 4 3 2 10
Byte n + 3
7 6 5 4 3 2 10
Byte n + 2
7 6 5 4 3 2 10
Byte n + 1
7 6 5 4 3 2 10
Byte n
7 6 5 4 3 2 10
Word
address = n + 4
Word
address = n
Every memory cell has a unique integer address
The CPU accesses a cell by giving its address
Addresses of logically adjacent cells differ by 1
The address space of a processor is the range of possible int
n
addresses, typically (02:  1
)
BYTE ORDERING
Big-endian byte ordering
Most significant (leftmost) byte has the lowest address
The address of a word is the address of its most significant
byte
Default byte ordering in MIPS, DEC Alpha, HP PA-RISC
and IBM/Motorola/Apple PowerPC architectures
Only available byte ordering in SPARC
and IBM 370 architectures
Little-endian byte ordering
Least significant (rightmost) byte has the lowest address
The address of a word is the address of its least significant
byte
Only available byte ordering in Intel 80x86,
National SemiconductorNS 32000 and DEC Vax
LITTLE-ENDIAN vs BIG-ENDIAN BYTE ORDERING
Affects the interpretation of multi-byte structures (4-byte words,
etc.)
Examples:
Strings:
"MIPS" = 4D 49 50 53 (big-endian)
= 53 50 49 4D (little-endian)
But
53 50 49 4D = "SPIM" (big-endian)
Unsigned 32-bit integer (such as an IP address):
81 6E 10 53 (base16) = 2,171,474,003 (base 10) (bigendian)
But
53 10 6E 81(base16) = 1,393,585,793 (base10) (littleendian)
Byte ordering conventions
The arrows point in the direction of increasingly significant digits
7
3
0
31
3
24
15
2
8
23
2
16
23
1
16
15
1
8
31
0
24
7
0
0
Bytes: 3210
Bytes: 0123
Big - Endian
Little - Endian
ALIGNMENT
In RISC ISAs, the address of the low-address byte of a block of m
ory that holds a data type must be a multiple of the data type's si
The address of a byte can be any unsigned integer within the
processor's address space
Assume that a word is 4 bytes (32 bits)
The address of a word (4 bytes) must be a multiple of 4
A word address ends with 2 zero bits (00)
Possible last hexadecimal digits in a word address: 0, 4, 8, C
The address of a doubleword (8 bytes) must be a multiple of 8
A doubleword address ends with 3 zero bits (000)
Possible last hexadecimal digits in a word address: 0, 8
The MIPS directive .align n
aligns block addresses on multiples of n
Input and Output
• input
– keyboard (character),
– mouse (x,y),
– disc(block)
•Output
- character terminal
25 x 80 characters, 8 attribute bits/character, 4kbyte video RAM
- bit-mapped terminal
1280 x 1024 pixels, 24 attribute bits/pixel, 3840kbyte video RAM
- laser printer
300-600 dots/inch (dpi), 6-12 pages per min
SIMULATORS
SPIM (“ 1/25th the performance at none of the cost”)
Simulates the RISC architecture (MIPS) most used
embedded systems (Nintendo 64, Sony PlayStation, ... )
Available for architectures other than the native one
The MIPS instruction set is simpler than most
The SPIM interface is better than any real debuggers
(Registers, data segment, text segment, stack)
Documentation: Patterson & Hennessy, Appendix A;
Waldron
XMPSIM
Simulates one Cray X- MP processor
Runs under DOS
Gives good view of pipeline timing, stalls, etc.
Scales, Units, and Conventions
Term
Normal Usage
As a power of 2
K (kilo-)
103
210 = 1,024
M (mega-)
106
220 = 1,048,576
G (giga-)
109
230 = 1,073,741,824
T (tera-)
1012
240 = 1,099,511,627,776
Term
Usage
m (milli-)
10-3
 (micro-)
10-6
n (nano-)
10-9
p (pico-)
10-12
Units: Bit (b), Byte (B), Nibble, Word (w), Double Word, Long Word,
Second (s), Hertz (Hz)