Download cutoff voltage, V GS(off)

Chapter 4
Field-Effect Transistors (FETs)
4.0 Field Effect Transistors (FETs)
4.1 The JFET
4.2 JFET Characteristics and Parameter
4.3 JFET Biasing
4.4 MOSFET
4.5 MOSFET Characteristics and Parameter
4.6 MOSFET Biasing
4.7 FET Amplification
4.8 Common-Source Amplifiers
4.9 Common-Drain Amplifiers
4.10 Common-Gate Amplifiers
4.1 The JFET
The JFET (junction field effect transistor) is a type of FET that operates with
a reverse biased pn junction to control current in a channel.
Terminals of a JFET are source, gate, and
drain. JFET can be either p-channel or nchannel.
For n-channel JFET, two p-type are
diffused in n-type material to form a
channel, and both p-type are connected to
gate lead. For simplicity, gate lead is
shown connected to only one of the p
regions.
Basic structure of JFET
JFET schematic symbols
Basic Operation
For n-channel, VDD provide drain-to-source voltage and supplies current
from drain-to-source. VGG set reverse-bias voltage between gate and
source. JFET always operated with the G-S pn junction reverse-bias.
Reverse-bias gate-source junction, produce depletion region along pnjunction, which extend into n-channel, thus increase it’s resistance by
restricting channel width. Channel resistance can be control by varying gate
voltage, thereby controlling the amount ID.
Increase VGG (reverse bias) will narrow the channel which increase the
resistance of the channel and decreases ID. This field or resistance limits ID.
With low or no VGG ID will maximum.
4.2 JFET Characteristics and
Parameters
Ohmic region
4.2 JFET Characteristics and Parameters
Let’s look at the effects with a VGS = 0V, by shorting gate to source. ID
increase proportionally with increase of VDD from 0V, (VDS increase as
VDD increase). Here, the channel resistance is constant because the
depletion region is not large enough to have significant effect. This is
called the ohmic region (point A to B), because VDS and ID are related to
Ohm law.
At B, curve level off and ID become almost constant and as VDS increases
from B to C (active region), reverse-bias VGD produce large enough
depletion region to offset increase in VDS, thus ID almost constant.
For VGS = 0V, value VDS at which ID become constant (Point B) is called
pinch-off voltage, Vp and it value is fix for a given JFET.
Continue increases in VDS above pinch-off produce almost constant ID and
called maximum drain current IDSS, and it always specified for the condition,
VGS = 0V.
Breakdown (Point C) is reached when ID
begin increase rapidly with further
increase VDS. It can damage the JFET, so
it always operate below breakdown and
within constant-current area (point B and
C).
As VGS increases more negative by adjusting VGG, family of drain
characteristic curves is produce. ID decreases as VGS is increased to larger
negative because of the narrowing of the channel. For each increase in
VGS, JFET reach pinch-off (where constant current begin), at value of VDS
less than VP. So, ID is controlled by VGS.
Value VGS that ID = 0, is called cutoff
voltage, VGS(off). JFET must operate
between VGS = 0V and VGS(off). The ID
vary from IDSS to almost zero. More
negative VGS, the smaller ID becomes
in the active region.
When VGS has sufficient negative
value, ID reduce to zero. Cut-off effect
caused by widening of the depletion
region to a point where it completely
closes the channel. P-channel
required negative VDD and positive
VGS.
Comparison of Pinch-off Voltage and Cutoff Voltage
There is difference between pinch-off and cut-off. VP is value of VDS at which ID
become constant and always measure at VGS = 0V. However, pinch-off occurs
for VDS < VP when VGS non-zero. So, VP is constant, and minimum value VGS
which ID constant varies with VGS. VGS(off) and VP always equal but opposite
sign. Data sheet usually give either VGS(off) or Vp but not both.
Example : If VGS(off) = -4V and IDSS = 12 mA, calculate min VDD for constant
current area.
VP = 4V = VDS min value
In constant current area, VGS = 0V, ID = IDSS =
12mA
VRD = IDRD = 12mA x 560Ω = 6.72V
So, VDD = VDS + VRD = 4V + 6.72V
= 10.7V
JFET Universal Transfer Characteristic
Range of VGS from 0V to VGSoff that control the amount of ID. For n-channel
VGS(off) is negative and for p-channel VGSoff is positive. Because VGS does
control ID, the relationship between these two quantities is important. From
graph, ID = 0 when VGS = VGS(off) and ID = IDSS when VGS = 0.
Transfer characteristic curve can be develop by plotting ID for value VGS at
pinch-off. Each point on transfer characteristic curve correspond to VGS
and ID on drain curve. Example, when VGS =-2V, ID = 4.32mA and the VGS(off)
= -5V and IDSS = 12mA.
Transfer characteristic can be express as ;
ID = IDSS(1 - VGS/VGS(off))2
From data sheet, ID for VGS can be
determine if VGS(off) and IDSS
known. The parabolic relationship
known as square law. JFET and
MOSFET often referred as squarelaw devices.
JFET Data Sheet.
JFET Forward Transconductance
Forward transconductance (transfer conductance), gm is the change in drain
current (ΔID)for a given change in gate to source voltage (ΔVGS) with the drain
to source voltage constant.
Forward transconductance, gm = ΔID/ ΔVGS with VDS constant. Because transfer
characteristic is non-linear, so gm value varies depend on curve set by VGS. A
data sheet normally gives gm at VGS = 0V (gm0). Where gm0 = (2IDSS) / |VGS(off)|.
So gm = gm0(1 – (VGS/VGSoff))
EX : if gm0 = 500 µS, VGS(off) = -6V , VGS = -4V and IDSS = 3.0 mA
gm = 500µS(1 – 4V/6V) = 1667 µS
ID = IDSS(1 – VGS/VGS(off))2 = 3.0 mA(1 – -4V/-6V) = 333 µA
Input Resistance and Capacitance
JFET operate with reverse-bias, so input resistance at gate is very high.
These is one advantage JFET over BJT. Data sheet often specify the input
resistance by giving a value for the gate reverse current, IGSS.
RIN = |VGS/IGSS|.
IGSS increase with temperature, so RIN decrease.
Input capacitance, Ciss, is a result of JFET operating with reverse-bias pnjunction and the value depends on amount of reverse voltage.
EX : If IGSS = = -2nA VGS = -20V
So RIN = |20V/2nA| = 10,000MΩ
From drain characteristic curve, above pinch-off ID is relatively constant over
VDS range, so large change in VDS produce small change in ID.
The ratio drain to source resistance, r’ds = ΔVDS/ ΔID
4.3 JFET Biasing
Self-Bias
Self-bias is most common for JFET. For n-channel G-S junction reverse-bias,
VGS must negative. RG has no effect on bias because there is no voltage
applied to gate and voltage to ground is 0V. RG only to isolate an ac signal
from ground in amplifier application. However, VGS will be positive and can
be determined ID = IS for all JFET circuits.
Is produce VRS and make source positive respect to ground.
Since IS = ID and VG = 0, then VS = IDRS.
VGS = VG – VS = 0 – IDRS = -IDRS
For p-channel, IRS produce negative
voltage at source, make gate positive
respect with source.
Since IS = ID, so VGS = IDRS.
Self-biased JFETs (IS = ID in all JFETs)
VD = VDD – IDRD
Since VS = IDRS, so VDS = VD – VS = VDD – ID(RD + RS)
Example : Find VDS and VGS for circuit below ;
Setting the Q-Point of a Self-Biased JFET
To establish bias point (Q-point) is to determine ID for desired VGS and
calculate RS = | VGS/ID |
For a VGS value, ID can be determine by transfer characteristic curve or using
IDSS and VGS(off) from data sheet.
Example : Find RS using transfer
characteristic at VGS = - 5V
From graph, ID = 6.25 mA, so
RS = |5V/6.25mA| = 800Ω
The data sheet provides IDSS and VGS(off). VGS is the desired voltage to set the
bias. ID = IDSS(1 - VGS/VGSoff)2
Ex : Find RS if IDSS = 25mA and VGS(off) = 15V, VGS = 5V
Midpoint Bias
Since midpoint biasing is the most common, where it allow the maximum
amount of ID swing between IDSS and 0V ,and values of RS and RD will
determine approximate midpoint bias. Half of IDSS would be ID that is
midpoint. VGS to establish this can be determined by, VGS  VGS(off)/3.4
ID = IDSS(1 – VGS/VGS(off))2 = IDSS(1 – (VGS(off)/3.4)/VGS(off)) = 0.5IDSS
To set drain voltage at mid point, VD = VDD/2, select RD to produce the desired
voltage drop. Choose RG slightly larger to prevent loading on driving stage in
cascade amplifier.
Ex : If IDSS = 12 mA and VGS(off) = -3V and VD= 6V, find RD and RS.
For mid-point ID = IDSS/2 = 6 mA
VGS = VGS(off)/3.4 = -3V/3.4V = 882 mV
RS = |VGS/ID| = 882mV/6mA =147Ω
VD = VDD – IDRD
IDRD = VDD – VD
RD = (VDD - VD)/ID = (12 - 6)/6mA = 1kΩ
Remember the purpose of biasing is to set a
point of operation (Q-point). In a self-biasing
type JFET circuit the Q-point is determined
by the given parameters of the JFET itself
and values of RS and RD. Setting it at
midpoint on the drain curve is most
common.
One thing not mentioned in the discussion
was RG. It’s value is arbitrary but it should
be large enough to keep the input
resistance high.
Graphical Analysis of a Self-Biased JFET
The transfer characteristic curve along
with other parameters can be used to
determine the mid-point bias Q-point of a
self-biased JFET circuit.
First determine the VGS when ID is zero ;
VGS = -IDRS (this establish a point at the
origin on the graph, ID=0; VGS=0)
Next, calculate VGS when ID=IDSS.
Then draw a line to connect this 2 point
(load line).
Where the two lines intersect gives us the
ID and VGS (Q-point) needed for mid-point
bias. Note that load line extends from
VGS(off) (ID= 0A) to VP(ID = IDSS)
Ex: Determine Q-point if RS = 680 Ω
For ID = 0
VGS = - IDRS = 0 x 680Ω = 0
IDSS = ID = 4 mA
VGS = -IDRS = -4mA x 680Ω
Q - point from graph
ID = 2.25mA
VGS = -1.5V
Voltage-Divider Bias
Voltage-divider bias can also be used to bias a JFET. Voltage at source must
be more positive than voltage at gate so R1 and R2 are used to keep gatesource junction in reverse bias. Operation is no different from self-bias.
Source voltage, VS = IDRS
Gate voltage, VG = (R2/(R1 + R2))VDD
VGS = VG – VS
Source voltage, VS = VG - VGS
Drain current, ID = VS/RS
So, ID = (VG – VGS) / RS
An n-channel JFET with voltage divider
bias (IS=ID)
EX : If R1 = 6.8 MΩ, R2 = 1.0 MΩ, RD = 3.3 KΩ, RS = 2.2 KΩ, VD = 7V and
VDD = 12V, find ID and VGS.
Graphical Analysis of a JFET with Voltage-Divider Bias
In using transfer characteristic curve to determine the approximate Q-point
we must establish the two points for the load line. The first point is ID = 0 and
find VGS (note that VGS = VG when ID = 0).
VGS = VG = (R2/(R1 + R2))VDD
The second point is find ID when VGS = 0, ID = VG/RS
Transfer characteristics can vary for
JFET of same type. This would
adversely affect the Q-point. Voltagedivider bias is less affected by this
than self-bias. This is an undesirable
problem that in extreme cases would
require trying several of the same
type until you find one that works
within the desired range of operation.
Ex : Determine the approx Q-point.
For ID = 0, VGS = VG = 2.2MΩ/4.4MΩ x 8V = 4V
For VGS = 0, ID = VG/RS = 4V/3.3kΩ = 1.2mA
4.4 MOSFET
Metal oxide semiconductor field effect transistor (MOSFET) has no actual
pn junction as the p and n materials are insulated from channel by a silicon
dioxide and static sensitive device and sometime called as IGFET.
There are depletion MOSFET (D-MOSFET) and enhancement MOSFET
(E-MOSFET). Drain and source D-MOSFET are diffuse into the substrate
material and connected to isolated gate by a narrow channel. E-MOSFET
has no structural channel.
D-MOSFET
D-MOSFET can be operated in depletion or enhancement modes and
sometimes called depletion/enhancement MOSFET. Gate voltage can either
positive or negative because it’s insulated from channel. n-channel MOSFET
operates in depletion mode when negative gate-to-source voltage is applied
and in enhancement mode when a positive gate-to-source voltage is applied.
It normally operated in depletion mode.
In schematic symbol, substrate,
indicated by arrow, normally but not
always connected internally to source.
Sometime, there is a separate
substrate pin. Inward arrow for nchannel and outward for p-channel.
In depletion mode, gate and channel act as capacitor and SiO2 insulating
layer is the dielectric. Negative charge from gate repel conduction electrons
from channel, leaving positive ion. So some n-channel electron is depleted,
thus decrease channel conductivity. The greater the voltage on gate, the
greater the depletion of n-channel electrons. When reach VGSoff, channel
totally depleted and ID = 0. So ID will conduct when VGS between VGS(off) and
0V.
In enhancement mode, positive gate voltage, electron are attracted into
channel, thus (enhancing) increasing channel conductivity.
E-MOSFET
E-MOSFET can operate only in enhancement mode and has no depletion
mode. It differs in construction from D-MOSFET, that it no structural channel
and substrate extends completely to SiO2 layer. For n-channel, positive gate
voltage above threshold value induces a channel by creating a thin layer of
negative charge in substrate region adjacent to SiO2 layer.
Conductivity of channel is enhanced
by increase VGS, thus pulling more
electron into channel area. For gate
voltage below threshold, there is no
channel.
In E-MOSFET schematic symbol, broken line symbolize the absence of
physical channel.
Conventional enhancement MOSFET have long thin lateral channel, and
this result a relatively high drain-to-source resistance and limits EMOSFET to low power applications.
When gate is positive, channel is formed close to gate between source
and drain.
Power MOSFET Structure
Lateral double diffused MOSFET (LDMOSFET) is specifically designed for
high power applications.
It’s has shorter channel between drain and source, so lower resistance,
which allow higher current and voltage.
V-groove MOSFET (VMOSFET) also specifically designed for high power
applications by creating a shorter and wider channel with less resistance
between drain and source.
Shorter, wider channel allow for higher current thus, greater power
dissipation and improve frequency response.
It’s has two source connections, gate on top and drain on the bottom.
Channel is induced vertically along both sided of v-shaped groove between
drain and source connection.
Channel length is set by layer
thickness, which is controlled by
doping density and diffusion time
rather mask dimension.
TMOSFET is similar to VMOSFET except it doesn’t use v-shaped
groove, so easier to manufacture. Gate structure is embedded in a
silicon dioxide layer, and the source contact is continuous over the entire
surface area. It achieve greater packing density while retaining short
vertical channel advantage.
Dual gate MOSFET can be either depletion or enhancement and have two
gates which helps control unwanted capacitive effects (reduced) so it can be
used in high-freq RF amplifier application. The arrangement also allow for
automatic gain control input in certain RF amplifiers.
4.5 MOSFET Characteristics and Parameters
D-MOSFET
D-MOSFET can operate either positive or negative gate voltage. The
general transfer characteristic curve where VGS = 0 correspond to IDSS and
where ID = 0 correspond to VGS(off) = -VP (as with the JFET).
The square-law expression also applied to D-MOSFET curve.
D-MOSFET general transfer characteristic curves
For D-MOSFET it’s enhancement mode also have to consider. Calculating ID
with given parameters in enhancement mode and depletion mode is same.
Note this equation is no different for ID than JFETs and that transfer
characteristics are similar except for it’s effect in enhancement mode.
ID = IDSS(1 - VGS/VGS(off) )2
Remember n and p channel polarity differences.
E-MOSFET
E-MOSFET uses only channel enhancement and for all practical purposes
does not conduct until VGS (positive for n-channel) reaches threshold
voltage, VGS(th). ID = 0 when VGS = 0V so it’s don’t have IDSS.
The transfer characteristic curve starts at VGS(th) rather than VGS(off) on the
horizontal axis and never intersects the vertical axis.
The equation for the E-MOSFET transfer characteristics curve is
ID = K(VGS - VGS(th))2
where K = ID(on) /(VGS - VGS(th))2
Handling Precautions
All MOS are subject to damage from electrostatic discharge (ESD).
Excess static charge can be accumulated coz input capacitance
combine with very high input resistance and can damage the device.
The precaution when handling MOSFET are ;
a.
b.
c.
d.
e.
Should be shipped and stored in conductive foam.
All instruments and metal benches in assembly and test should be
connected to earth ground.
Handler wrist strap should be connected to earth ground with a length
of wire and high value series resistor.
Don’t move MOS from circuit when power is on.
Don’t apply signals to MOS device while dc power supply is off.
4.6 MOSFET Biasing
Three ways to bias a MOSFET are zero-bias, voltage-divider bias, and
drain-feedback bias.
For D-MOSFET zero biasing has no applied bias voltage to the gate, VGS =
0 so an ac signal at gate varies the VGS above and below 0V.
Since VGS = 0, ID = IDSS
VDS = VDD – IDSSRD
RG is to accommodate an ac input
signal by isolating it from ground.
Since there is no dc gate current, RG
does not affect the zero gate-tosource bias.
A zero-biased D_MOSFET
Ex : Calculate VDS if VGS(off) = -8V and IDSS = 12mA
Since ID = IDSS = 12mA,
so VDS = VDD – IDSSRD = 18V – 12mA x 620Ω = 10.6V
For E-MOSFETs zero biasing cannot be used because VGS must higher
then VGS(th) so only voltage-divider bias or drain-feedback.
VGS = (R2 / (R1 + R2)) x VDD
VDS = VDD - IDRD
where ID = K(VGS -VGS(th))2 and
K = ID(on)/(VGS - VGS(th))2
With drain-feedback bias, IG = 0,
there is no voltage drop across
RG making VGS = VDS. With VGS
given,
ID = (VDD – VDS)/RD
Voltage divider bias
Ex: If ID(on) = 200mA at VGS = 4V and VGS(th) = 2V,
calculate VGS and VDS.
VGS = (R2 / (R1 + R2)) x VDD = 15kΩ/115kΩ x 24V = 3.13V
K = ID(on)/(VGS - VGS(th))2 = 200mA/4V2 = 50mA/V2
ID for VGS = 3.13V is ;
ID = K(VGS -VGS(th))2
= 50mA/V2 x (3.13V – 2V) = 63.8mA
VDS = VDD – IDRD
= 24V - 63.8mA x 200Ω = 11.2V
4.7 FET Amplification
FET amplifiers are similar to BJT amplifiers in operation.The purpose of the
amplifier is the same for both. FET amplifiers have certain advantages over
BJT amplifiers such as high input impedance. However, BJT normally has a
higher voltage gain.
There are also similarities in three amplifier configurations of FET and BJTs.
Common-source (emitter), common-drain (collector), and common-gate
(base) are three FET amplifier configurations.
Transconductance, gm = ΔID/ ΔVGS .
In ac gm = Id/Vgs, so Id = gmVgs
Internal FET equivalent circuits
There are internal gate to source resistance (r’gs), current source is gmVgs
and internal drain-to-source resistance ( r’ds).
Resistance r’gs can be neglected since it is so large in value and in most
cases r’ds can be neglected as well.
Voltage gain, AV = Vout/Vin = Vds/Vgs.
Since Vds = IdRd, Vgs = Id/gm
So, Av = IdRd/(Id/gm) =(gmIdRd)/Id
AV = gmRd
Example : If gm = 4ms and Rd=
1.5kΩ, calculate Av
Av = 6
Simplified FET equivalent circuit with an
external ac drain resistance
4.8 Common-Source Amplifiers
Common-source amplifier is one in which the ac input signal is applied to
the gate and ac output signal is taken from the drain. It either has no
source resistor or has a bypassed source resistor. RG is to keep gate at 0V
dc because IGSS is so small and it’s large value to prevent loading of ac
signal source. Bypass C2,keeps the source of JFET at ground.
Vin cause Vgs to swing along Qpoint and also do Id. As Id
increases, VRD increase, VD
decrease.
Vds also swing along Q-point and
1800 out of phase with Vgs.
DC Analysis
Capacitors are viewed as open when doing dc analysis.
Normally the value is ID = IDSS(1 – (IDRS/VGSoff))2
JFET common source amplifier
DC equivalent for the amplifier
AC Equivalent Circuit
Capacitors effectively as shorts and Xc = 0. Notice that dc source is at
ground and RD and RL are in parallel. This will lower Av by lowering the
overall drain resistance, Rd.
Since input resistance is extremely high, so Vin at gate will be very little
voltage drop across internal source resistance,
where Vgs = Vin
Av = gmRd
Vout = Vds = AvVgs or
Vout = gmRdVin
Where Rd = RD||RL and Vin = Vgs
Effect of an AC Load on Voltage Gain
When RL is connected to amplifier output through coupling capacitor C3, so
Rd = RD||RL because the upper RD is at ac ground.
Input Resistance.
Rin is extremely high and it approach infinite and can be neglected.
Rin is reverse-bias in FET and insulated gate in MOSFET .
The actual Rin is gate to ground, RG parallel with FET input resistance, RIN(gate)
is VGS/IGSS.
So Rin = RG || (VGS/IGSS)
Ex : If IGSS = 30 nA and VGS = 10V, find Rin.
D-MOSFET Amplifier Operation
Normally zero biased D-MOSFET amplifier with ac capacitive couple and it is
quite easy to analyze drain circuit since ID = IDSS. Gate is approx 0V dc and
source at ground, so VGS = 0V.
VD = VDD - IDRD
Signal voltage cause Vgs to swing at 0V. Negative Vgs swing produce
depletion mode and Id decrease. Positive Vgs swing produce enhancement
mode and Id increase.
Depletion-enhancement operation Zero-biased D-MOSFET common source amplifier
of D-MOSFET
Ex : If IDSS = 200 mA, gm = 200 ms and Vin = 500 mV, find VD and Vout.
E-MOSFET Amplifier Operation
For a voltage-divider biased E-MOSFET, circuit voltage divider set the VGS
needed to set Q-point above threshold. Value of K for dc analysis of ID is ;
K = ID(on) /(VGS - VGS(th))2
ID = K(VGS – V GS(th))2
As with JFET and D-MOSFET, the signal voltage produces a swing in VGS
above and below its Q point value, VGSQ. This cause Id swing above and
below its Q point value, IDQ.
It use voltage-divider bias for VGS > VGS(th)
VGS = (R2/(R1+R2)) x VDD
ID = K(VGS – VGS(th))2
VDS = VDD – IDRD
Av is same as JFET and D-MOSFET
Rin = R1||R2||RIN(gate)
Where RIN(gate) = VGS/IGSS
4.9 Common-Drain Amplifiers
Common-drain amplifier is similar to common-collector BJT amplifier in that
Vin is same as Vout with no phase shift. Gain is actually slightly less than 1.
Input signal is applied to gate, output is taken from source. It is known as
source-follower.
Self-bias is used in this circuit. Input is applied to gate through C1,output is
coupled to load resistor through C2. There is no drain resistor.
Vin = Vgs + IdRs
Vout = IdRs
Av = IdRs/(Vgs + IdRs)
Id = gmVgs so Av = gmRs/(1 + gmRs)
If gmRs >> 1, then good for Av = 1
Gate resistor, RG, input resistance looking
at the gate, RIN(gate)
Rin = RG||RIN(gate)
where RIN(gate) = VGS/IGSS
4.10 Common-Gate Amplifiers
Common-gate is similar to common base BJT amplifier in that it has a low
input resistance. Self-bias and gate is connected direct to ground. Input from
source and output from drain.
Av = Vd/Vgs = IdRd/Vgs = gmVgsRd/Vgs = gmRd
Rd = RD||RL
Both common source and common drain
configuration have high input because the
gate is input terminal. In contrast, common
gate configuration where the source is the
input terminal has a low input resistance.
Iin = Is = Id = gmVgs ;
Vin = Vgs
Rin(source) = Vin/Iin = Vgs/gmVgs = 1/gm
Rin = Rin(source)||RS
Example : Calculate Av and Rin if gm = 2000µS. Why VDD is neg.
Av = 10
Rin(source)
Rin = 452 Ω