Download CAD of Digital VLSI

CAD of Digital VLSI
Ralph Etienne-Cummings
Devices, Circuits, Inverters, Combination, Sequential and Basic Architecture
(Open book, No Collaboration)
Try all questions, as time allows. Clearly organize or solutions; partial credit will be
awarded. If you are running out of time, explain how you would have solved the
problem.
P1: (55 points)
Consider a 3-layer system of doped semi-conductors where the top layer is p-type with a
doping density of 1019/cm3, the middle layer is n-type with a doping density 1014/cm3 and
the bottom layer is p-type with doping density of 1011/cm3.
(a) Draw the equilibrium energy levels for the system, showing clearly where the
Fermi-level is located when there is no external voltage applied to the system. (5pts)
(b) Determine the built-in potential for each junction in the system. (10pts)
(c) If a voltmeter is attached between the top and bottom layers of the system, what
would be the reading on the meter? (5pts)
(d) What is the capacitance of each of the junctions assuming no external potential is
applied to the system. (Give your answer in F/m2) (10pts)
(e) If the top layer is held at 3V, the middle layer is held at 2V and the bottom layer is
held at 0V, draw the new energy diagram for the system. (10pts)
(f) What do you expect to happen if an ammeter is connected between the top layer
and the bottom layer? Explain. (5pts)
(g) What do you expect to happen if an ammeter is connected between the top layer
and the middle layer? Explain. (5pts)
(h) Is there a relationship between what will happen in (f) and (g)? Explain. (5pts)
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P2. (50 pts)
For the process whose parameters are provided at the end of this exam, design a CMOS
inverter with the following characteristics:
(a) The Logic Threshold is located at Vdd/2 (10pts)
(b) The rise and fall times are smaller than 1ns if the external load capacitance is
10fF. (20pts)
(c) Determine the VOL, VOH, VIL and VIH for the inverter. (20pts)
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P3. (65 pts)
You are to design a circuit that implements the following Boolean function:
Y= (A+B’)(C+D’) + E’(F+G) [Assume all inverses are available.]
(a) Determine how many transistors it takes to implement this function literally.
(10pts)
(b) Determine how many transistors it takes to implement it with NOR gates only.
(10pts)
(c) Determine how many transistors it takes to implement it as a complex CMOS gate.
(10pts)
(d) Identify the transitions with the shortest rise and fall times. (10pts)
(e) Identify the transition with the longest rise and fall times. (10pts)
(f) Assuming the mobility of the NMOS is twice that of the PMOS, and that the desired
transition times for the worse case transition is supposed to be 1, indicate the
relative sizes of the transistors in (c) that will achieve this goal. (10pts)
(g) Implement the function with Domino logic. How many transistors does it take?
(5pts)
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P4. (40 pts)
For the Mano Architecture, let the OPCODE be extended to 4bits. With the additional
space in your OPCODE, let us assume that a SUB (subtraction) is now possible as one of
the possible instruction.
(a)
(b)
(c)
(d)
(e)
Write the RTL description of the SUB instruction. (10pts)
Develop the timing sequence to execute the SUB instruction. (10pts)
Draw the flow chart to execute the SUB instruction. (5pts)
Modify the ALU to include the SUB instruction. (10pts)
Modify the LD, INR and CLR logic for the AC to implement the SUB instruction.
(5pts)
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Process Parameters:
NMOSFET
PMOSFET
K (oCox)
19.6 uA/V2
5.4 uA/V2
VTO
0.74 V
-0.74 V

0.6
0.6

0.06 V-1
0.19 V-1
Xd (Under Diffusion)
6 nm
6 nm
NSUB
1.3 x 10^(16) cm-3
4.8 x 10^(15) cm-3
COX
1.1 x 10^(-3) F/m2
1.1 x 10^(-3) F/m2
CGDO = CGSO
6.6 x 10^(-12) F/m
6.6 x 10^(-12) F/m
CJ
2.8 x 10^(-4) F/m2
3.0 x 10^(-4) F/m2
CJSW
1.7 x 10^(-10) F/m
2.6 x 10^(-10) F/m
mb = msw
0.5
0.5
b = sw
1V
1V
5um
Depth of Well
Boltzmann’s Constant (k)
1.38x10^-23 J/K
Electronic Charge (q)
1.6x10^-19 C
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