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Lecture 27 Sequencial Logic (cont’d) Mar. 17, 2003 Modern VLSI Design 3e: Chapters 5& 6 week11-1 Partly from 2002 Prentice Hall PTR Topics Memory elements. Basics of sequential machines. Modern VLSI Design 3e: Chapters 5& 6 week11-2 Partly from 2002 Prentice Hall PTR Flip-flops Not transparent—use multiple storage elements to isolate output from input. Major varieties: – master-slave; – edge-triggered. Modern VLSI Design 3e: Chapters 5& 6 week11-3 Partly from 2002 Prentice Hall PTR Master-slave flip-flop master slave D Q Modern VLSI Design 3e: Chapters 5& 6 week11-4 Partly from 2002 Prentice Hall PTR Master-slave operation = 0: master latch is disabled; slave latch is enabled, but master latch output is stable, so output does not change. = 1: master latch is enabled, loading value from input; slave latch is disabled, maintaining old output value. Modern VLSI Design 3e: Chapters 5& 6 week11-5 Partly from 2002 Prentice Hall PTR Sequential machines Use memory elements to make primary output values depend on state + primary inputs. Varieties: – Mealy—outputs function of present state, inputs; – Moore—outputs depend only on state. Modern VLSI Design 3e: Chapters 5& 6 week11-6 Partly from 2002 Prentice Hall PTR Sequential machine definition Machine computes next state N, primary outputs O from current state S, primary inputs I. Next-state function: – N = (I,S). Output function (Mealy): – O = (I,S). Modern VLSI Design 3e: Chapters 5& 6 week11-7 Partly from 2002 Prentice Hall PTR FSM structure Modern VLSI Design 3e: Chapters 5& 6 week11-8 Partly from 2002 Prentice Hall PTR Constraints on structure No combinational cycles. All components must have bounded delay. Modern VLSI Design 3e: Chapters 5& 6 week11-9 Partly from 2002 Prentice Hall PTR Signal skew Machine data signals must obey setup and hold times—avoid signal skew. Modern VLSI Design 3e: Chapters 5& 6 week11-10 Partly from 2002 Prentice Hall PTR Clock skew Clock must arrive at all memory elements in time to load data. Modern VLSI Design 3e: Chapters 5& 6 week11-11 Partly from 2002 Prentice Hall PTR Assignment 3 Questions: 3.9 (switch logic), 3.13, 3.15, 3.16, 3.17, 5.1, 5.4 VHDL and Verilog: one-bit full-adder 4-bit counter Due date: Mar. 31, 2003 12:00 pm Drop off: Modern VLSI Design 3e: Chapters 5& 6 EC 2135 week11-12 Partly from 2002 Prentice Hall PTR Lecture 28 VHDL and Memory RAM and ROM Mar. 19, 2003 Modern VLSI Design 3e: Chapters 5& 6 week11-13 Partly from 2002 Prentice Hall PTR VHDL example Counter Modern VLSI Design 3e: Chapters 5& 6 week11-14 Partly from 2002 Prentice Hall PTR Memory: basic concepts m × n memory Stores large number of bits – – – – … m x n: m words of n bits each k = Log2(m) address input signals or m = 2^k words e.g., 4,096 x 8 memory: m words … n bits per word » 32,768 bits » 12 address input signals » 8 input/output data signals memory external view r/w Memory access – r/w: selects read or write – enable: read or write only when asserted – multiport: multiple accesses to different locations simultaneously 2k × n read and write memory enable A0 … Ak-1 … Qn-1 Modern VLSI Design 3e: Chapters 5& 6 week11-15 Q0 Partly from 2002 Prentice Hall PTR Traditional ROM/RAM distinctions – ROM » read only, bits stored without power – RAM » read and write, lose stored bits without power Traditional distinctions blurred Storage permanence Write ability/ storage permanence Life of product Mask-programmed ROM OTP ROM EPROM Tens of years Battery life (10 years) – Advanced RAMs can hold bits without power » e.g., NVRAM Write ability – Manner and speed a memory can be written Storage permanence EEPROM FLASH NVRAM Nonvolatile – Advanced ROMs can be written to » e.g., EEPROM Ideal memory In-system programmable SRAM/DRAM Near zero Write ability During External External External fabrication programmer, programmer, programmer 1,000s OR in-system, only one time only 1,000s of cycles of cycles External In-system, fast programmer writes, OR in-system, unlimited block-oriented cycles writes, 1,000s of cycles Write ability and storage permanence of memories, showing relative degrees along each axis (not to scale). – ability of memory to hold stored bits after they are written Modern VLSI Design 3e: Chapters 5& 6 week11-16 Partly from 2002 Prentice Hall PTR Write ability Ranges of write ability – High end » processor writes to memory simply and quickly » e.g., RAM – Middle range » processor writes to memory, but slower » e.g., FLASH, EEPROM – Lower range » special equipment, “programmer”, must be used to write to memory » e.g., EPROM, OTP ROM – Low end » bits stored only during fabrication » e.g., Mask-programmed ROM In-system programmable memory – Can be written to by a processor in the embedded system using the memory – Memories in high end and middle range of write ability Modern VLSI Design 3e: Chapters 5& 6 week11-17 Partly from 2002 Prentice Hall PTR Storage permanence Range of storage permanence – High end » essentially never loses bits » e.g., mask-programmed ROM – Middle range » holds bits days, months, or years after memory’s power source turned off » e.g., NVRAM – Lower range » holds bits as long as power supplied to memory » e.g., SRAM – Low end » begins to lose bits almost immediately after written » e.g., DRAM Nonvolatile memory – Holds bits after power is no longer supplied – High end and middle range of storage permanence Modern VLSI Design 3e: Chapters 5& 6 week11-18 Partly from 2002 Prentice Hall PTR ROM: “Read-Only” Memory Modern VLSI Design 3e: Chapters 5& 6 week11-19 External view 2k × n ROM enable A0 … Nonvolatile memory Can be read from but not written to, by a processor in an embedded system Traditionally written to, “programmed”, before inserting to embedded system Uses – Store software program for general-purpose processor » program instructions can be one or more ROM words – Store constant data needed by system – Implement combinational circuit Ak-1 … Qn-1 Q0 Partly from 2002 Prentice Hall PTR Example: 8 x 4 ROM Horizontal lines = words Vertical lines = data Lines connected only at circles Decoder sets word 2’s line to 1 if address input is 010 Data lines Q3 and Q1 are set to 1 because there is a “programmed” connection with word 2’s line Word 2 is not connected with data lines Q2 and Q0 Output is 1010 Internal view 8 × 4 ROM word 0 enable 3×8 decoder word 1 word 2 A0 A1 A2 word line data line programmable connection wired-OR Q3 Q2 Q1 Q0 Modern VLSI Design 3e: Chapters 5& 6 week11-20 Partly from 2002 Prentice Hall PTR EPROM: Erasable programmable ROM Programmable component is a MOS transistor – Transistor has “floating” gate surrounded by an insulator – (a) Negative charges form a channel between source and drain storing a logic 1 – (b) Large positive voltage at gate causes negative charges to move out of channel and get trapped in floating gate storing a logic 0 – (c) (Erase) Shining UV rays on surface of floating-gate causes negative charges to return to channel from floating gate restoring the logic 1 – (d) An EPROM package showing quartz window through which UV light can pass (a) +15V (b) source drain 5-30 min source drain (c) Reduced storage permanence – program lasts about 10 years but is susceptible to radiation and electric noise drain source Better write ability – can be erased and reprogrammed thousands of times 0V floating gate Typically used during design development Modern VLSI Design 3e: Chapters 5& 6 week11-21 (d) . Partly from 2002 Prentice Hall PTR EEPROM: Electrically erasable programmable ROM Programmed and erased electronically – typically by using higher than normal voltage – can program and erase individual words Better write ability – can be in-system programmable with built-in circuit to provide higher than normal voltage » built-in memory controller commonly used to hide details from memory user – writes very slow due to erasing and programming » “busy” pin indicates to processor EEPROM still writing – can be erased and programmed tens of thousands of times Similar storage permanence to EPROM (about 10 years) Far more convenient than EPROMs, but more expensive Modern VLSI Design 3e: Chapters 5& 6 week11-22 Partly from 2002 Prentice Hall PTR RAM: “Random-access” memory external view Typically volatile memory r/w – bits are not held without power supply A0 Read and written to easily by embedded system during execution Internal structure more complex than ROM each cell in its column – rd/wr connected to every cell – when row is enabled by decoder, each cell has logic that stores input data bit when rd/wr indicates write or outputs stored bit when rd/wr indicates read Modern VLSI Design 3e: Chapters 5& 6 week11-23 … Ak-1 … Qn-1 Q0 internal view I3 I2 I1 I0 – a word consists of several memory cells, each storing 1 bit – each input and output data line connects to 2k × n read and write memory enable 4×4 RAM enable 2×4 decoder A0 A1 Memory cell rd/wr To every cell Q3 Q2 Q1 Q0 Partly from 2002 Prentice Hall PTR Basic types of RAM SRAM: Static RAM memory cell internals – Memory cell uses flip-flop to store bit – Requires 6 transistors – Holds data as long as power supplied SRAM Data' Data DRAM: Dynamic RAM – Memory cell uses MOS transistor and capacitor to store bit – More compact than SRAM – “Refresh” required due to capacitor leak » word’s cells refreshed when read W DRAM Data W – Typical refresh rate 15.625 microsec. – Slower to access than SRAM Modern VLSI Design 3e: Chapters 5& 6 week11-24 Partly from 2002 Prentice Hall PTR Ram variations PSRAM: Pseudo-static RAM – DRAM with built-in memory refresh controller – Popular low-cost high-density alternative to SRAM NVRAM: Nonvolatile RAM – Holds data after external power removed – Battery-backed RAM » SRAM with own permanently connected battery » writes as fast as reads » no limit on number of writes unlike nonvolatile ROM-based memory – SRAM with EEPROM or flash » stores complete RAM contents on EEPROM or flash before power turned off Modern VLSI Design 3e: Chapters 5& 6 week11-25 Partly from 2002 Prentice Hall PTR VHDL example RAM / ROM Modern VLSI Design 3e: Chapters 5& 6 week11-26 Partly from 2002 Prentice Hall PTR Lecture 29 Verilog Mar. 21, 2003 Modern VLSI Design 3e: Chapters 5& 6 week11-27 Partly from 2002 Prentice Hall PTR Verilog What is verilog? – Hardware Description Language(HDL) Why use a HDL? – – – It is becoming increasingly difficult to design directly on hardware. Exploring different design options is easier and cheaper. Reduces time and cost. Modern VLSI Design 3e: Chapters 5& 6 week11-28 Partly from 2002 Prentice Hall PTR Verilog Circuit Circuit Description Circuit Description Description Testfixture Verilog Simulator Simulation Result Modern VLSI Design 3e: Chapters 5& 6 week11-29 Partly from 2002 Prentice Hall PTR Verilog Example1 module mux(out, a, b, c); input a, b, c; output out; mux a b not n0(c_, c); and (o1, a, b); c or (out, c_, o1); endmodule Modern VLSI Design 3e: Chapters 5& 6 week11-30 o1 out c_ Partly from 2002 Prentice Hall PTR Verilog Example2 counter Modern VLSI Design 3e: Chapters 5& 6 week11-31 Partly from 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapters 5& 6 week11-32 Partly from 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapters 5& 6 week11-33 Partly from 2002 Prentice Hall PTR