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ATLAS
Electronics Issues, Frontend
(Strips that is, not Pixels)
US-ATLAS Upgrade R&D Meeting
UCSC
10-Nov-2005
A.A. Grillo
SCIPP – UCSC
10-Nov-05
1
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
1
Experience
ATLAS
We have shown for past experiments that the bipolar technology
has advantages over CMOS in power and performance for frontend amplification of silicon strip readout when the capacitive loads
are high and the shaping times short.
•
•
•
ZEUS-LPS
SSC-SDC
ATLAS-SCT
Tek-Z IC
LBIC IC
ABCD, CAFE-M, CAFE-P ICs
CMOS is the preferred technology for back-end data processing but
biCMOS technologies have not been readily available, making it
difficult to find a one chip solution.
Experience with the commercial 0.25 mm CMOS has shown the
great advantage of using a high volume commercial rather than a
niche technology.
10-Nov-05
2
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
2
Technical Issues
ATLAS
The ATLAS-ID upgrade will put even larger constraints on power.
Can we meet power and shaping time requirements with deep submicron CMOS?
•
Achieving sufficient transconductance of the frontend
transistor typically requires large bias currents.
The changes that make SiGe Bipolar technology operate at 100
GHz for the wireless industry coincide with the features
that enhance performance for our application.
•
Small feature size increases radiation tolerance
•
Extremely small base resistance (of order 10-100 W)
affords low noise designs at very low bias currents.
Can these features help us save power?
Will the SiGe technologies meet rad-hard requirements?
10-Nov-05
3
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
3
Example CMOS Front-End
ATLAS
J. Kaplon et al., 2004 IEEE Rome Oct 2004, use 0.25 mm CMOS
Can SiGe beat
these numbers?
For CMOS: Input transistor: 300 mA, other transistors 330 mA (each 20 – 90 mA)
10-Nov-05
4
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
4
biCMOS with Enhanced SiGe
ATLAS
The market for wireless communication has now spawned many biCMOS
technologies where the bipolar devices have been enhanced with a
germanium doped base region (SiGe devices).
We have identified at least the following vendors:
•
•
•
•
•
Growing number of fab facilities
IBM (at least
3 generations available)
STm
IHP, (Frankfurt on Oder, Germany)
Motorola
JAZZ
Advanced versions include CMOS with feature sizes of 0.25 mm to 0.13 mm.
The bipolar devices have DC current gains (b) of several 100 and fTs up to
200s of GHz. This implies very small geometries that could afford higher
current densities and more rad-hardness.
10-Nov-05
5
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
5
Radiation vs. Radius in Upgraded Tracker
The usefulness of a SiGe
bipolar front-end circuit will
depend upon its radiation
hardness for the various
regions (i.e. radii) where
silicon strip detectors might
be used.
10-Nov-05
6
Fluence [1014 neq/cm2]
ATLAS
Inner
Pixel
Electronics Issues, Frontend
Mid-Radius
Short Strips
Outer-Radius
“SCT”
E.N. Spencer
SCIPP-UCSC
6
Tracker Regions Amenable for SiGe
ATLAS
For the inner tracker layers, pixel detectors will be needed, and their
small capacitances allow the use of deep sub-micron CMOS as an
efficient readout technology.
Starting at a radius of about 20 cm, at fluence levels of 1015 n/cm2, short
strips can be used, with a detector length of about 3 cm and capacitances
of the order of 5 pF.
At a radius of about 60 cm, the expected fluence is a few times 1014 p/cm2,
and longer strips of about 10 cm and capacitance of 15 pF can be used.
It is in these two outer regions with sensors with larger capacitive loads
where bipolar SiGe might be used in the front-end readout ASICs with
welcome power savings while still maintaining fast shaping times.
10-Nov-05
7
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
7
Biasing the Analogue Circuit
ATLAS
The analog section of a readout IC for silicon strips typically has a special
front transistor, selected to minimize noise (often requiring a larger
current than the other transistors), and a large number of additional
transistors used in the shaping sections and for signal-level
discrimination.
The current for the front transistor is selected in order to achieve the
desired transconductance (minimize noise). For the other bipolar
devices, bias levels for the other transistors are determined to achieve the
necessary rad-hardness, matching and shaping times.
Depending upon the performance (especially radiation hardness) of the
bipolar process, power savings could be realized in both the front
transistor and in the other parts of the analogue circuit.
10-Nov-05
8
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
8
Evaluation of SiGe Radiation Hardness
ATLAS
The Team
D.E. Dorfan, A. A. Grillo, J. Metcalfe, M Rogers,
H. F.-W. Sadrozinski, A. Seiden, E. N. Spencer, M. Wilder
SCIPP-UCSC
Collaborators:
A. Sutton, J.D. Cressler
Georgia Tech, Atlanta, GA 30332-0250, USA
M. Ullan, M. Lozano
CNM, Barcelona
and newly joined:
S. Rescia et al.
BNL
10-Nov-05
9
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
9
First SiGe High-rate Radiation Testing
ATLAS
Radiation testing has been performed on some SiGe devices by our
Georgia Tech collaborators up to a fluence of 1x1014 p/cm2 and they
have demonstrated acceptable performance. (See for example:
http://isde.vanderbilt.edu/Content/muri/2005MURI/Cressler_MURI.ppt)
In order to extend this data to higher fluences, we obtained some
arrays of test structures from our collaborator at Georgia Tech.
These were from a b-enhanced 5HP process from IBM. (i.e. the b
was ~250 rather than ~100.)
The parts were tested at UCSC and with the help of RD50
collaborators (Michael Moll & Maurice Glaser) they were irradiated
in Fall 2004 at the CERN PS and then re-tested at UCSC.
For expediency, all terminals were grounded during the irradiation
This gives slightly amplified rad effects than with normal biasing.
Annealing was performed after initial post-rad testing.
10-Nov-05
10
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
10
Irradiated Samples
ATLAS
ATLAS Upgrade
Outer Radius
Pre-rad
4.15 x 1013
1.15 x 1014
3.50 x 1014
Mid Radius
Inner Radius
1.34 x 1015
10-Nov-05
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3.58 x 1015
Electronics Issues, Frontend
1.05 x 1016
E.N. Spencer
SCIPP-UCSC
11
Radiation Damage Mechanism
ATLAS
Forward Gummel Plot for 0.5x2.5 mm2
Ic,Ib vs. Vbe Pre-rad and After 1x1015 p/cm2 & Anneal Steps
Radiation damage
increases base
current causing the
gain of the device to
degrade.
Collector current
remains the same
Base current
increases after
irradiation
Gain=Ic/Ib (collector
current/base current)
Vbe [V]
Ionization Damage (in the spacer oxide layers)
• The charged nature of the particle creates oxide trapped charges and
interface states in the emitter-base spacer increasing the base current.
Displacement Damage (in the oxide and bulk)
• The incident mass of the particle knocks out atoms in the lattice
structure shortening hole lifetime, which is inversely proportional to
the base current.
10-Nov-05
12
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
12
Annealing Effects
ATLAS
Annealing of 0.5x2.5 mm2: Current Gain, b, vs. Ic
Pre-rad and After 1x1015 p/cm2 & Anneal Steps
Current Gain, b
Before Irradiation
After Irradiation
After Irradiation
& Full Annealing
Ic [A]
We studied the effects of annealing. The performance improves appreciably. In the case
above, the gain is now over 50 at 10mA entering into the region where an efficient chip
design may be implemented with this technology. The annealing effects are expected to be
sensitive to the biasing conditions. We plan to study this in the future.
10-Nov-05
13
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
13
Initial Results
ATLAS
Current Gain, b, vs. Ic for 0.5x10 mm2
Pre-rad and for All Fluences Including Full Annealing
Before Irradiation
Gain, bb
Current Gain,
Current
Lowest Fluence
Increasing Fluence
Highest Fluence
Ic [A]
After irradiation, the gain decreases as the fluence level increases. Performance is still
very good at a fluence level of 1x1015 p/cm2. A typical Ic for transistor operation might be
around 10 mA where a b of around 50 is required for a chip design. At 3x1015, operation
is still acceptable for certain applications.
10-Nov-05
14
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
14
Universality of Results
ATLAS
D(1/b)
Post-rad & Anneal to Pre-rad @ Jc=10mA
Ratio of Current Gain, b
Post-rad & Anneal to Pre-rad @ Jc=10 mA
Proton Fluence [p/cm2]
Proton Fluence [p/cm2]
Universal behavior independent of transistor geometry when compared at the same
current density Jc. For a given current density D(1/b) scales linearly with the log of
the fluence. This precise relation allows the gain after irradiation to be predicted for
other SiGe HBTs. Note there is little dependence on the initial gain value.
10-Nov-05
15
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
15
Feasibility for ATLAS ID Upgrade
ATLAS
Qualifications for a good transistor:
A gain of 50 is a good figure of merit for a transistor to use in a front-end
circuit design.
Low currents translate into increased power savings.
Fluence: 3.50E14 p/cm 2 (2.17x10 14 neq/cm2)
Fluence: 1.34E15 p/cm 2 (8.32x10 14 neq/cm2)
Transistor Size mm2
0.5x1
0.5x2.5
0.5x10
0.5x20
4x5
Transistor Size mm2
0.5x1
0.5x2.5
0.5x10
0.5x20
4x5
b=50
cirrad
2.E-06
4.E-06
3.E-05
5.E-05
9.E-06
Ic anneal
5.E-08
8.E-07
2.E-06
5.E-07
At 3.5x1014 in the outer region (60 cm),
where long (10 cm) silicon strip detectors
with capacitances around 15pF will be used,
the collector current Ic is low enough for
substantial power savings over CMOS!
10-Nov-05
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b=50
cirrad
3.E-05
7.E-05
4.E-04
1.E-04
Ic anneal
1.E-07
4.E-06
9.E-06
6.E-05
1.E-05
At 1.34x1015 closer to the mid radius (20 cm),
where short (3 cm) silicon strip detectors with
capacitance around 5pF will be used, the
collector current Ic is still good for a front
transistor, which requires a larger current while
minimizing noise. We expect better results from
3rd generation IBM SiGe HBTs.
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
16
IHP Design to Estimate Power of
Upgrade Frontend
ATLAS
IHP has the SG25H1 200 GHz SiGe process available on
Europractice. b is ~200. In parallel with radiation testing by
Barcelona, UCSC is developing an eight channel
amplifier/comparator with similar specifications to the present
ABCD.
The x4 minimum transistor has base resistance of 51 W,0.21mm x
3.36 mm. 0.25 mm CMOS is also included. Extensive use is made of
the 2.0 kW/ square unsilicided polysilicon resistor structure, since this
is expected to be radiation resistant.
The purpose of this FE design is to estimate the low current bias
performance of SiGe, and to see whether it can produce significant
power savings. The target voltage bias level is 2 V.
10-Nov-05
17
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
17
Design Procedure Details
ATLAS
IHP provides a Cadence Kit, with support for both Diva and Allegro.
The bipolar devices are complete as provided, no editing allowed,
with some hidden layers to protect IHP intellectual property.
Radiation hard annular NMOS transistor drawing is well supported.
This is done by allowing 135 degree bends of Poly lines on Active in
the DRC. There are included Virtuoso utilities that are needed for
successful DRC.
Cadence Spectre does not DC converge well. Mentor has Eldo utility
“Artist Link” that enables Eldo to run with Cadence schematic
Composer. Eldo converges vigorously. Overall, the Cadence Kit is
complete enough, and with the help of Eldo, is a good toolset.
10-Nov-05
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Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
18
Frontend Simulation Results
ATLAS
10-Nov-05
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Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
19
First Guess at Potential Power Savings
ATLAS
Using similar estimates of bias settings and transistor counts, an estimate for
power can be obtained.
CHIP TECHNOLOGY
FEATURE
Power: Bias for all but front
transistor
0.25 mm CMOS ABCDS/FE
J. Kaplon et al.,
(IEEE Rome Oct 2004)
330 mA
0.8 mW
IHP SG25H1 SCT-FE
Preliminary design
= 30 mA
.06 mW
(conservative)
Power: Front bias for 25 pF load
300 mA
0.75 mW
150 mA
0.30 mW
Power: Front bias for 7 pF load
120 mA
0.3 mW
50mA
0.10 mW
Total Power (7 pF)
Total Power (25 pF)
10-Nov-05
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2x1015
3x1014
1.1 mW
0.16mW
1.5 mW
0.36 mW
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
20
Conclusions on SiGe Evaluation So Far
ATLAS
First tests of one SiGe biCMOS process indicate that the bipolar
devices may be sufficiently rad-hard for the upgraded ATLAS
tracker, certainly in the outer-radius region and even perhaps in the
mid-radius region.
A simulation estimate of power consumption for such a SiGe frontend circuit indicates that significant power savings might be
achieved.
More work is needed to both confirm the radiation hardness and
arrive at more accurate estimates of power savings.
In particular, with so many potential commercial vendors available,
it is important to understand if the post-radiation performance is
generic to the SiGe technology or if it is specific to some versions.
10-Nov-05
21
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
21
Work Ahead
ATLAS
Along with our collaborators, we plan two parallel paths of work.
First, we plan more irradiations with several SiGe processes. In
particular, we plan to test at least the IBM 5HP, IBM enhanced 5HP,
IBM 8HP, IHP SG25H1 and one from STm.
•
•
•
•
CNM has obtained a first set of test structures from IHP and is
proceeding.
UCSC has recently received the IBM test structures.
We have been promised test structures from STm but a schedule
is not yet fixed.
Irradiations will be done with neutrons (Ljubljana), gammas
(BNL) and protons (CERN).
To obtain a better handle on the true power savings, we will submit
an IHP 8 channel amplifier/comparator early in 2006. This work is
in parallel with IHP radiation characterization.
10-Nov-05
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Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
22
Other Issues
ATLAS
Joining forces with CMOS:
• As was pointed out, the data processing backend of the readout IC
will use CMOS technology.
• The SiGe technologies we are looking at come with 0.25 mm to
0.13 mm CMOS, so a biCMOS solution is possible.
• It is assumed that these CMOS technologies will be or can be made
rad-hard as the 0.25 mm process was for current ATLAS. However,
this required 2-3 man-years to modify the IBM standard cell
library.
• The current CERN-IBM frame contract will expire at end of 2006.
• The tendering process for a new frame contract has started and
SiGe is stated as an option, but only an option.
10-Nov-05
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Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
23
More Issues
ATLAS
Joining forces with CMOS (cont.):
• If a frame contract is signed for a technology that does not include
SiGe, the SiGe biCMOS may require a duplication effort for
library conversion.
• A new frame contract itself may be an issue since the total number
of wafers expected for LHC Upgrade is expected to be much less
than it was for the present LHC construction and IBM has
already expressed disappointment in volume.
• With or without a frame contract, it would be very unfortunate
(and possibly not financially viable) to be forced to modify two
CMOS libraries, one for straight CMOS (e.g. for Pixels) and one
for SiGe biCMOS.
10-Nov-05
24
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
24
Yet More Issues
ATLAS
Readout architecture:
• The present readout IC uses binary readout (hit/no-hit).
• There is not universal satisfaction with this within the present
SCT community
• There is a call to re-evaluate the architecture choice
• Choice will be driven by lowest power option
There is a proposal to build an “ABCD-next” IC on 0.25 mm CMOS
• Prototype vehicle for detector development
• Dual polarity input
• Compatible with present SCT DAQ
• Some power regulation structures
• No identified funding source as yet
10-Nov-05
25
Electronics Issues, Frontend
E.N. Spencer
SCIPP-UCSC
25