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The Alice Silicon Pixel Redout System – Moving towards system integration Roberto Dinapoli CERN-CEM II,Montpellier For the ALICE Collaboration Colmar, 9-13 September 2002 Thanks to: Thanks to all the ALICE SPD Group!! And in particular, for their contributions to the present talk: Petra Riedler (Test beam, wafer probing) Peter Chochula (Test system) Michel Morel (Bus) Alex Kluge (Digital Pilot Chip and MCM) M. Campbell, Ken Wyllie (LHCBPIX1) Giorgio Stefanini Outline • The Alice Silicon Pixel Detector System • The front-end chip • The readout system and its components • The test system • The 2002 test beam • Conclusions The Alice Silicon Pixel Detector 2 barrel layers D z= 28.3 cm r= 3.9 cm & 7.6 cm Image: INFN Padova The Alice Silicon Pixel Detector: the front-end pixel chip •Mixed mode signal (analogue, digital) 13.5 mm •256 rows 32 columns (8192 channels) •13 million transistors 15.8 mm •Designed to serve ALICE and LHCb •10MHz clock •1.8V power supply •~100W/channel The Alice Silicon Pixel Detector: the ladder and the singles Ladder: Five chips Bump Bonding Single: Single chip Bump Bonding Ladder detector (12.8 x 69.6 mm2 active area) single chip detector (12.8 x 13.6 mm2 active area) Detector Chips: Chip Bump-bonding: • VTT/Finland Pb-Sn solder bumps • AMS/Italy In bumps • 750 µm thick, target: 150 µm Detectors: • p-in-n • 300 µm/200 µm thickness The Alice Silicon Pixel Detector: the half stave and the stave Half stave ± 193 mm ladder2 ladder1 70.72 mm 70.72 mm MCM Stave In total: • 60 staves • 240 ladders • 1200 chips • 9.83 E6 active channels Control,readout and and auxiliary chips: •Analog Pilot •Digital pilot •GOL •Optical links The Alice The ALICE SPD Silicon Pixel Detector: the sector One carbonfibre support for Layer 1+2 Image: INFN Padova readout of 120 half-staves in parallel 4 staves in layer 2 2 staves in layer 1 ladder ALICE1LHCb pixel cell 50 m 35mm 125mm 265mm 125mm 265mm pre-amp (differential) two digital delay units shaper (differential) trigger coincidence logic discriminator (+ fast-OR, fastMULT) 4-event FIFO buffer 65mW static consumption readout logic 35mm 5 un-upsettable latches for configuration test input on/off pixel mask on/off 3 bits of threshold adjust Pixel Front End: preamplifier-shaper Closed loop poles (s plane) Cfb SHAPER #1 IN A2 p2 r SHAPER #2 A3 p3 p3 PREAMPLIFIER gmf FEEDBACK STAGE fb = Cfb A2 gmf p1 x Simplified equation: s2 p2 fb+ s fb +1=0 j x p2 x fb=20 ns p2=5 ns p1-2=(8050j) Mrad/s p3=13.5 ns Radiation Tolerance Single Event Effects: Total Ionizing Dose: Studied at Louvain-la-Neuve No SEGR nor SEL observed Measure SEU rate indicates that in Alice environment it will not exceed 1bit/10hours of operation for the full detector (calculated for all DACs in SPD) Studied at CERN-MIC irradiation facility Total expected dose: Design tolerance: 2.5kGy 5 kGy Tested tolerance: >100kGy NOTE: ALL the asics in the barrel were designed in 0.25m CMOS technology using special layout and design techniques to obtain radiation tolerance Front-end results MEASURED: Gain: ~2 mV/100ePeaking time: ~35ns Power consumption: ~0.6W (@1.6V) Noise: ~180e- ½ shaper Problems: Pulser,Output buffers CORRECTED: Gain: ~3 mV/100ePeaking time: ~27ns Noise: ~120e- preamp Threshold distribution (no threshold adjust) and Threshold Scan noise Pulse each row (e.g. 250 triggers) with test-pulse (e.g. 0-50 mV) Mean minimum threshold: ~1000 e-, ~ 200 e- RMS Determined from S-curve. Mean noise:~120 e- Wafers Wafer probing On our wafer prober we can test: single chips, assemblies, ladders, wafers • 8” wafers (200 mm diameter) • Each wafer contains 86 ALICE1LHCb chips (chip-size: 15.8 x 13.5 mm2) Tests for each chip: Power supply currents JTAG functionality DAC scans Configuration registers functionality Minimum threshold Threshold Scan •Yield of class I chips: ~35-70% Ladder Tests First Ladder Tests - VTT Chip 57 Chip 58 VTT Ladder2: Detector: 3.1µA @ 80V Chip 65 Chip 67 Chip 75 Cd-measurement Pixels with hits: chip Sr Cd 75 98.5 % 97.9 % 3 noisy pixel 67 94.1 % 94.2 % 2 noisy pixel 65 99.4 % 99.2 % 58 99.5 % 99.5 % 57 99.4% 99.5 % 1 noisy column pixel chip 9 The Readout System . pixel chip 0 . Temp. Sensors Pixel Bus pixel transmit Digita l Pilot Chip Analog Pilot G-link serializer& optics i Converter and control daughter card link receiver pixel converter pixel router busy, jtag pixelcontrol receive Pilot MCM pixelcontrol transmit L1, L2y, L2n, testpulse, jtag Control Room The Analog Pilot Chip •Designed by G. Anelli, R. Dinapoli, A. Kluge • Submitted: 19 April 2002 • First tests started beginning August 2002 • Only 2 boards available, new board in production 4 mm • Mixed mode • Power supply: 2.5 V • Power consumption (clocked): ~50mW 2 mm The Analog Pilot Chip: the architecture • Six 8-bit DACs for biasing the pixel chip • One 10-bit ADC (with a 16-input multiplexer) to monitor: Temperature Power Supplies Pixel chip DAC outputs Analog Pilot chip DAC outputs • Current sources for T monitoring • Voltage references for the on-chip DACs and ADC (can be bypassed) • JTAG controller The Analog Pilot Chip: first results References Simul. 1.5 Meas. 1.4 DAC_REF_MID 0.56 0.558 DAC_REF_VD D 1 0.998 ADC_ref_0 0.513 0.512 ADC_ref_1 1.925 1.918 v_bias 1.16 1.153 1.3 Output voltage [ V ] Reference name DACs scan 1.2 vo_TESTHI vo_TESTLOW vo_DRMID vo_GTLA vo_GTLD 1.1 1 0.9 0.8 0.7 0.6 0.5 0 •All references work well 32 64 96 128 160 192 224 256 Input code •Five out of six DACs work well •The JTAG and the digital part seem to work well Still to be tested: • Multiplexer + ADC • Temperature monitoring pixel chip 9 The Readout System . pixel chip 0 . Temp. Sensors Pixel Bus pixel transmit Digita l Pilot Chip Analog Pilot G-link serializer& optics i Converter and control daughter card link receiver pixel converter pixel router busy, jtag pixelcontrol receive Pilot MCM pixelcontrol transmit L1, L2y, L2n, testpulse, jtag Control Room The GOL Chip and the Digital Pilot Chip Digital Pilot Chip •Receives control signals from the control room •Controls all the chips on the MCM via JTAG •Reads data from the chips and sends them to the GOL chip •First prototype tested and fully functional Gigabit Optical Link serializer •Translates data into Glink compatible 800Mbit/s stream of data on an optical link, which will provide the connection from the MCM to the control room •It was already developed at CERN •It’s tested and fully functional Digital pilot test board Optical link (clk, data) Fast G-link Pixel chip Pilot chip Deserializer GOL chip Trigger/DAQ The MCM • First Prototype of the MCM board is ready Analog Pilot Digital Pilot GOL chip 5cm Lasers and PIN diodes The SPD Bus ± 193 mm ladder2 ladder1 Power supplies connector Extenders (Copper-capton) Flexible Extender 70.72 mm MCM 70.72 mm 2mm 11mm 7 SMD component 7 7 6 Wire bonds to the ALICE1LHCb chip 1000mm 5 4 3 7 6 5 240µm 7 layers Al-Kapton flex 2 2 1 1 PIXEL DETECTOR READOUT CHIP COOLING TUBE Michel Morel EP/ED Aluminum Polyimide Glue The SPD Bus As of today, we successfully tested: First Bus prototype with 10 mounted chips Ladder with 5 chips mounted on bus (with beam) Waiting for the Second Bus prototype M. Morel The pixel test system components VME Master JTAG Controller Pixel Carrier R/O Controller Pixel Carrier P. Chochula DAQ Adapter Pixel Chip DAQ Adapter Modular System based on VME Designed for wafer probing, chip, assemblies, ladders, bus studies and test beams Control software based mainly on Windows and LabView The test system software • This is the test beam version of the software Pixel Test beams July and September 2001 3 detector planes with single chip assemblies Studies of chip efficiency, thresholds and timings July 2002 5 detector planes in the beam (2 mini busses and a DUT) Tests of a thick assembly (300m) Tests of thin assembly (200m) Tests of a ladder (300m) Collection of data for simulation models tuning The Test beam Setup Minibus Tested Object Minibus Scintillators Online Measurements Ladder Threshold-scan Thin assembly Bias Scan Conclusions • The Front End chip has been extensively tested, and is now qualified to be used in the experiment • Assemblies and ladders have been produced and successfully tested with source measurements and during test beams (2001 and 2002) • All the components of the MCM are ready, even if they are still prototype versions •The first bus with 10 chips was successfully tested •The test system proved to be robust and extremely flexible •Next step: test of a half stave on a dedicated board
