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Behind the Numbers
Technology Hurdles for Next-Generation ICs
With each smaller process node, the cost and complexity of implementing a chip design
escalates. At the same time, new technologies are emerging to ensure that those chips
deliver the desired performance at ever-lower power levels. Yet each of those new
technologies comes with a price--whether it’s 10 or more levels of copper metallization,
strained silicon, multiple transistor types with different threshold voltages, or still other
enhancements. That price is increased complexity in both design and fabrication.
To add more levels of metal or new transistor structures, more mask layers are needed.
As more layers are employed, however, there will very likely be additional yield losses
due to manufacturing-related defects. Such defects can cause circuit failure. To handle
these issues during physical design, various techniques are increasingly applied at each
smaller process node. These techniques are loosely grouped into “design for yield”
(DFY) and “design for manufacturing” (DFM). Unfortunately, the techniques can
increase the design time as well as the design and physical-layout verification time. The
layout of a latch design can dramatically illustrate this point (see the figure). Designers at
IBM Corp. crafted a latch using typical layout approaches. They then redid the layout
using techniques to optimize it for manufacturability. The resulting design differs
significantly from the original layout in order to better accommodate DFM guidelines for
the lithography.
As stated, these techniques will add to the up-front design and verification time. In some
cases, they also may add slightly to the chip area. Yet these techniques can result in
significant savings if no respin of the chip is needed to correct a design problem that
wasn’t caught before the chip was released to manufacturing. In this case, companies
save the cost of creating a new mask set. For a 65-nm process, that mask set could cost
several million dollars. In addition, the companies could improve their time to market by
months by getting the design right the first time. Missing a market window doesn’t just
delay the introduction of the product. It also can cost 20% or more of a product’s lifetime
revenue, as the best profit margins are usually achieved when the product beats the
competitors to market--when there’s little or no competition.
Chip area is a very valuable commodity. The smaller the chip, the more manufacturable it
is and the more chips that can be fabricated on a wafer. When several DFM techniques
are implemented in a design, chip area tends to grow. Such increased area will raise chip
cost. These DFM techniques include redundant vias (extra connections from metal layer
to metal layer to ensure that connections are made from layer to layer) and wire spreading
(increasing the spacing between wires on a metal layer to prevent shorts due to
lithography limitations).
In some complex chips like advanced microprocessors, systems-on-a-chip (SoCs), and
multi-megagate field-programmable gate arrays (FPGAs), designs are interconnectlimited. The problem is the large number of on-chip buses on processors and SoCs. In
addition, a lot of configurable interconnect is needed to improve FPGA-gate utilization.
Rather than grow the horizontal area to accommodate more wiring, designers have been
adding more and more layers of metal. Their goal is to compensate for area increases due
to the application of DFM and DFY guidelines while keeping the chip area to a highly
manufacturable size. The latest FPGAs, such as the Virtex 5 family from Xilinx, employ
as many as 12 levels of metallization. Such a large number would’ve been unimaginable
a decade ago.
Thanks to advances in chemical mechanical polishing and copper damascene deposition
technologies, however, such large numbers of metal interconnect layers are now
practical. For smaller chips, the use of four to eight layers of metal also can play an
important role in reducing chip area. Think of this in terms of valuable real estate in, say,
New York or Tokyo: Architects build skyscrapers on small plots of land to minimize the
area. This is one way to keep the chip size from growing even though there are more
transistors on a chip. Even though it costs more to build vertically, that cost is offset by
the smaller chip area and larger number of chips that can therefore fit on a wafer. This
aspect of chip design requires careful tradeoff analysis to determine the most costeffective combination.
As process features drop below the 65-nm node, DFM and DFY approaches may not be
enough to ensure that chips will work the first time through the fabrication line. Many
companies are advocating the use of restricted design rules (RDRs) at 45 nm and below.
In the RDR approach, the tools will actually limit what a designer can do so that physical
circuit design becomes correct by construction. This approach will greatly improve the
ability to get working chips the first time through the manufacturing line.
--- Dave Bursky, Contributing Editor, Chip Design Trends