Download Design of CMOS Active Inductor for High

International Journal of Applied Sciences, Engineering and Management
ISSN 2320 – 3439, Vol. 04, No. 05, September 2015, pp. 52 – 59
Design of CMOS Active Inductor for High-Frequency
Applications
Dosapalli Mallikarjun1, V. V. V. S. Prasad2
M. Tech Scholar, JB Institute of Engineering and Technology, Hyderabad.
2
Associate Professor, JB Institute of Engineering and Technology, Hyderabad.
1
Abstract: The potential of active inductors (AIs) has been often reduced by lack of accurate design
methodologies and limitations due to the inherent noise sources. This paper deals with these two open issues for
a high-frequency CMOS AI characterized by high-quality factor, low-power consumption, and low noise. First,
it reports an effective design methodology for the implementation of high-frequency CMOS AIs with a
highquality factor. In particular, it shows how, through an advanced small-signal circuit model, to carry out an
accurate and reliable design at high frequency (over 30 GHz) in modern nanoscale CMOS process. The design
methodology is validated through cases of study at 30 GHz implemented in a standard 180-nm CMOS process
and characterized experimentally.
Keywords: active inductors, inherent noise sources, high-frequency CMOS AI, reliable design.
INTRODUCTION
The evolution of CMOS microelectronic technology over the years has allowed integration of communication
systems on a single chip. Scaling of transistors over the years, a case of Moore’s law has resulted in a decrease
in channel length. The following figure illustrates the decrease of transistor´s channel length over the years:
Fig. 1: CMOS integration
Channel length is taken as the reference geometrical parameter in a CMOS technology node. All geometrical
dimensions in a circuit are considered to be scaled according to the channel length. Therefore, the decrease in
channel length has led to integration of more and more transistors on a single chip and has also led to the
decrease in the area of chip, which also has reduced the cost. In digital devices, the minimum channel length has
gone upto 20nm, but in analog devices, the minimum channel length has gone upto 45nm. In general, this
decrease is component size has allowed the integration of more circuitry -and more functionality- in a single
chip. Today, complex communication systems, including radiofrequency transmitters and receivers, digital
processing, processors and mamories, can be produced in a single silicon die.
Indeed, there is a critical need for inductive characteristics in high-speed applications. CMOS spiral inductors
have found a broad range of applications in high-speed analog signal processing and data communications. But
integrated spiral inductors have a number of limitations due to their layouts. These limitations are low quality
factor, low self resonance frequency, small and non tunable inductance and need for very large silicon area [1].
Implementation of inductors with active elements, offers several attractive advantages over their spiral
counterparts including large and tunable inductance and low silicon consumption. Unfortunately active
inductors have high level of noise due to using a number of transistors. One of the applications of inductive
characteristic is LC oscillator. Using the active inductor in LC oscillator increases the phase noise of it. Whereas
the most important characteristic in an oscillator is phase noise, this high level of noise restricts use of active
inductors in oscillator. Another limitation of LC oscillators with integrated spiral inductors is their narrow
tuning range. In these oscillators, frequency tuning is carried out by a varactor instead of capacitor.
Theoretically, the VCO tuning range is determined by the maximum-to-minimum capacitance ratio of the
varactor (Cvar,max/Cvar,min). For a typical capacitance ratio in astandard CMOS process, the tuning range of
LC-tank VCOs is approximately limited within 30% making them unattractive for wideband applications [2]-
IJAEM 040508 Copyright @ 2015 SRC. All rights reserved.
Design of CMOS Active Inductor for High-Frequency
High Frequency Applications
[5]. Several techniques have been proposed to enhance the tuning range of the LC-tank
LC tank VCOs such as switched
capacitors and switched inductors. However a wide frequency tuning range can be achieved in cost of additional
add
circuits with considerable increase in the chip area and complexity of control mechanism [6], [7]. LC oscillators
based on active inductors overcome their limitation in tuning range [8-9].
[ 9]. By utilizing a differential active
inductor for the LC-tank,, the circuit exhibits a very wide frequency tuning range. In this paper we present a new
active inductor with wide tuning range and low noise performance. It is shown that added local common mode
feedback scheme to conventional active inductor, reduces the
the noise as a common mode signal in its terminal.
The proposed oscillator base on new active inductor shows better phase noise performance compared to the
conventional oscillators [10].
LITERATURE
Despite several circuits and techniques were already proposed
proposed and investigated, the term active inductors ( AIs),
appeared in the title of a paper in the early 1970s [2]. Later, efficient implementations of selective active filters
on silicon, i.e., bipolar technology, were proposed in the 1990s, see [3] (other references
references therein). Some of the
most recent and representative CMOS solutions proposed in the literature are reported in [4]–[15],
[4]
including
also implementations for highspeed serial data link [13] and low-frequency
low frequency applications [14]. One of these AIs
is the boot-strapped
strapped inductor (BSI) [15]. This circuit exhibits a tunable equivalent inductance associated with
high-quality factor, low-noise
noise and lowpower consumption [16], [17]. In particular, lowlow-noise amplifier (LNA)
[18], RF switch [19], [20], and voltage controlled oscillator (VCO) were successfully implemented using the
BSI circuit. The effectiveness of this AI in terms of equivalent inductance, quality factor, linearity, and power
consumption has been also verified experimentally [17], including the case
case of its application to the
implementation of lownoise and high-quality
high
factor LC tank in VCO.. However, an effective design
methodology validated by experimental evidences, in advanced CMOS technology nodes for implementations at
frequencies higher than 10 GHz, as well as an analytical proof of its low-noise
low noise contribution through a circuit
analysis have not been provided yet.
DESIGN METHODOLOGY
In principle, the BSI circuit consists of an integrated transformer and a current amplifier [15]–[17].
[15]
It exploits
the current amplification between the two spirals of the integrated transformer to boost up the equivalent
inductance seen from the terminals of the AI and its quality factor. The equivalent inductance is proportional to
the amplification of the transconductance stage. The BSI-based
BSI based AIs have been designed on silicon both in
bipolar [18]–[20] and CMOS [15]––[17] processes. Analogies and differences
es between the bipolar and CMOS
implementations are discussed in [15] and [16], and therefore they will not be repeated herein. However, for
reasons of self-consistency,
consistency, it is worth reporting the latest circuit implementation in CMOS technology [17]
shown in Fig. 1. The transistors M1 and M2 perform the current amplification implemented in practice by means
of a cascodetransconductance stage. If the terminal 2 is grounded, a varactorC
varactor R can be introduced to perform a
tuning of the equivalent impedance Z12.
A. Design Equations
In [16], it has been shown that the equivalent circuit of the active inductor obtained by considering only the
gate-source capacitance CGS and the transconductanceg
transconductance mof the MOSFET does not lead to an accurate design
over 7 GHz. Thereby in [16], the MOSFET has been replaced by the simplified small-signal
small signal equivalent circuit
reported in Fig. 2. Such an equivalent circuit has been achieved from more complex and accurate circuit
circu models
at high frequency by introducing some simplifications applicable
applicable in the cases of interest [16]. In particular, this
small-signal
signal equivalent circuit considers the capacitances between gate and drain (C
( GD) and between drain and
source (CDS), the gate resistance (R
RG),, and the substrate subnetwork, including the bulk resistance, the sourcebulk, anddrain-bulk
bulk capacitances (R
( B, CSB, and CDB),, which may play a relevant role in the AI circuit
performance.
Fig. 2. Simplified ac equivalent-circuit
equivalent circuit of the MOSFETs at high frequency.
International Journal of Applied Sciences, Engineering and Management
ISSN 2320 – 3439, Vol. 04, No. 05, September 2015, pp. 52 – 59
Dosapalli Mallikarjun, V. V. V. S. Prasad
Fig. 3. Advanced small-signal equivalent-circuit
circuit of the CMOS AI in [16]. C GS1, CGD1, and gm11 are the gate-source
gate
capacitance, gatedrain capacitance, and transconductance of M1, respectively. L1 and R1, and L2 and R2,
2, are the inductance and parasitic resistance
resi
of the
primary and secondary spirals of the transformer, respectively. ZC, ZP, and AV are given by (1)–(4).
(1)
It is worth emphasizing that the objective is not obtaining an extremely accurate model of the MOSFET (this is
already available within the Cadence design environment), but to reduce the complete and accurate device
model to a relatively simple ac equivalent circuit of the MOSFET so that it can be used to derive an equivalent
circuit of the AI, from which it is possible to obtain a set of design
design equations that are still manageable and able
to capture the main performance in the typical cases of interest. In particular, in [16] it is shown how in the
practical cases of our interest RG and RB can be neglected, as well as CDS and CDB of M2, still providing an
adequate description of the circuit behavior. For convenience, the advanced equivalent circuit of the AI is
reported in Fig. 3
AV(jω)
(jω = gm2 (jωL2 + R2)
(1)
Z P = (RR + jωLR)1/(jωCR)
(2)
ZC = 1/(gm2 + jωCPAR)
(3)
CPAR
PAR = CDS1CDB1CSB2CGS2
(4)
whereω is the angular frequency, L2 and R2 are the inductance and parasitic resistance of the secondary spiral
inductor of the integrated transformer, respectively, RR is the parasitic resistance of the additional spiral inductor
LR, the indexes 1 and 2 in transconductance and parasitic capacitances refer to the MOSFETs M1 and M2,
respectively.
In the practical cases, the design requires a set of rules useful to carry out the circuit synthesis. The typical
approach to the design of ann active inductor requires an inductance L12 = L0 and a quality factor Q = Q0 at the
operating frequency f = f0. Thus, for our AI we consider the following design specifications and entries:
1) operating frequency ( f0);
2) equivalent inductance L12 at f0 (L0);
3) quality factor of L12 at f0 (Q
Q0);
4) quality factor and coupling factor of the two spirals of the integrated transformer (depending on
technology process and geometry);
5) budget of power consumption (P
( C).
From (7)–(9), ZIN and the quality factor Q depend on the values of the circuit elements: L1, L2, LR, M,CR, and
gm(assuming that gm1 = gm2 = gm) and the most relevant parasitic components associated with the MOSFETs. The
assumption on g m simplifies the design equations and also corresponds with good
good approximation (despite the
body effect) to the typical practical case, i.e., same aspect ratio and bias current for M1 and M2 of the
cascodetransconductance stage.
As a first consideration, it is worth noting that the power budget allows the derivation of
of the maximum value of
transconductancegmand the area size of the MOSFETs. The current density for the maximum oscillation
frequency ( fmax) and maximum cutoff frequency ( fT) are two invariants of the MOSFETs in modern
m
CMOS
processes ; they are close each other, and equal to 0.2 and 0.3 mA/µm,
mA/ m, respectively. In addition, the fmaxand
fTcurves are quite flat over such a current density range. Their actual expressions contain additional terms with
respect to the widespread simplified expressions, resulting less intuitive. In particular, in [31], it is observed that
CGS and CGD are monotonically
cally increasing functions of IDS, and that fTreaches its peak as a function of current
density ID/W slightly before gmreaches its peak. Thereby, it is possible considering that a current density of about
0.3 mA/µm could lead to gmclose to the peak value. A higher power consumption can lead to a wider design
space of the active inductor in terms of gm. In case of very low-power
power budget, the resulting transistor width
could be very small, leading to potential device mismatch and design reliability problems. In
I such a case, if gmis
not critical, a lower current density can be considered as a tradeoff between gmand reliability. A larger transistor
width is also beneficial for the linearity.
International Journal of Applied Sciences, Engineering and Management
ISSN 2320 – 3439, Vol. 04, No. 05, September 2015, pp. 52 – 59
Design of CMOS Active Inductor for High-Frequency Applications
DESIGN METHODOLOGY
In this section, we present an effective algorithmic design methodology that considers the relevant parasitic
components in order that the AI circuit design meets the specifications with adequate accuracy and reliability.
To validate the approach proposed, the methodology is applied to cases of study at 13 GHz in 90 nm bulk
CMOS process by ST-microelectronics. Following our design specifications, two versions of an AI, one single
ended and one differential have been designed to exhibit an equivalent inductance equal to 1.6 and 3.2 nH, with
a power consumption of 1 and 2 mW, respectively. The two versions are reported and discussed hereinafter,
with the aim of providing the details of the design flow implementation that could be adopted also in other
practical cases.
A. Single-Ended AI
The AI circuit has been designed according to the criteria reported in Section II, considering an equivalent
inductance L12 of 1.6 nH and a quality factor (Q) of about 200 ( i.e., about one order of magnitude higher than
those achievable by spiral inductors on standard silicon process), at 13 GHz, with a power budget (PC) of 1 mW.
1) Practical Considerations: First, it is worth considering preliminarily some practical design aspects. To relax
the design complexity, it is convenient that the self-inductances L1 and L2 (i.e. the two spirals of the
transformer), and LR have approximately the same value L (L1 = L2 = LR = L).
This is directly related with the EM design of L1 and L2, i.e., corresponding to a one-to-one transformer. In other
terms, the EM design can be carried out by starting from the same form factor for all the spirals. A different
ratio is possible, but could lead to a slight complication in the physical design of the integrated transformer and
could require a larger number of iterations (time consuming EM simulations). The unity ratio L1/LR is also
related with some useful simplification in the analytical equations [15], [16]. However, it is worth considering
that, at a given frequency, higher values of inductance are associated to lower quality factors. In addition, in
integrated circuit design is always better to have expressions depending on the same aspect ratio of
homogeneous parameters to reduce the impact of the device mismatches. Thereby, a unity ratio L1/LR could also
be the first reasonable choice.
SIMULATION RESULTS
Figure 4. Electric binary user interface.
International Journal of Applied Sciences, Engineering and Management
ISSN 2320 – 3439, Vol. 04, No. 05, September 2015, pp. 52 – 59
Dosapalli Mallikarjun, V. V. V. S. Prasad
Figure 5. Open the library file for inductor
Figure 6. Basic active inductor
International Journal of Applied Sciences, Engineering and Management
ISSN 2320 – 3439, Vol. 04, No. 05, September 2015, pp. 52 – 59
Design of CMOS Active Inductor for High-Frequency
High Frequency Applications
Figure 7.. Advanced active inductor
ind
with modified capacitance
The AI circuit is alternated by changing the values of capacitor and Inductor values keeping constant. Achieved
frequency is 35.7 GHz.
Figure 8. High Frequency 13GHz AI (Active Inductors)
In this Paper high frequency Boot Strap Inductor is designed which is basic which is for medium frequency
below 10GHz which is shown in above figure.
International Journal of Applied Sciences, Engineering and Management
ISSN 2320 – 3439, Vol. 04, No. 05, September 2015, pp. 52 – 59
Dosapalli Mallikarjun, V. V. V. S. Prasad
Figure 9.
9 High Frequency 35 GHz AI (Active Inductors)
The change the values of Inductor
or to achieve frequency change. Change the quality factor of the Inductor L1
and L2 and this can be done only in Process variations.Using
variations.
Active Inductor AI for more than 13GHz
frequency is used. Which
hich is shown in above figure. This methods are existing methods explained and proposed
method in this.
CONCLUSION
The
he effective design methodology has been addressed to implementations at very high frequency in an advanced
CMOS technology node, allowing us to overcome the limitations of the previous designs. The proposed design
methodology has been implemented using a small-signal
signal equivalent circuit proposed previously, and
considering the equivalent inductance, quality factor, operating frequency, and power consumption as the main
design entries. It considers the relevant parasitic components and practical aspects of the
the design implementation
in advanced CMOS technology nodes. The design criteria have been presented, discussed and applied to several
designs at 35 GHz in a 180-nm
nm bulk CMOS process.
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International Journal of Applied Sciences, Engineering and Management
ISSN 2320 – 3439, Vol. 04, No. 05, September 2015, pp. 52 – 59