Download An Ultra-Wideband Self-Calibrating Frequency Divider

2015, 4th International conference on Modern Circuits and System Technologies
An Ultra-Wideband Self-Calibrating Frequency
Divider for Multi-GHz PLL Applications
L.Mountrichas, P.Athanasiadis, S.Siskos
Electronics Laboratory, Physics Department
Aristotle University of Thessaloniki
Thessaloniki, Greece
[email protected]
Abstract— An ultra wide band frequency divider by 4 is
implemented operating at mm-wave frequencies, with emphasis
on low power dissipation. The proposed divider is designed in
TSMC 65 nm CMOS technology using 1V power supply. The
proposed divider achieved a locking range from 15GHz to 60GHz
with maximum power dissipation of 6.46mW.
Keywords—frequency divider; ultra wide band; low power;
mm-wave.
I. INTRODUCTION
Nowadays, research activity in development of mm- wave
applications systems is intensive. Both frequency spectrum
saturation used by telecommunication systems and demands
for higher transmission data rates lead to that direction.
Millimeter waves promise much higher data rates than
microwaves, making applications such as improved WiFi,
radar on chip or HD video transmission achievable. Based on
that PLL is the heart of modern telecommunication
applications, an effort to improve its performance at multi GHz
band, took place. Frequency dividers optimization is a step
towards this direction. Commonly used frequency divider
architectures for GHz applications are based on current mode
logic (CML) latches or injection-locked topologies. The above
architectures come with drawbacks such high power
dissipation, large silicon area consumption or narrow frequency
dynamic range. Attempting to improve upon those
characteristics, this work presents a frequency divider capable
of operating at mm waves, with low power dissipation, and
ultra wide locking range. This divider is ideally suited for
multi-VCO PLLs.
II. DIVIDE BY 4 ARCHITECTURES
A. Existing Divider Topologies
Frequency dividers based on classic CML architecture are
widely used for GHz applications. Although CML provides
wide frequency dynamic range at high frequencies, it suffers
from high power dissipation.
On the other hand, dividers based on injection-locked
topology integrate coils, leading to narrow frequency dynamic
range but in addition consume large area on chip. An
improved version of CML topology [1], based on dynamic
latches with load modulation is depicted in Fig. 1.
Fig. 1. Dynamic latch
Using the dynamic latch of Fig. 1, the track phase is
achieved by setting the pmos loads to triode region. The latch
phase is achieved by forcing the loads to cut-off region,
holding the tracked value taking advantages of the output node
parasitic capacitance. This latch version results in a low-power
high frequency divider, an important improvement over the
classic topology. Cascading four latch stages a divide by 4
circuit is created as illustrated in Fig. 2. According to [1],
Vbiasp controls the self-oscillation frequency of such a
divider. As a result, the same circuit can operate divide at a
variety of frequency bands by simply changing the pmos bias
voltage.
B. Proposed Divider
Based on the topology of dynamic latches with load
modulation, this work proposes an ultra wide band low power
frequency divider. Such a wide locking range is accomplished
by introducing a control unit that dynamically changes the bias
voltage of the pmos loads.
Fig. 2. Synchronous Divider by 4
2015, 4th International conference on Modern Circuits and System Technologies
A modification was applied in divider of Fig. 2 in relation
to the latches of Fig.1. Instead of using one ac coupling circuit
per latch for the pmos load modulation, the divider in Fig.2
uses only two, consuming less space and adding less parasitic
effects. Fig.3 illustrates the RC circuits that generate the
appropriate signals for dividers input.
Charge
Pump
PFD
Control
Unit
C
CLKn
Divider
CLKp
Fig. 4. Proposed divider in a PLL
R
Vbiasp
Control Unit
The purpose of the control unit is to map the CP voltage /
VCO frequency pair to the appropriate bias. This is
accomplished by the circuit illustrated in Fig.5
R
C
CLKn
LPF
CLKp
Fig. 3. Clock generation circuit
VDD
CPout
The above remark implies that each latch of the divider of
Fig.2 is being composed only by transistors M1 to M5 of Fig.1
while Fig.3 circuit is used by all four latches. Signals CLKp
and CLKp in Fig. 2 modulate the pmos loads M3, M4
whereas CLKn and CLKn are applied to the gate of M5.
Simulation results of the proposed divider are presented in
Table I
Results of Table I show that the proposed divider is fully
operational from 15GHz to 60GHz provided that the bias
voltage for the pmos loads changes appropriately. Idc in Table
I corresponds to the current of a diode connected pmos that
provides Vbiasp.
That feature of dynamic latches is exploited in order to
implement an ultra wide range frequency divider for PLL
applications.
TABLE I.
PROPOSED DIVIDER MIN-MAX INPUT FREQUENCY
Idc
Vbiasp
Fmin
Fmax
(μA)
(mV)
(GHz)
(GHz)
110
600
15
25
440
400
57
60
III. CONTROL UNIT
In a phase locked loop, a dc voltage generated from the
charge pump controls the VCO output frequency. By utilizing
a control circuit, the charge pump (CP) voltage can be used to
control the pmos load bias voltage of a dynamic latch based
divider, thus achieving an automatic dynamic calibration of
the circuit’s self oscillation frequency. That way it is possible
to extent the locking range of the divider without human
intervention, making the proposed circuit ideal candidate for
low-power ultra-wide range PLLs. In Fig. 4 the PLL
architecture utilizing the proposed divider is illustrated. The
added control unit uses the filtered CP output to set the bias
voltage of the divider.
M1
-
M2
M5
M3
M4
Vbiasp
Op
+
Idc
R1
Ibias
Fig. 5. Control Unit
The operational amplifier and M1 implement a controlled
current source. The generated current is mirrored through M2,
M3 and M4 to the diode connected transistor M5 creating the
desirable bias voltage, Vbiasp for the modulation of the pmos
loads in the latches. R1 and Ibias are used to calibrate the
control unit in order to work in unison with the application
specific VCO and Charge pump. The resistor sets the current
slope, effectively matching the bias current to the slope of the
VCO. The additional current source sets the minimum current
when the CP output would be zero. In effect it sets the initial
value of the current. The Idc value is given by equation (1).
I dc = I bias +
CPout
R1
(1)
Using the data from Table I the appropriate value for Ibias
and R1 can be calculated. If the working range of the charge
pump is from 100mV to 1V and the VCO output frequency for
that range is 15GHz to 60GHz then solving equations (2) and
(3), the appropriate values for Ibias and R1 can be calculated.
0.1
= 100uA
R1
1
I bias +
= 440uA
R1
I bias +
(2)
(3)
For the above formulas it is assumed that if charge pumps
output is at 0.1V then VCO will generate its lowest frequency
(15GHz for this case), while for 1V the VCO will generate its
maximum frequency (60GHz).
By using equation (1), the control unit can be matched to
2015, 4th International conference on Modern Circuits and System Technologies
any VCO / CP pair making the proposed divider a universal
solution for mm-wave PPLs. The divider can easily be
incorporated in multi-VCO PLLs such the one presented in
[2]. A simplified block diagram is illustrated in Fig. 6. Using
the proposed divider in such PLLs considerably minimizes the
current consumption and the occupied area by eliminating the
need for extra dividers and their associated buffers
CP
LPF
VCO1
Divider1
.
.
.
.
.
.
VCOn
Dividern
.
.
.
M
U
L
T
I
P
L
E
X
E
R
TABLE II.
POWER DISSIPATION VARIATION FROM 15GHZ TO 60GHZ
Fin (GHz)
Power (mW)
15
4.3
20
5.0
25
5.5
30
5.8
40
6.3
60
6.5
(a)
CP
VCO1
LPF
.
.
.
VCOn
M
U
L
T
I
P
L
E
X
E
R
Divider
(b)
Fig. 6. (a) Typical Multi-VCO PLL, (b) Multi-VCO PLL utilizing the
proposed divider
Fig. 8. Fout waveform for Fin @15GHz
IV. SIMULATION RESULTS
Simulations results of a dynamic latch based divider
controlled by the circuit of Fig. 5 confirm the validity of our
claims. The ultra-wide dynamic range of the divider is shown
in Fig. 7.
Fig. 9. Fout waveform for Fin @60GHz
Fig. 7. Fin vs Fout
As expected for such a wide locking range the power
dissipation varies. Table II presents the power dissipation for
various frequencies in the range of 15GHz to 60GHz. As
indicated from the results the power dissipation varies
aggressively at the lower frequency range, while remaining
almost constant at the upper end of the operating frequencies.
Furthermore, Fig.8 and Fig.9 depict the divider output
waveforms for input frequencies of 15GHz and 60GHz
respectively.
As expected the output swing drops at high frequencies.
The divider was used to drive a dual modulus divider, also
implemented with dynamic latches. Simulation results confirm
that the proposed divider is fully capable of driving a
following division stage, as would be the case in a PLL.
Finally, the divider phase noise simulation results are
illustrated in Fig. 10. The divider’s phase noise for a 15GHz
input frequency is -143dB at 1MHz offset and -147dB at
10MHz offset. For a 60GHz input frequency the divider
exhibits slightly larger phase noise, -137dB at 1MHz offset
and -144dB at 10MHz. The above phase noise values are
comparable to the state-of-the-art mm-wave frequency
dividers.
2015, 4th International conference on Modern Circuits and System Technologies
TABLE III.
SIMULATION RESULTS COMPARISON TO THE STATE-OF-THEART
fmin-fmax
(GHz)
L.R.
(%)
Pdiss
(mW)
Tech
CMOS
(nm)
FoM
(GHz/mW)
4
14 -70
60-90
1.3-4.8
32
6.67-17.5
4
79.7-81.6
2.4
12
65
0.16
[4]
4
62.9-71.6
3.2
2.8
65
0.82
[5]
4
82.5-89
7.6
3.0
65
2.17
[6]
4
67-72.4
7.7
15.5
65
0.35
[7]
This
work
4
58.5-72.9
21.9
2.2
65
6.55
4
15-60
120
4.3-6.5
65
6.9 - 10.45
Ref
fin/fout
[1]
[3]
low power dissipation and the ultra wide locking range. Power
dissipation is comparable or better than the state-of-the-art,
reaching its maximum at 6.46mW in order to perform division
of 60GHz signal and its minimum at 4.3mW for 15GHz input
signal. The achieved locking range is 15GHz to 60GHz is far
wider than other published mm-wave frequency dividers and
resulted through the use of a control circuit which
continuously calibrates the proposed divider.
ACKNOWLEDGMENT
This research is co-financed by Hellenic Funds and by the
European Regional Development Fund under the Hellenic
National Strategic Reference Framework 2007-2013,
according to Contract no. 11SYN_6_100 of the Project “An Eband / mmwave CMOS RFIC/MMIC implementation for
future private networks and mobile backhaul radio
applications” within the framework “Cooperation 2011”.
REFERENCES
[1]
Fig. 10. Phase noise analysis
Closing, it is important to compare the proposed low-power,
ultra-wideband divider, to the state-of-the-art of mm-wave
dividers in order to gain a better picture.
Table III illustrates the basic characteristics of a frequency
divider. It’s important to mention that measurements of
reference [1] represent two different states of the same circuit,
which are accomplished by manually changing the dc voltage
that modulates the pmos loads.
Table III results show that compared to other published
frequency dividers, the achieved locking range of this work is
much wider. The 120% locking range percentage is much
higher than other dividers. The varied current consumption
makes the comparison slightly difficult, since the typical
Figure of Merit (FoM) does not apply. Using both the
minimum and maximum power dissipation, it is found that the
proposed divider achieves the largest FoM, excluding that of
[1] which uses manual calibration.
V. CONCLUSION
In conclusion, this work resulted in a new frequency divider
by 4, having an ultra-wide locking range, implemented in
65nm CMOS technology at 1V power supply. The proposed
divider is based on dynamic latches with load modulation and
is designed for PLL applications, specifically those utilizing
multiple VCOs and dividers. The divider main features are the
A. Ghilioni, A. Mazzanti and F. Svelto, "Analysis and Design of mmWave Frequency Dividers Based on Dynamic Latches With Load
Modulation," Solid-State Circuits, IEEE Journal of, vol. 48, pp. 18421850, 2013.
[2] Yikui Jen Dong and F. Zhong, "A self-calibrating multi-VCO PLL
scheme with leakage and capacitive modulation mitigations," in Circuits
and Systems (ISCAS), 2013 IEEE International Symposium on, 2013, pp.
1400-1403.
[3] P. Mayr, C. Weyers and U. Langmann, "A 90GHz 65nm CMOS
injection-locked frequency divider," in Solid-State Circuits Conference,
2007. ISSCC 2007. Digest of Technical Papers. IEEE International,
2007, pp. 198-596.
[4] K. Yamamoto and M. Fujishima, "70GHz CMOS harmonic injectionlocked divider," in Solid-State Circuits Conference, 2006. ISSCC 2006.
Digest of Technical Papers. IEEE International, 2006, pp. 2472-2481.
[5] Chung-Chun Chen, Hen-Wai Tsao and Huei Wang, "Design and
Analysis of CMOS Frequency Dividers With Wide Input Locking
Ranges," Microwave Theory and Techniques, IEEE Transactions on,
vol. 57, pp. 3060-3069, 2009.
[6] Chao-An Yu, Tang-Nian Luo and Y. -. E. Chen, "A V-Band Divide-byFour Frequency Divider With Wide Locking Range and Quadrature
Outputs," Microwave and Wireless Components Letters, IEEE, vol. 22,
pp. 82-84, 2012.
[7] Liang Wu and H. C. Luong, "Analysis and Design of a 0.6 V 2.2 mW
58.5-to-72.9 GHz Divide-by-4 Injection-Locked Frequency Divider
With Harmonic Boosting," Circuits and Systems I: Regular Papers,
IEEE Transactions on, vol. 60, pp. 2001-2008, 2013.