Download Homework #3 Solution

Homework #3 Solution
1. In a particular cascaded current mirror, such as that shown at the right, all
transistors have Vt=0,6V, µnCox=160
=160µA/V2, L=1µm, and VA=10V. Widths
W1=W4=4µm, and W2=W3=40µm.
µm. The reference current IREF is 20µA. What
output current results? What are the voltages at the gates of Q2 and Q3?
What is the lowest voltage at the output for which current
current-source operation is
possible? What are the values of gm and ro of Q2 and Q3? What is the output
resistance of the mirror?
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Homework #3 Solution
2. Find the output resistance of the double
double-cascode current mirror below.
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Homework #3 Solution
3. Show that the input resistance (R
R seen at V3 node
node)) for the Wilson MOS mirror shown at right is given
by 2/gm. Assume that all three transistors are identical and neglect the Early effect. (Hint: Use a test
source and find the Thevenin equivalent resistance)
V3
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Homework #3 Solution
4. (a) For the circuit below, assume BJTs with high β and vBE=0.8V at 1mA. Find the value of R that will
result in Io=10µA.
(b) For the design in (a), find Ro assuming β=100 and VA=50V.
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Homework #3 Solution
5. If the pnp transistor in the circuit below is characterized by its exponential relationship with a scale
current IS show that the dc current I is determined by IR=VTln(I/ IS). Assume Q1 and Q2 to be
matched and Q3, Q4, and Q5 to be matched. Find the value of R that yields a current I =100µA. For the
BJT, VEB=0.7V at IE = 1mA. (worth 2 problems)
+
VEB
-
+
VR
-
VEB6=VR
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Homework #3 Solution
6. Design a bipolar differential amplifier such as that below to operate from ±2.5V
2.5V power supplies and
to provide differential gain of 40 V/V. The power dissipation in the quiescent state should not exceed
2mW.
(a) Specify the values of I and RC. What dc voltage appears at the collectors?
(b) If β=100,
=100, what is the input differential resistance.
(c) For vid=20mV,
20mV, what is the signal voltage at each of the collectors?
(d) For the situation in (c), what is the maximum allowable value of the input common mode voltage,
VCM? Recall that to maintain an npn BJT in saturation, VB should not exceed VC by more than 0.4V.
(a)
(b) Rid=2rπ where rπ=β/gm=(100(25m)
(25m))/0.2m=12,500Ω
Rid=2(12,500)=25kΩ
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Homework #3 Solution
7. Find the voltage gain and input resistance of the amplifier below assuming that β=100.
=100.
8. Consider the basic bipolar differential circuit in which the transistors have β=100
=100 and VA=100V, with
I=0.5mA, REE=200kΩ, and RC=20kΩ
Ω. Find:
(a)
(b)
(c)
(d)
the differential gain
the differential input resistance
the common-mode gain
the common-mode
mode rejection ratio
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Homework #3 Solution
(c) Acm=vod/Vicm=Rc/(2REE+rπ/β+1)=20k/(2*200k+10,100/(101))=14mV/V
=
=20log10|200/14m|=83dB
9. It is required to design a bipolar differential amplifier to provide the largest possible signal to a pair of
10kΩ load resistances. The input differential signal is a sinusoid of 5mV peak amplitude, which is
applied to one input terminal while the other input terminal is grounded. The power supply available is
10V. To determine the required bias current I, derive an expression for the total voltage at each of the
collectors in terms of VCC and I in the presence of the input signal. Then impose the condition that both
transistors should remain well out of saturation with a minimum VCB of approximately 0V. Thus
determine the required value of I. For this design ,what differential gain is achieved? What is the
amplitude of the signal voltage obtained between the two collectors? Assume α≈1.
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Homework #3 Solution
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