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Secondary Power Routing Issues
Let’s start this article with a brief introduction on what secondary power routing is.
Whenever a standard cell requires more than one power supply to function, the extra power
supply is called as secondary power. Consider a standard cell placed in a switch-able
domain but which needs to remain in ON state when that domain is switched OFF. An extra
power connectivity needs to be provided to this cell such that it remains in ON state even if
its corresponding domain is powered OFF. Such a routing is called secondary power routing.
A few examples of such cells are: Level Shifter cells, State retention cells, always-ON cells,
Isolation cells etc.
Secondary routing requires careful treatment since they can result in scenarios that
adversely affect IR drop or overall power consumption. A few issues that arise during
secondary routing and their impact are listed below.
1. Lots of jogs:
If secondary power routes jog up and down through many layers dropping lots of vias,
the increased resistance causes high voltage drop.
2. Lower Layer Routing:
Ideally power routing should not be done on lower routing layers. Secondary power
routing should not go below the layer on which the cell’s secondary power pin is present.
Lower metal layers cause high resistance in the path.
3. High Fanout:
When a single power net drives a large number of standard cells, the increased fanout
load will cause dynamic and static voltage drop.
4. Routing through pins of a standard cell:
When the secondary power net for a cell is routed through pins of similar cells placed in
a cluster, this will result in large dynamic drop since the width of these pins is less. This
is shown in Figure 1.
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Figure 1: Routing through pins
5. Not tapping to the nearest stripe:
If the secondary power net is not tapped to the nearest stripe then it will take a longer
path to tap to a source resulting in increased resistance and high IR drop. This is shown
in Figure 2.
Figure 2. Long route to power stripes
6. No / Incorrect NDR:
When secondary power nets are not routed using any NDR (ie. default metal width, layer
and via type are used), it will give high resistance as power routing needs special
attention whether it is primary or secondary.
7. Congestion:
When all the signal nets and clock nets are routed, during ECO, the newly inserted cells
which require secondary power nets face congestion issues and will not be able to follow
NDR and will be forced to take many jogs which again results in high resistance.
8. Grid Issues:
When grid issues cause shorts, dangling nets, missing via and stripes-not-stretched-tillcore-boundary etc., secondary power will not be routed properly. As an example, due to
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missing vias the net may not be tapped to the nearest vertical stripe resulting in a longer
route and higher resistance.
By: Gaurav Jain
BlackPepper Technologies
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